NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/test_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BIT_GEN(0)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(1)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(2)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(3)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(4)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(5)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(6)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(7)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_4_REG_COMP	100.0 % (2/2)	N.A.	100.0 % (60/60)	100.0 % (6/6)	N.A.	N.A.	100.0 % (68/68)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_4_REG_COMP

100.0 % (2/2)

N.A.

100.0 % (60/60)

100.0 % (6/6)

N.A.

100.0 % (68/68)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 145:

145: wr_en <= write and cs and (not lock);
Count: 529989
Threshold: 1

Signal assignment statement on line 168:

168: reg_value <= reg_value_r;
Count: 9605
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOCK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REG_VALUE

	Element	From	To	Count	Threshold
Bin	(7)	0	1	1524	1
Bin	(7)	1	0	3125	1
Bin	(6)	0	1	1474	1
Bin	(6)	1	0	3075	1
Bin	(5)	0	1	1522	1
Bin	(5)	1	0	3123	1
Bin	(4)	0	1	1636	1
Bin	(4)	1	0	3237	1
Bin	(3)	0	1	1638	1
Bin	(3)	1	0	3239	1
Bin	(2)	0	1	1628	1
Bin	(2)	1	0	3229	1
Bin	(1)	0	1	1652	1
Bin	(1)	1	0	3253	1
Bin	(0)	0	1	1686	1
Bin	(0)	1	0	3287	1

Signal:

REG_VALUE_R

	Element	From	To	Count	Threshold
Bin	(7)	0	1	2817	1
Bin	(7)	1	0	5187	1
Bin	(6)	0	1	2946	1
Bin	(6)	1	0	5058	1
Bin	(5)	0	1	3010	1
Bin	(5)	1	0	4994	1
Bin	(4)	0	1	3061	1
Bin	(4)	1	0	4943	1
Bin	(3)	0	1	2927	1
Bin	(3)	1	0	5077	1
Bin	(2)	0	1	2988	1
Bin	(2)	1	0	5016	1
Bin	(1)	0	1	2994	1
Bin	(1)	1	0	5010	1
Bin	(0)	0	1	3037	1
Bin	(0)	1	0	4967	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	32353	1
Bin	1	0	33954	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 145:

 write and cs and (not lock) 
 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	347206	1
Bin	'1'	'0'	9020	1
Bin	'1'	'1'	32353	1

"and" expression on line 145:

 write and cs 
 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	41383	1
Bin	'1'	'0'	219383	1
Bin	'1'	'1'	41373	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_4_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/test_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 145:

Signal assignment statement on line 168:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 145:

"and" expression on line 145:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: