NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TXTB_PORT_A_CS_GEN(5)

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TXTB_PORT_A_CS_GEN(5)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1') 
377:                                 else 
378:                             '0';

Count: 10633121
Threshold: 1

Signal assignment statement:

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1')

Count: 11417
Threshold: 1

Signal assignment statement:

378: '0';
Count: 10621704
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1')

	Evaluated to	Count	Threshold
Bin	True	11417	1
Bin	False	10621704	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1')

	Evaluated to	Count	Threshold
Bin	False	10123075	1
Bin	True	510046	1

"and" expression

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1') 
                                           <--------------LHS-------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	498629	1
Bin	True	False	11438	1
Bin	True	True	11417	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TXTB_PORT_A_CS_GEN(5)

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: