NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	85.7 % (6/7)	N.A.	N.A.	91.6 % (11/12)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.BYTE_GEN(2)

100.0 % (3/3)

100.0 % (2/2)

N.A.

85.7 % (6/7)

N.A.

91.6 % (11/12)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 143 to 145:

143:        byte_we(i) <= '1' when (write = '1' and be(i) = '1') 
144:                          else 
145:                      '0';

Count: 49972241
Threshold: 1

Signal assignment statement on line 143:

143: byte_we(i) <= '1' when (write = '1' and be(i) = '1')
Count: 46368
Threshold: 1

Signal assignment statement on line 145:

145: '0';
Count: 49925873
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 143:

143: byte_we(i) <= '1' when (write = '1' and be(i) = '1')

	Evaluated to	Count	Threshold
Bin	True	46368	1
Bin	False	49925873	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

"and" expression on line 143:

 write = '1' and be(i) = '1' 
 <---LHS--->     <---RHS--->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1

Excluded expressions:

Covered expressions:

"and" expression on line 143:

 write = '1' and be(i) = '1' 
 <---LHS--->     <---RHS--->

	LHS	RHS	Count	Threshold
Bin	True	False	46348	1
Bin	True	True	46368	1

"=" expression on line 143:

write = '1'

	Evaluated to	Count	Threshold
Bin	False	49879525	1
Bin	True	92716	1

"=" expression on line 143:

be(i) = '1'

	Evaluated to	Count	Threshold
Bin	False	46348	1
Bin	True	46368	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.BYTE_GEN(2)

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 143 to 145:

Signal assignment statement on line 143:

Signal assignment statement on line 145:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 143:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

"and" expression on line 143:

Excluded expressions:

Covered expressions:

"and" expression on line 143:

"=" expression on line 143:

"=" expression on line 143:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: