NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TXT_BUF_TEST_DATA_PADDING_GEN(3)

File:  /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average
TXT_BUF_PADDING_INDEX_GEN_TRUE N.A. N.A. N.A. N.A. N.A. N.A. N.A.
TXT_BUF_PADDING_INDEX_GEN_FALSE 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TXT_BUF_TEST_DATA_PADDING_GEN(3) N.A. N.A. N.A. N.A. N.A. N.A. N.A.

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The limit of printed items was reached (5000). Total 261615 items are not displayed.

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