NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_C_MASK_PRESENT_GEN_T.FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (58/58)	100.0 % (3/3)	N.A.	N.A.	100.0 % (62/62)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

140: wr_en <= write and cs;
Count: 58335
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	3267797	1
Bin	1	0	3267962	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	1156	1
Bin	1	0	991	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	18507	1
Bin	1	0	320310	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	21922	1
Bin	1	0	316895	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	19202	1
Bin	1	0	319615	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	22335	1
Bin	1	0	316482	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	40384	1
Bin	1	0	298433	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	41708	1
Bin	1	0	297109	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	49733	1
Bin	1	0	289084	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	50881	1
Bin	1	0	287936	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	27300	1
Bin	1	0	27465	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	1620	1
Bin	1	0	1785	1

Port:

REG_VALUE(7)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	190	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	190	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	208	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	196	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	18	1
Bin	1	0	183	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	245	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	224	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	238	1

Signal:

REG_VALUE_R(7)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	436	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	436	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	418	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	430	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	18	1
Bin	1	0	443	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	381	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	402	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	388	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	1616	1
Bin	1	0	1781	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

140:    wr_en <= write and cs; 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	1620	1
Bin	'1'	'0'	27300	1
Bin	'1'	'1'	1616	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_C_MASK_PRESENT_GEN_T.FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Signal assignment statement:

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Port:

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Signal:

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Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: