File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Purpose:
70: -- Read Write register
71: --------------------------------------------------------------------------------
72: -- Revision History:
73: -- 14.10.2018 Created file
74: --------------------------------------------------------------------------------
75:
76: Library ieee;
77: USE IEEE.std_logic_1164.all;
78: USE IEEE.numeric_std.ALL;
79:
80: entity memory_reg_rw is
81: generic(
82:
83: -- Width of register data
84: constant data_width : natural := 32;
85:
86: -- Reset value of register
87: constant reset_value : std_logic_vector
88: );
89: port(
90: ------------------------------------------------------------------------
91: -- Clock and reset
92: ------------------------------------------------------------------------
93: signal clk_sys :in std_logic;
94: signal res_n :in std_logic;
95:
96: ------------------------------------------------------------------------
97: -- Address bus
98: ------------------------------------------------------------------------
99: signal data_in :in std_logic_vector(data_width - 1 downto 0);
100: signal write :in std_logic;
101: signal cs :in std_logic;
102:
103: ------------------------------------------------------------------------
104: -- Register outputs
105: ------------------------------------------------------------------------
106: signal reg_value :out std_logic_vector(data_width - 1 downto 0)
107: );
108:
109: end entity memory_reg_rw;
110:
111:
112: architecture rtl of memory_reg_rw is
113:
114: ---------------------------------------------------------------------------
115: -- Create new constants for reset value, implemented etc.
116: -- This is important because generic can't be directly passed to if-generate
117: -- condition. In instance of the module, generic is filled like so:
118: -- reset_value => "0000000110011111"
119: -- Some tools interpret this vector as 'downto' (GHDL), other tools as 'to'.
120: -- (Vivado). We want to keep the module generic therefore we will not give
121: -- range (and direction) to generic "reset_value", but we must tell the tool
122: -- how to interpret this constant that is passed without "to/downto"!
123: -- So we re-declare constants internally and give direction to them.
124: -- Tool should assign the constant the same way as it was passed.
125: ---------------------------------------------------------------------------
126: constant reset_value_i : std_logic_vector(data_width - 1 downto 0) := reset_value;
127:
128: -- Register implementation itself!
129: signal reg_value_r : std_logic_vector(data_width - 1 downto 0);
130:
131: -- Write enable
132: signal wr_en : std_logic;
133:
134: begin
135:
136: ----------------------------------------------------------------------------
137: -- Write enable
138: ----------------------------------------------------------------------------
139: wr_en <= write and cs;
140:
141: ----------------------------------------------------------------------------
142: -- Register instance
143: ----------------------------------------------------------------------------
144: bit_gen : for i in 0 to data_width - 1 generate
145:
146: reg_access_proc : process(clk_sys, res_n)
147: begin
148: if (res_n = '0') then
149: reg_value_r(i) <= reset_value_i(i);
150: elsif (rising_edge(clk_sys)) then
151: if (wr_en = '1') then
152: reg_value_r(i) <= data_in(i);
153: end if;
154: end if;
155: end process;
156:
157: end generate bit_gen;
158:
159: ----------------------------------------------------------------------------
160: -- Register to output propagation
161: ----------------------------------------------------------------------------
162: reg_value <= reg_value_r;
163:
164: end architecture;