NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ERR_DETECTOR_INST

File:  /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
ERR_PIPELINE_TRUE_GEN 100.0 % (3/3) 100.0 % (4/4) N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (9/9)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ERR_DETECTOR_INST 100.0 % (75/75) 100.0 % (68/68) 100.0 % (388/388) 100.0 % (121/121) N.A. 100.0 % (13/13) 100.0 % (665/665)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 257 to 263:

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
258:                     '1' when (stuff_err = '1') else 
...
262:                     '1' when (tran_frame_parity_error = '1') else 
263:                     '0'; 
Count: 255496
Threshold: 1

Signal assignment statement on line 257:

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
Count: 9861
Threshold: 1

Signal assignment statement on line 258:

258:                     '1' when (stuff_err = '1') else 
Count: 15862
Threshold: 1

Signal assignment statement on line 259:

259:                     '1' when (form_err = '1' or ack_err = '1') else 
Count: 95853
Threshold: 1

Signal assignment statement on line 260:

260:                     '1' when (crc_err = '1') else 
Count: 863
Threshold: 1

Signal assignment statement on line 261:

261:                     '1' when (bit_err_arb = '1') else 
Count: 1455
Threshold: 1

Signal assignment statement on line 262:

262:                     '1' when (tran_frame_parity_error = '1') else 
Count: 728
Threshold: 1

Signal assignment statement on line 263:

263:                     '0'; 
Count: 130874
Threshold: 1

If statement on lines 266 to 268:

266:    form_err_i <= '1' when (form_err = '1') else 
267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
268:                  '0'; 
Count: 249308
Threshold: 1

Signal assignment statement on line 266:

266:    form_err_i <= '1' when (form_err = '1') else 
Count: 87476
Threshold: 1

Signal assignment statement on line 267:

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Count: 416
Threshold: 1

Signal assignment statement on line 268:

268:                  '0'; 
Count: 161416
Threshold: 1

Sequential statement on lines 291 to 299:

291:    with dst_ctr select dst_ctr_grey <= 
292:        "001" when "001", 
...
298:        "100" when "111", 
299:        "000" when others; 
Count: 995560
Threshold: 1

Signal assignment statement on line 292:

292:        "001" when "001", 
Count: 147140
Threshold: 1

Signal assignment statement on line 293:

293:        "011" when "010", 
Count: 137299
Threshold: 1

Signal assignment statement on line 294:

294:        "010" when "011", 
Count: 126443
Threshold: 1

Signal assignment statement on line 295:

295:        "110" when "100", 
Count: 117682
Threshold: 1

Signal assignment statement on line 296:

296:        "111" when "101", 
Count: 110698
Threshold: 1

Signal assignment statement on line 297:

297:        "101" when "110", 
Count: 105363
Threshold: 1

Signal assignment statement on line 298:

298:        "100" when "111", 
Count: 100603
Threshold: 1

Signal assignment statement on line 299:

299:        "000" when others; 
Count: 150332
Threshold: 1

Signal assignment statement on line 301:

301:    dst_parity <= dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2); 
Count: 995560
Threshold: 1

If statement on lines 307 to 310:

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
309:                             else 
310:                         '0'; 
Count: 102764
Threshold: 1

Signal assignment statement on line 307:

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
Count: 53899
Threshold: 1

Signal assignment statement on line 310:

310:                         '0'; 
Count: 48865
Threshold: 1

Signal assignment statement on line 313:

313:    rx_crc_15 <= rx_crc(14 downto 0); 
Count: 3821969
Threshold: 1

Signal assignment statement on line 314:

314:    rx_crc_17 <= rx_crc(16 downto 0); 
Count: 4169579
Threshold: 1

Signal assignment statement on line 315:

315:    rx_crc_21 <= rx_crc(20 downto 0); 
Count: 4853728
Threshold: 1

If statement on lines 318 to 320:

318:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
319:                     else 
320:                 '0'; 
Count: 9636317
Threshold: 1

Signal assignment statement on line 318:

318:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
Count: 74491
Threshold: 1

Signal assignment statement on line 320:

320:                 '0'; 
Count: 9561826
Threshold: 1

If statement on lines 323 to 325:

323:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
324:                     else 
325:                 '0'; 
Count: 11114632
Threshold: 1

Signal assignment statement on line 323:

323:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
Count: 20037
Threshold: 1

Signal assignment statement on line 325:

325:                 '0'; 
Count: 11094595
Threshold: 1

If statement on lines 328 to 330:

328:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
329:                     else 
330:                 '0'; 
Count: 11798783
Threshold: 1

Signal assignment statement on line 328:

328:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
Count: 11774
Threshold: 1

Signal assignment statement on line 330:

330:                 '0'; 
Count: 11787009
Threshold: 1

If statement on lines 333 to 335:

333:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
334:                          else 
335:                      '0'; 
Count: 1989579
Threshold: 1

Signal assignment statement on line 333:

333:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
Count: 161495
Threshold: 1

Signal assignment statement on line 335:

335:                      '0'; 
Count: 1828084
Threshold: 1

If statement on lines 338 to 343:

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
342:                       else 
343:                   '1'; 
Count: 667621
Threshold: 1

Signal assignment statement on line 338:

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
Count: 539073
Threshold: 1

Signal assignment statement on line 343:

343:                   '1'; 
Count: 128548
Threshold: 1

If statement on lines 345 to 347:

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
346:                   crc_match_c when (crc_check = '1') else 
347:                   crc_match_q; 
Count: 438656
Threshold: 1

Signal assignment statement on line 345:

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Count: 85462
Threshold: 1

Signal assignment statement on line 346:

346:                   crc_match_c when (crc_check = '1') else 
Count: 87283
Threshold: 1

Signal assignment statement on line 347:

347:                   crc_match_q; 
Count: 265911
Threshold: 1

If statement on lines 351 to 355:

351:        if (res_n = '0') then 
352:            crc_match_q <= '0'; 
353:        elsif (rising_edge(clk_sys)) then 
354:            crc_match_q <= crc_match_d; 
355:        end if; 
Count: 1090018206
Threshold: 1

Signal assignment statement on line 352:

352:            crc_match_q <= '0'; 
Count: 2424883
Threshold: 1

Signal assignment statement on line 354:

354:            crc_match_q <= crc_match_d; 
Count: 543791678
Threshold: 1

If statement on lines 368 to 373:

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
369:                              else 
370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
372:                              else 
373:                          '0'; 
Count: 3001743
Threshold: 1

Signal assignment statement on line 368:

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Count: 430
Threshold: 1

Signal assignment statement on line 370:

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
Count: 365
Threshold: 1

Signal assignment statement on line 373:

373:                          '0'; 
Count: 3000948
Threshold: 1

Signal assignment statement on line 377:

377:    err_detected <= err_frm_req_i; 
Count: 252142
Threshold: 1

If statement on lines 382 to 389:

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
383:                           ERC_BIT_ERR when (bit_err = '1') else 
...
388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
389:                           err_capt_err_type_q; 
Count: 263559
Threshold: 1

Signal assignment statement on line 382:

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Count: 90074
Threshold: 1

Signal assignment statement on line 383:

383:                           ERC_BIT_ERR when (bit_err = '1') else 
Count: 10549
Threshold: 1

Signal assignment statement on line 384:

384:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Count: 1712
Threshold: 1

Signal assignment statement on line 385:

385:                           ERC_CRC_ERR when (crc_err = '1') else 
Count: 1637
Threshold: 1

Signal assignment statement on line 386:

386:                           ERC_ACK_ERR when (ack_err = '1') else 
Count: 8643
Threshold: 1

Signal assignment statement on line 387:

387:                           ERC_STUF_ERR when (stuff_err = '1') else 
Count: 16777
Threshold: 1

Signal assignment statement on line 388:

388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Count: 777
Threshold: 1

Signal assignment statement on line 389:

389:                           err_capt_err_type_q; 
Count: 133390
Threshold: 1

If statement on lines 396 to 406:

396:        if (res_n = '0') then 
397:            err_capt_err_type_q <= ERR_TYPE_RSTVAL; 
...
405:            end if; 
406:        end if; 
Count: 1090018206
Threshold: 1

Signal assignment statement on line 397:

397:            err_capt_err_type_q <= ERR_TYPE_RSTVAL; 
Count: 2424883
Threshold: 1

Signal assignment statement on line 398:

398:            err_capt_err_pos_q <= ERR_POS_RSTVAL; 
Count: 2424883
Threshold: 1

Signal assignment statement on line 399:

399:            err_capt_err_erp <= ERR_ERP_RSTVAL; 
Count: 2424883
Threshold: 1

If statement on lines 401 to 405:

401:            if (err_frm_req_i = '1') then 
402:                err_capt_err_type_q <= err_capt_err_type_d; 
403:                err_capt_err_pos_q <= err_pos; 
404:                err_capt_err_erp <= is_err_passive; 
405:            end if; 
Count: 543791678
Threshold: 1

Signal assignment statement on line 402:

402:                err_capt_err_type_q <= err_capt_err_type_d; 
Count: 31302
Threshold: 1

Signal assignment statement on line 403:

403:                err_capt_err_pos_q <= err_pos; 
Count: 31302
Threshold: 1

Signal assignment statement on line 404:

404:                err_capt_err_erp <= is_err_passive; 
Count: 31302
Threshold: 1

Signal assignment statement on line 410:

410:    err_capt_err_type <= err_capt_err_type_q; 
Count: 7328
Threshold: 1

Signal assignment statement on line 411:

411:    err_capt_err_pos <= err_capt_err_pos_q; 
Count: 12038
Threshold: 1

Signal assignment statement on line 412:

412:    crc_match <= crc_match_q; 
Count: 58834
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 257:

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
Evaluated toCountThreshold
BinTrue98611
BinFalse2456351

"if" / "when" / "else" condition on line 258:

258:                     '1' when (stuff_err = '1') else 
Evaluated toCountThreshold
BinTrue158621
BinFalse2297731

"if" / "when" / "else" condition on line 259:

259:                     '1' when (form_err = '1' or ack_err = '1') else 
Evaluated toCountThreshold
BinTrue958531
BinFalse1339201

"if" / "when" / "else" condition on line 260:

260:                     '1' when (crc_err = '1') else 
Evaluated toCountThreshold
BinTrue8631
BinFalse1330571

"if" / "when" / "else" condition on line 261:

261:                     '1' when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinTrue14551
BinFalse1316021

"if" / "when" / "else" condition on line 262:

262:                     '1' when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinTrue7281
BinFalse1308741

"if" / "when" / "else" condition on line 266:

266:    form_err_i <= '1' when (form_err = '1') else 
Evaluated toCountThreshold
BinTrue874761
BinFalse1618321

"if" / "when" / "else" condition on line 267:

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Evaluated toCountThreshold
BinTrue4161
BinFalse1614161

"case" / "with" / "select" choice on line 292:

292:        "001" when "001", 
Choice ofCountThreshold
Bin"001"1471401

"case" / "with" / "select" choice on line 293:

293:        "011" when "010", 
Choice ofCountThreshold
Bin"010"1372991

"case" / "with" / "select" choice on line 294:

294:        "010" when "011", 
Choice ofCountThreshold
Bin"011"1264431

"case" / "with" / "select" choice on line 295:

295:        "110" when "100", 
Choice ofCountThreshold
Bin"100"1176821

"case" / "with" / "select" choice on line 296:

296:        "111" when "101", 
Choice ofCountThreshold
Bin"101"1106981

"case" / "with" / "select" choice on line 297:

297:        "101" when "110", 
Choice ofCountThreshold
Bin"110"1053631

"case" / "with" / "select" choice on line 298:

298:        "100" when "111", 
Choice ofCountThreshold
Bin"111"1006031

"case" / "with" / "select" choice on line 299:

299:        "000" when others; 
Choice ofCountThreshold
Binothers1503321

"if" / "when" / "else" condition on lines 307 to 308:

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
Evaluated toCountThreshold
BinTrue538991
BinFalse488651

"if" / "when" / "else" condition on line 318:

318:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
Evaluated toCountThreshold
BinTrue744911
BinFalse95618261

"if" / "when" / "else" condition on line 323:

323:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
Evaluated toCountThreshold
BinTrue200371
BinFalse110945951

"if" / "when" / "else" condition on line 328:

328:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
Evaluated toCountThreshold
BinTrue117741
BinFalse117870091

"if" / "when" / "else" condition on line 333:

333:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
Evaluated toCountThreshold
BinTrue1614951
BinFalse18280841

"if" / "when" / "else" condition on lines 338 to 341:

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
Evaluated toCountThreshold
BinTrue5390731
BinFalse1285481

"if" / "when" / "else" condition on line 345:

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Evaluated toCountThreshold
BinTrue854621
BinFalse3531941

"if" / "when" / "else" condition on line 346:

346:                   crc_match_c when (crc_check = '1') else 
Evaluated toCountThreshold
BinTrue872831
BinFalse2659111

"if" / "when" / "else" condition on line 351:

351:        if (res_n = '0') then 
Evaluated toCountThreshold
BinTrue24248831
BinFalse10875933231

"if" / "when" / "else" condition on line 353:

353:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437916781
BinFalse5438016451

"if" / "when" / "else" condition on line 368:

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Evaluated toCountThreshold
BinTrue4301
BinFalse30013131

"if" / "when" / "else" condition on lines 370 to 371:

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
Evaluated toCountThreshold
BinTrue3651
BinFalse30009481

"if" / "when" / "else" condition on line 382:

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Evaluated toCountThreshold
BinTrue900741
BinFalse1734851

"if" / "when" / "else" condition on line 383:

383:                           ERC_BIT_ERR when (bit_err = '1') else 
Evaluated toCountThreshold
BinTrue105491
BinFalse1629361

"if" / "when" / "else" condition on line 384:

384:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinTrue17121
BinFalse1612241

"if" / "when" / "else" condition on line 385:

385:                           ERC_CRC_ERR when (crc_err = '1') else 
Evaluated toCountThreshold
BinTrue16371
BinFalse1595871

"if" / "when" / "else" condition on line 386:

386:                           ERC_ACK_ERR when (ack_err = '1') else 
Evaluated toCountThreshold
BinTrue86431
BinFalse1509441

"if" / "when" / "else" condition on line 387:

387:                           ERC_STUF_ERR when (stuff_err = '1') else 
Evaluated toCountThreshold
BinTrue167771
BinFalse1341671

"if" / "when" / "else" condition on line 388:

388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinTrue7771
BinFalse1333901

"if" / "when" / "else" condition on line 396:

396:        if (res_n = '0') then 
Evaluated toCountThreshold
BinTrue24248831
BinFalse10875933231

"if" / "when" / "else" condition on line 400:

400:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437916781
BinFalse5438016451

"if" / "when" / "else" condition on line 401:

401:            if (err_frm_req_i = '1') then 
Evaluated toCountThreshold
BinTrue313021
BinFalse5437603761

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RES_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 TX_DATA
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_DATA
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BIT_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BIT_ERR_ARB
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 STUFF_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 FORM_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 ACK_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CRC_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_CRC
ElementFromToCountThresholdExcluded due to
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_15
ElementFromToCountThresholdExcluded due to
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_17
ElementFromToCountThresholdExcluded due to
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_21
ElementFromToCountThresholdExcluded due to
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 RX_STUFF_COUNT
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 DST_CTR
ElementFromToCountThresholdExcluded due to
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 FIXED_STUFF
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 ERR_POS
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_CHECK
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CRC_CLEAR_MATCH_FLAG
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CRC_SRC
ElementFromToCountThresholdExcluded due to
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 IS_ARBITRATION
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 IS_TRANSMITTER
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 IS_ERR_PASSIVE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 TRAN_FRAME_PARITY_ERROR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_SETTINGS_NISOFD
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 ERR_CAPT_ERR_TYPE
ElementFromToCountThreshold
Bin(2)019641
Bin(2)1025641
Bin(1)0112341
Bin(1)1028331
Bin(0)013361
Bin(0)1019361

Port:

 ERR_CAPT_ERR_POS
ElementFromToCountThreshold
Bin(3)0141881
Bin(3)1025951
Bin(2)0144211
Bin(2)1028211
Bin(1)0137431
Bin(1)1021461
Bin(0)0129411
Bin(0)1013411

Port:

 ERR_CAPT_ERR_ERP
FromToCountThreshold
Bin012901
Bin1018911

Port:

 ERR_FRM_REQ
FromToCountThreshold
Bin01313021
Bin10329031

Port:

 ERR_DETECTED
FromToCountThreshold
Bin011244701
Bin101260711

Port:

 CRC_MATCH
FromToCountThreshold
Bin01278161
Bin10294171

Port:

 ERR_CTRS_UNCHANGED
FromToCountThreshold
Bin017951
Bin1023961

Signal:

 ERR_FRM_REQ_I
FromToCountThreshold
Bin011244701
Bin101260711

Signal:

 ERR_CAPT_ERR_TYPE_D
ElementFromToCountThreshold
Bin(2)01146101
Bin(2)10162101
Bin(1)01824381
Bin(1)10840371
Bin(0)01117361
Bin(0)10133361

Signal:

 ERR_CAPT_ERR_TYPE_Q
ElementFromToCountThreshold
Bin(2)019641
Bin(2)1025641
Bin(1)0112341
Bin(1)1028331
Bin(0)013361
Bin(0)1019361

Signal:

 ERR_CAPT_ERR_POS_Q
ElementFromToCountThreshold
Bin(3)0141881
Bin(3)1025951
Bin(2)0144211
Bin(2)1028211
Bin(1)0137431
Bin(1)1021461
Bin(0)0129411
Bin(0)1013411

Signal:

 FORM_ERR_I
FromToCountThreshold
Bin01878921
Bin10894931

Signal:

 CRC_MATCH_C
FromToCountThreshold
Bin01740051
Bin10724131

Signal:

 CRC_MATCH_D
FromToCountThreshold
Bin01278441
Bin10294451

Signal:

 CRC_MATCH_Q
FromToCountThreshold
Bin01278161
Bin10294171

Signal:

 DST_CTR_GREY
ElementFromToCountThreshold
Bin(2)014343461
Bin(2)105596131
Bin(1)014921221
Bin(1)105018371
Bin(0)015005001
Bin(0)104934591

Signal:

 DST_PARITY
FromToCountThreshold
Bin014848841
Bin104864801

Signal:

 STUFF_COUNT_CHECK
FromToCountThreshold
Bin01437811
Bin10453771

Signal:

 CRC_15_OK
FromToCountThreshold
Bin01744911
Bin10729011

Signal:

 CRC_17_OK
FromToCountThreshold
Bin01200371
Bin10184451

Signal:

 CRC_21_OK
FromToCountThreshold
Bin01117741
Bin10101841

Signal:

 STUFF_COUNT_OK
FromToCountThreshold
Bin011607861
Bin101591921

Signal:

 RX_CRC_15
ElementFromToCountThreshold
Bin(14)013991091
Bin(14)104007061
Bin(13)014084321
Bin(13)104100281
Bin(12)014195571
Bin(12)104211531
Bin(11)014319181
Bin(11)104335131
Bin(10)014437371
Bin(10)104453311
Bin(9)014534151
Bin(9)104550121
Bin(8)014653471
Bin(8)104669431
Bin(7)015119841
Bin(7)105135781
Bin(6)015230261
Bin(6)105246191
Bin(5)015342261
Bin(5)105358221
Bin(4)015447241
Bin(4)105463181
Bin(3)015548171
Bin(3)105564101
Bin(2)015663571
Bin(2)105679501
Bin(1)015776271
Bin(1)105792191
Bin(0)015867711
Bin(0)105883631

Signal:

 RX_CRC_17
ElementFromToCountThreshold
Bin(16)013442331
Bin(16)103458331
Bin(15)013854581
Bin(15)103870571
Bin(14)013991091
Bin(14)104007061
Bin(13)014084321
Bin(13)104100281
Bin(12)014195571
Bin(12)104211531
Bin(11)014319181
Bin(11)104335131
Bin(10)014437371
Bin(10)104453311
Bin(9)014534151
Bin(9)104550121
Bin(8)014653471
Bin(8)104669431
Bin(7)015119841
Bin(7)105135781
Bin(6)015230261
Bin(6)105246191
Bin(5)015342261
Bin(5)105358221
Bin(4)015447241
Bin(4)105463181
Bin(3)015548171
Bin(3)105564101
Bin(2)015663571
Bin(2)105679501
Bin(1)015776271
Bin(1)105792191
Bin(0)015867711
Bin(0)105883631

Signal:

 RX_CRC_21
ElementFromToCountThreshold
Bin(20)013118641
Bin(20)103134641
Bin(19)013228641
Bin(19)103244601
Bin(18)013316111
Bin(18)103332071
Bin(17)013377801
Bin(17)103393791
Bin(16)013442331
Bin(16)103458331
Bin(15)013854581
Bin(15)103870571
Bin(14)013991091
Bin(14)104007061
Bin(13)014084321
Bin(13)104100281
Bin(12)014195571
Bin(12)104211531
Bin(11)014319181
Bin(11)104335131
Bin(10)014437371
Bin(10)104453311
Bin(9)014534151
Bin(9)104550121
Bin(8)014653471
Bin(8)104669431
Bin(7)015119841
Bin(7)105135781
Bin(6)015230261
Bin(6)105246191
Bin(5)015342261
Bin(5)105358221
Bin(4)015447241
Bin(4)105463181
Bin(3)015548171
Bin(3)105564101
Bin(2)015663571
Bin(2)105679501
Bin(1)015776271
Bin(1)105792191
Bin(0)015867711
Bin(0)105883631

Uncovered expressions:

Excluded expressions:

"and" expression on lines 307 to 308:

 (mr_settings_nisofd = ISO_FD) and (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
  <-----------LHS----------->       <--------------------RHS--------------------->  
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"or" expression on line 308:

 crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC 
 <--------LHS-------->    <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"or" expression on lines 338 to 340:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or (crc_21_ok = '0' and crc_src = C_CRC21_SRC) 
 <------------------------------------------LHS------------------------------------------->     <------------------RHS------------------>  
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"or" expression on lines 338 to 339:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) 
  <------------------LHS------------------>      <------------------RHS------------------>  
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"and" expression on line 338:

 crc_15_ok = '0' and crc_src = C_CRC15_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"and" expression on line 339:

 crc_17_ok = '0' and crc_src = C_CRC17_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"and" expression on line 340:

 crc_21_ok = '0' and crc_src = C_CRC21_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

Covered expressions:

"=" expression on line 257:

 bit_err = '1' 
Evaluated toCountThreshold
BinFalse2456351
BinTrue98611

"=" expression on line 258:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse2297731
BinTrue158621

"or" expression on line 259:

 form_err = '1' or ack_err = '1' 
 <----LHS----->    <----RHS----> 
LHSRHSCountThreshold
BinFalseFalse1339201
BinFalseTrue83771
BinTrueFalse874761

"=" expression on line 259:

 form_err = '1' 
Evaluated toCountThreshold
BinFalse1422971
BinTrue874761

"=" expression on line 259:

 ack_err = '1' 
Evaluated toCountThreshold
BinFalse2213961
BinTrue83771

"=" expression on line 260:

 crc_err = '1' 
Evaluated toCountThreshold
BinFalse1330571
BinTrue8631

"=" expression on line 261:

 bit_err_arb = '1' 
Evaluated toCountThreshold
BinFalse1316021
BinTrue14551

"=" expression on line 262:

 tran_frame_parity_error = '1' 
Evaluated toCountThreshold
BinFalse1308741
BinTrue7281

"=" expression on line 266:

 form_err = '1' 
Evaluated toCountThreshold
BinFalse1618321
BinTrue874761

"and" expression on line 267:

 stuff_err = '1' and fixed_stuff = '1' 
 <-----LHS----->     <------RHS------> 
LHSRHSCountThreshold
BinFalseTrue135121
BinTrueFalse202561
BinTrueTrue4161

"=" expression on line 267:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse1411601
BinTrue206721

"=" expression on line 267:

 fixed_stuff = '1' 
Evaluated toCountThreshold
BinFalse1479041
BinTrue139281

"xor" expression on line 301:

 dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2) 
 <---------------LHS--------------->     <-----RHS-----> 
LHSRHSCountThreshold
Bin'0''0'2860301
Bin'0''1'2113011
Bin'1''0'2735831
Bin'1''1'2230451

"xor" expression on line 301:

 dst_ctr_grey(0) xor dst_ctr_grey(1) 
 <-----LHS----->     <-----RHS-----> 
LHSRHSCountThreshold
Bin'0''0'2493341
Bin'0''1'2441251
Bin'1''0'2525031
Bin'1''1'2479971

"and" expression on lines 307 to 308:

 (mr_settings_nisofd = ISO_FD) and (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
  <-----------LHS----------->       <--------------------RHS--------------------->  
LHSRHSCountThreshold
BinTrueFalse455071
BinTrueTrue538991

"=" expression on line 307:

 mr_settings_nisofd = ISO_FD 
Evaluated toCountThreshold
BinFalse33581
BinTrue994061

"or" expression on line 308:

 crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC 
 <--------LHS-------->    <--------RHS--------> 
LHSRHSCountThreshold
BinFalseFalse455071
BinFalseTrue244941

"or" expression on lines 338 to 341:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or (stuff_count_ok = '0' and stuff_count_check = '1') 
 <------------------------------------------------------------------LHS------------------------------------------------------------------>     <---------------------RHS---------------------->  
LHSRHSCountThreshold
BinFalseFalse1285481
BinFalseTrue140741
BinTrueFalse3507271

"or" expression on lines 338 to 340:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or (crc_21_ok = '0' and crc_src = C_CRC21_SRC) 
 <------------------------------------------LHS------------------------------------------->     <------------------RHS------------------>  
LHSRHSCountThreshold
BinFalseFalse1426221
BinFalseTrue2581531

"or" expression on lines 338 to 339:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) 
  <------------------LHS------------------>      <------------------RHS------------------>  
LHSRHSCountThreshold
BinFalseFalse4007751
BinFalseTrue1131541

"and" expression on line 338:

 crc_15_ok = '0' and crc_src = C_CRC15_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThreshold
BinTrueFalse3524251
BinTrueTrue1536921

"=" expression on line 338:

 crc_15_ok = '0' 
Evaluated toCountThreshold
BinFalse1615041
BinTrue5061171

"and" expression on line 339:

 crc_17_ok = '0' and crc_src = C_CRC17_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThreshold
BinTrueFalse3772451
BinTrueTrue1131541

"=" expression on line 339:

 crc_17_ok = '0' 
Evaluated toCountThreshold
BinFalse235301
BinTrue4903991

"and" expression on line 340:

 crc_21_ok = '0' and crc_src = C_CRC21_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThreshold
BinTrueFalse1273641
BinTrueTrue2581531

"=" expression on line 340:

 crc_21_ok = '0' 
Evaluated toCountThreshold
BinFalse152581
BinTrue3855171

"and" expression on line 341:

 stuff_count_ok = '0' and stuff_count_check = '1' 
 <-------LHS-------->     <---------RHS---------> 
LHSRHSCountThreshold
BinFalseTrue1944491
BinTrueFalse1533681
BinTrueTrue1883461

"=" expression on line 341:

 stuff_count_ok = '0' 
Evaluated toCountThreshold
BinFalse3259071
BinTrue3417141

"=" expression on line 341:

 stuff_count_check = '1' 
Evaluated toCountThreshold
BinFalse2848261
BinTrue3827951

"=" expression on line 345:

 crc_clear_match_flag = '1' 
Evaluated toCountThreshold
BinFalse3531941
BinTrue854621

"=" expression on line 346:

 crc_check = '1' 
Evaluated toCountThreshold
BinFalse2659111
BinTrue872831

"=" expression on line 351:

 res_n = '0' 
Evaluated toCountThreshold
BinFalse10875933231
BinTrue24248831

"and" expression on line 368:

 ack_err = '1' and is_err_passive = '1' 
 <----LHS---->     <-------RHS--------> 
LHSRHSCountThreshold
BinFalseTrue7369981
BinTrueFalse79471
BinTrueTrue4301

"=" expression on line 368:

 ack_err = '1' 
Evaluated toCountThreshold
BinFalse29933661
BinTrue83771

"=" expression on line 368:

 is_err_passive = '1' 
Evaluated toCountThreshold
BinFalse22643151
BinTrue7374281

"and" expression on lines 370 to 371:

 stuff_err = '1' and is_arbitration = '1' and is_transmitter = '1' and rx_data = DOMINANT 
 <------------------------------LHS------------------------------>     <------RHS-------> 
LHSRHSCountThreshold
BinFalseTrue15190741
BinTrueFalse4731
BinTrueTrue3651

"and" expression on lines 370 to 371:

 stuff_err = '1' and is_arbitration = '1' and is_transmitter = '1' 
 <-----------------LHS------------------>     <-------RHS--------> 
LHSRHSCountThreshold
BinFalseTrue13349741
BinTrueFalse24941
BinTrueTrue8381

"and" expression on line 370:

 stuff_err = '1' and is_arbitration = '1' 
 <-----LHS----->     <-------RHS--------> 
LHSRHSCountThreshold
BinFalseTrue5958521
BinTrueFalse173401
BinTrueTrue33321

"=" expression on line 370:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse29806411
BinTrue206721

"=" expression on line 370:

 is_arbitration = '1' 
Evaluated toCountThreshold
BinFalse24021291
BinTrue5991841

"=" expression on line 371:

 is_transmitter = '1' 
Evaluated toCountThreshold
BinFalse16655011
BinTrue13358121

"=" expression on line 371:

 rx_data = DOMINANT 
Evaluated toCountThreshold
BinFalse14818741
BinTrue15194391

"=" expression on line 382:

 form_err_i = '1' 
Evaluated toCountThreshold
BinFalse1734851
BinTrue900741

"=" expression on line 383:

 bit_err = '1' 
Evaluated toCountThreshold
BinFalse1629361
BinTrue105491

"=" expression on line 384:

 bit_err_arb = '1' 
Evaluated toCountThreshold
BinFalse1612241
BinTrue17121

"=" expression on line 385:

 crc_err = '1' 
Evaluated toCountThreshold
BinFalse1595871
BinTrue16371

"=" expression on line 386:

 ack_err = '1' 
Evaluated toCountThreshold
BinFalse1509441
BinTrue86431

"=" expression on line 387:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse1341671
BinTrue167771

"=" expression on line 388:

 tran_frame_parity_error = '1' 
Evaluated toCountThreshold
BinFalse1333901
BinTrue7771

"=" expression on line 396:

 res_n = '0' 
Evaluated toCountThreshold
BinFalse10875933231
BinTrue24248831

"=" expression on line 401:

 err_frm_req_i = '1' 
Evaluated toCountThreshold
BinFalse5437603761
BinTrue313021

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 420 to 421:

420:    -- psl err_detect_bit_err_cov : cover 
421:    --  {bit_err = '1'}; 
Count: 9785
Threshold: 1

PSL cover point on lines 423 to 424:

423:    -- psl err_detect_bit_err_arb_cov : cover 
424:    --  {bit_err_arb = '1'}; 
Count: 1455
Threshold: 1

PSL cover point on lines 426 to 427:

426:    -- psl err_detect_stuff_err_cov : cover 
427:    --  {stuff_err = '1'}; 
Count: 20672
Threshold: 1

PSL cover point on lines 429 to 430:

429:    -- psl err_detect_form_err_cov : cover 
430:    --  {form_err = '1'}; 
Count: 2733
Threshold: 1

PSL cover point on lines 432 to 433:

432:    -- psl err_detect_ack_err_cov : cover 
433:    --  {ack_err = '1'}; 
Count: 1321
Threshold: 1

PSL cover point on lines 435 to 436:

435:    -- psl err_detect_crc_err_cov : cover 
436:    --  {crc_err = '1'}; 
Count: 808
Threshold: 1

PSL cover point on lines 438 to 439:

438:    -- psl err_detect_parity_err_cov : cover 
439:    --  {tran_frame_parity_error = '1'}; 
Count: 165
Threshold: 1

PSL cover point on lines 441 to 442:

441:    -- psl err_capt_q_form_err_cov : cover 
442:    --  {err_capt_err_type_q = ERC_FRM_ERR}; 
Count: 36938682
Threshold: 1

PSL cover point on lines 444 to 445:

444:    -- psl err_capt_q_bit_err_cov : cover 
445:    --  {err_capt_err_type_q = ERC_BIT_ERR}; 
Count: 332595228
Threshold: 1

PSL cover point on lines 447 to 448:

447:    -- psl err_capt_q_crc_err_cov : cover 
448:    --  {err_capt_err_type_q = ERC_CRC_ERR}; 
Count: 724417
Threshold: 1

PSL cover point on lines 450 to 451:

450:    -- psl err_capt_q_ack_err_cov : cover 
451:    --  {err_capt_err_type_q = ERC_ACK_ERR}; 
Count: 3906033
Threshold: 1

PSL cover point on lines 453 to 454:

453:    -- psl err_capt_q_stuff_err_cov : cover 
454:    --  {err_capt_err_type_q = ERC_STUF_ERR}; 
Count: 170011737
Threshold: 1

PSL cover point on lines 456 to 457:

456:    -- psl err_capt_q_prt_err_cov : cover 
457:    --  {err_capt_err_type_q = ERC_PRT_ERR}; 
Count: 821732
Threshold: 1