NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ERR_DETECTOR_INST

File:  /__w/ctu-can-regression/ctu-can-regression/src/can_core/err_detector.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average
ERR_PIPELINE_TRUE_GEN 100.0 % (3/3) 100.0 % (4/4) N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (9/9)

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ERR_DETECTOR_INST 100.0 % (68/68) 100.0 % (68/68) 100.0 % (388/388) 100.0 % (121/121) N.A. 100.0 % (13/13) 100.0 % (658/658)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
258:                     '1' when (stuff_err = '1') else 
...
262:                     '1' when (tran_frame_parity_error = '1') else 
263:                     '0'; 
Count: 253038
Threshold: 1

Signal assignment statement:

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
Count: 9458
Threshold: 1

Signal assignment statement:

258:                     '1' when (stuff_err = '1') else 
Count: 15674
Threshold: 1

Signal assignment statement:

259:                     '1' when (form_err = '1' or ack_err = '1') else 
Count: 95084
Threshold: 1

Signal assignment statement:

260:                     '1' when (crc_err = '1') else 
Count: 861
Threshold: 1

Signal assignment statement:

261:                     '1' when (bit_err_arb = '1') else 
Count: 1557
Threshold: 1

Signal assignment statement:

262:                     '1' when (tran_frame_parity_error = '1') else 
Count: 762
Threshold: 1

Signal assignment statement:

263:                     '0'; 
Count: 129642
Threshold: 1

If statement:

266:    form_err_i <= '1' when (form_err = '1') else 
267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
268:                  '0'; 
Count: 248072
Threshold: 1

Signal assignment statement:

266:    form_err_i <= '1' when (form_err = '1') else 
Count: 87083
Threshold: 1

Signal assignment statement:

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Count: 404
Threshold: 1

Signal assignment statement:

268:                  '0'; 
Count: 160585
Threshold: 1

Sequential statement:

291:    with dst_ctr select dst_ctr_grey <= 
292:        "001" when "001", 
...
298:        "100" when "111", 
299:        "000" when others; 
Count: 992866
Threshold: 1

Signal assignment statement:

292:        "001" when "001", 
Count: 147226
Threshold: 1

Signal assignment statement:

293:        "011" when "010", 
Count: 136405
Threshold: 1

Signal assignment statement:

294:        "010" when "011", 
Count: 124833
Threshold: 1

Signal assignment statement:

295:        "110" when "100", 
Count: 116920
Threshold: 1

Signal assignment statement:

296:        "111" when "101", 
Count: 110637
Threshold: 1

Signal assignment statement:

297:        "101" when "110", 
Count: 105473
Threshold: 1

Signal assignment statement:

298:        "100" when "111", 
Count: 100953
Threshold: 1

Signal assignment statement:

299:        "000" when others; 
Count: 150419
Threshold: 1

Signal assignment statement:

301:    dst_parity <= dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2); 
Count: 992866
Threshold: 1

If statement:

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
309:                             else 
310:                         '0'; 
Count: 100534
Threshold: 1

Signal assignment statement:

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
Count: 52814
Threshold: 1

Signal assignment statement:

310:                         '0'; 
Count: 47720
Threshold: 1

If statement:

318:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
319:                     else 
320:                 '0'; 
Count: 9589255
Threshold: 1

Signal assignment statement:

318:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
Count: 74073
Threshold: 1

Signal assignment statement:

320:                 '0'; 
Count: 9515182
Threshold: 1

If statement:

323:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
324:                     else 
325:                 '0'; 
Count: 11064419
Threshold: 1

Signal assignment statement:

323:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
Count: 19761
Threshold: 1

Signal assignment statement:

325:                 '0'; 
Count: 11044658
Threshold: 1

If statement:

328:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
329:                     else 
330:                 '0'; 
Count: 11754007
Threshold: 1

Signal assignment statement:

328:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
Count: 12007
Threshold: 1

Signal assignment statement:

330:                 '0'; 
Count: 11742000
Threshold: 1

If statement:

333:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
334:                          else 
335:                      '0'; 
Count: 1984700
Threshold: 1

Signal assignment statement:

333:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
Count: 161718
Threshold: 1

Signal assignment statement:

335:                      '0'; 
Count: 1822982
Threshold: 1

If statement:

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
342:                       else 
343:                   '1'; 
Count: 663436
Threshold: 1

Signal assignment statement:

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
Count: 535446
Threshold: 1

Signal assignment statement:

343:                   '1'; 
Count: 127990
Threshold: 1

If statement:

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
346:                   crc_match_c when (crc_check = '1') else 
347:                   crc_match_q; 
Count: 436387
Threshold: 1

Signal assignment statement:

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Count: 84961
Threshold: 1

Signal assignment statement:

346:                   crc_match_c when (crc_check = '1') else 
Count: 87235
Threshold: 1

Signal assignment statement:

347:                   crc_match_q; 
Count: 264191
Threshold: 1

If statement:

351:        if (res_n = '0') then 
352:            crc_match_q <= '0'; 
353:        elsif (rising_edge(clk_sys)) then 
354:            crc_match_q <= crc_match_d; 
355:        end if; 
Count: 1055177083
Threshold: 1

Signal assignment statement:

352:            crc_match_q <= '0'; 
Count: 2418499
Threshold: 1

Signal assignment statement:

354:            crc_match_q <= crc_match_d; 
Count: 526374300
Threshold: 1

If statement:

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
369:                              else 
370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
372:                              else 
373:                          '0'; 
Count: 2995861
Threshold: 1

Signal assignment statement:

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Count: 429
Threshold: 1

Signal assignment statement:

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
Count: 362
Threshold: 1

Signal assignment statement:

373:                          '0'; 
Count: 2995070
Threshold: 1

If statement:

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
383:                           ERC_BIT_ERR when (bit_err = '1') else 
...
388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
389:                           err_capt_err_type_q; 
Count: 260765
Threshold: 1

Signal assignment statement:

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Count: 89676
Threshold: 1

Signal assignment statement:

383:                           ERC_BIT_ERR when (bit_err = '1') else 
Count: 9981
Threshold: 1

Signal assignment statement:

384:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Count: 1819
Threshold: 1

Signal assignment statement:

385:                           ERC_CRC_ERR when (crc_err = '1') else 
Count: 1631
Threshold: 1

Signal assignment statement:

386:                           ERC_ACK_ERR when (ack_err = '1') else 
Count: 8268
Threshold: 1

Signal assignment statement:

387:                           ERC_STUF_ERR when (stuff_err = '1') else 
Count: 16417
Threshold: 1

Signal assignment statement:

388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Count: 812
Threshold: 1

Signal assignment statement:

389:                           err_capt_err_type_q; 
Count: 132161
Threshold: 1

If statement:

396:        if (res_n = '0') then 
397:            err_capt_err_type_q <= ERR_TYPE_RSTVAL; 
...
405:            end if; 
406:        end if; 
Count: 1055177083
Threshold: 1

Signal assignment statement:

397:            err_capt_err_type_q <= ERR_TYPE_RSTVAL; 
Count: 2418499
Threshold: 1

Signal assignment statement:

398:            err_capt_err_pos_q <= ERR_POS_RSTVAL; 
Count: 2418499
Threshold: 1

Signal assignment statement:

399:            err_capt_err_erp <= ERR_ERP_RSTVAL; 
Count: 2418499
Threshold: 1

If statement:

401:            if (err_frm_req_i = '1') then 
402:                err_capt_err_type_q <= err_capt_err_type_d; 
403:                err_capt_err_pos_q <= err_pos; 
404:                err_capt_err_erp <= is_err_passive; 
405:            end if; 
Count: 526374300
Threshold: 1

Signal assignment statement:

402:                err_capt_err_type_q <= err_capt_err_type_d; 
Count: 30824
Threshold: 1

Signal assignment statement:

403:                err_capt_err_pos_q <= err_pos; 
Count: 30824
Threshold: 1

Signal assignment statement:

404:                err_capt_err_erp <= is_err_passive; 
Count: 30824
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
Evaluated toCountThreshold
BinTrue94581
BinFalse2435801

"if" / "when" / "else" condition:

258:                     '1' when (stuff_err = '1') else 
Evaluated toCountThreshold
BinTrue156741
BinFalse2279061

"if" / "when" / "else" condition:

259:                     '1' when (form_err = '1' or ack_err = '1') else 
Evaluated toCountThreshold
BinTrue950841
BinFalse1328221

"if" / "when" / "else" condition:

260:                     '1' when (crc_err = '1') else 
Evaluated toCountThreshold
BinTrue8611
BinFalse1319611

"if" / "when" / "else" condition:

261:                     '1' when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinTrue15571
BinFalse1304041

"if" / "when" / "else" condition:

262:                     '1' when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinTrue7621
BinFalse1296421

"if" / "when" / "else" condition:

266:    form_err_i <= '1' when (form_err = '1') else 
Evaluated toCountThreshold
BinTrue870831
BinFalse1609891

"if" / "when" / "else" condition:

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Evaluated toCountThreshold
BinTrue4041
BinFalse1605851

"case" / "with" / "select" choice:

292:        "001" when "001", 
Choice ofCountThreshold
Bin"001"1472261

"case" / "with" / "select" choice:

293:        "011" when "010", 
Choice ofCountThreshold
Bin"010"1364051

"case" / "with" / "select" choice:

294:        "010" when "011", 
Choice ofCountThreshold
Bin"011"1248331

"case" / "with" / "select" choice:

295:        "110" when "100", 
Choice ofCountThreshold
Bin"100"1169201

"case" / "with" / "select" choice:

296:        "111" when "101", 
Choice ofCountThreshold
Bin"101"1106371

"case" / "with" / "select" choice:

297:        "101" when "110", 
Choice ofCountThreshold
Bin"110"1054731

"case" / "with" / "select" choice:

298:        "100" when "111", 
Choice ofCountThreshold
Bin"111"1009531

"case" / "with" / "select" choice:

299:        "000" when others; 
Choice ofCountThreshold
Binothers1504191

"if" / "when" / "else" condition:

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
Evaluated toCountThreshold
BinTrue528141
BinFalse477201

"if" / "when" / "else" condition:

318:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
Evaluated toCountThreshold
BinTrue740731
BinFalse95151821

"if" / "when" / "else" condition:

323:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
Evaluated toCountThreshold
BinTrue197611
BinFalse110446581

"if" / "when" / "else" condition:

328:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
Evaluated toCountThreshold
BinTrue120071
BinFalse117420001

"if" / "when" / "else" condition:

333:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
Evaluated toCountThreshold
BinTrue1617181
BinFalse18229821

"if" / "when" / "else" condition:

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
Evaluated toCountThreshold
BinTrue5354461
BinFalse1279901

"if" / "when" / "else" condition:

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Evaluated toCountThreshold
BinTrue849611
BinFalse3514261

"if" / "when" / "else" condition:

346:                   crc_match_c when (crc_check = '1') else 
Evaluated toCountThreshold
BinTrue872351
BinFalse2641911

"if" / "when" / "else" condition:

351:        if (res_n = '0') then 
Evaluated toCountThreshold
BinTrue24184991
BinFalse10527585841

"if" / "when" / "else" condition:

353:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5263743001
BinFalse5263842841

"if" / "when" / "else" condition:

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Evaluated toCountThreshold
BinTrue4291
BinFalse29954321

"if" / "when" / "else" condition:

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
Evaluated toCountThreshold
BinTrue3621
BinFalse29950701

"if" / "when" / "else" condition:

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Evaluated toCountThreshold
BinTrue896761
BinFalse1710891

"if" / "when" / "else" condition:

383:                           ERC_BIT_ERR when (bit_err = '1') else 
Evaluated toCountThreshold
BinTrue99811
BinFalse1611081

"if" / "when" / "else" condition:

384:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinTrue18191
BinFalse1592891

"if" / "when" / "else" condition:

385:                           ERC_CRC_ERR when (crc_err = '1') else 
Evaluated toCountThreshold
BinTrue16311
BinFalse1576581

"if" / "when" / "else" condition:

386:                           ERC_ACK_ERR when (ack_err = '1') else 
Evaluated toCountThreshold
BinTrue82681
BinFalse1493901

"if" / "when" / "else" condition:

387:                           ERC_STUF_ERR when (stuff_err = '1') else 
Evaluated toCountThreshold
BinTrue164171
BinFalse1329731

"if" / "when" / "else" condition:

388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinTrue8121
BinFalse1321611

"if" / "when" / "else" condition:

396:        if (res_n = '0') then 
Evaluated toCountThreshold
BinTrue24184991
BinFalse10527585841

"if" / "when" / "else" condition:

400:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5263743001
BinFalse5263842841

"if" / "when" / "else" condition:

401:            if (err_frm_req_i = '1') then 
Evaluated toCountThreshold
BinTrue308241
BinFalse5263434761

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK_SYS
FromToCountThreshold
Bin015275788691
Bin105275804601

Port:

 RES_N
FromToCountThreshold
Bin0180821
Bin1080721

Port:

 TX_DATA
FromToCountThreshold
Bin016353361
Bin106337381

Port:

 RX_DATA
FromToCountThreshold
Bin0113911881
Bin1013895881

Port:

 BIT_ERR
FromToCountThreshold
Bin0193811
Bin10109811

Port:

 BIT_ERR_ARB
FromToCountThreshold
Bin0115571
Bin1031571

Port:

 STUFF_ERR
FromToCountThreshold
Bin01204891
Bin10220891

Port:

 FORM_ERR
FromToCountThreshold
Bin01870831
Bin10886831

Port:

 ACK_ERR
FromToCountThreshold
Bin0180011
Bin1096011

Port:

 CRC_ERR
FromToCountThreshold
Bin0116121
Bin1032121

Port:

 RX_CRC(20)
FromToCountThreshold
Bin017017281
Bin1013449591

Port:

 RX_CRC(19)
FromToCountThreshold
Bin016177841
Bin1012658481

Port:

 RX_CRC(18)
FromToCountThreshold
Bin016552931
Bin1011603551

Port:

 RX_CRC(17)
FromToCountThreshold
Bin016335041
Bin1012282701

Port:

 RX_CRC(16)
FromToCountThreshold
Bin0112974851
Bin1020611201

Port:

 RX_CRC(15)
FromToCountThreshold
Bin017344901
Bin1011926301

Port:

 RX_CRC(14)
FromToCountThreshold
Bin015846391
Bin105610251

Port:

 RX_CRC(13)
FromToCountThreshold
Bin015642211
Bin105927901

Port:

 RX_CRC(12)
FromToCountThreshold
Bin015939571
Bin105774331

Port:

 RX_CRC(11)
FromToCountThreshold
Bin015861881
Bin106099631

Port:

 RX_CRC(10)
FromToCountThreshold
Bin016221651
Bin105981291

Port:

 RX_CRC(9)
FromToCountThreshold
Bin016091981
Bin106373871

Port:

 RX_CRC(8)
FromToCountThreshold
Bin016473751
Bin106182861

Port:

 RX_CRC(7)
FromToCountThreshold
Bin015110031
Bin105125811

Port:

 RX_CRC(6)
FromToCountThreshold
Bin015228691
Bin105244431

Port:

 RX_CRC(5)
FromToCountThreshold
Bin015325961
Bin105342361

Port:

 RX_CRC(4)
FromToCountThreshold
Bin015422531
Bin105438801

Port:

 RX_CRC(3)
FromToCountThreshold
Bin015552031
Bin105567351

Port:

 RX_CRC(2)
FromToCountThreshold
Bin015646661
Bin105662791

Port:

 RX_CRC(1)
FromToCountThreshold
Bin015762331
Bin105778361

Port:

 RX_CRC(0)
FromToCountThreshold
Bin015864821
Bin105880921

Port:

 CRC_15(14)
FromToCountThreshold
Bin0114526421
Bin1014542411

Port:

 CRC_15(13)
FromToCountThreshold
Bin0114043811
Bin1014059791

Port:

 CRC_15(12)
FromToCountThreshold
Bin0114168151
Bin1014184141

Port:

 CRC_15(11)
FromToCountThreshold
Bin0114310401
Bin1014326361

Port:

 CRC_15(10)
FromToCountThreshold
Bin0114445911
Bin1014461891

Port:

 CRC_15(9)
FromToCountThreshold
Bin0114382461
Bin1014398421

Port:

 CRC_15(8)
FromToCountThreshold
Bin0114522231
Bin1014538191

Port:

 CRC_15(7)
FromToCountThreshold
Bin0114890851
Bin1014906831

Port:

 CRC_15(6)
FromToCountThreshold
Bin0114285721
Bin1014301681

Port:

 CRC_15(5)
FromToCountThreshold
Bin0114421381
Bin1014437341

Port:

 CRC_15(4)
FromToCountThreshold
Bin0114541041
Bin1014557031

Port:

 CRC_15(3)
FromToCountThreshold
Bin0114537431
Bin1014553421

Port:

 CRC_15(2)
FromToCountThreshold
Bin0114405701
Bin1014421651

Port:

 CRC_15(1)
FromToCountThreshold
Bin0114564371
Bin1014580341

Port:

 CRC_15(0)
FromToCountThreshold
Bin0114700761
Bin1014716741

Port:

 CRC_17(16)
FromToCountThreshold
Bin0117340391
Bin1017356331

Port:

 CRC_17(15)
FromToCountThreshold
Bin0117445081
Bin1017461061

Port:

 CRC_17(14)
FromToCountThreshold
Bin0117590541
Bin1017606511

Port:

 CRC_17(13)
FromToCountThreshold
Bin0117571561
Bin1017587531

Port:

 CRC_17(12)
FromToCountThreshold
Bin0116959081
Bin1016975061

Port:

 CRC_17(11)
FromToCountThreshold
Bin0117105171
Bin1017121151

Port:

 CRC_17(10)
FromToCountThreshold
Bin0116577181
Bin1016593171

Port:

 CRC_17(9)
FromToCountThreshold
Bin0116713621
Bin1016729591

Port:

 CRC_17(8)
FromToCountThreshold
Bin0116859821
Bin1016875811

Port:

 CRC_17(7)
FromToCountThreshold
Bin0116994371
Bin1017010361

Port:

 CRC_17(6)
FromToCountThreshold
Bin0117136171
Bin1017152171

Port:

 CRC_17(5)
FromToCountThreshold
Bin0117133821
Bin1017149781

Port:

 CRC_17(4)
FromToCountThreshold
Bin0117255401
Bin1017271381

Port:

 CRC_17(3)
FromToCountThreshold
Bin0117440701
Bin1017456681

Port:

 CRC_17(2)
FromToCountThreshold
Bin0117139851
Bin1017155841

Port:

 CRC_17(1)
FromToCountThreshold
Bin0117292861
Bin1017308851

Port:

 CRC_17(0)
FromToCountThreshold
Bin0117577191
Bin1017593171

Port:

 CRC_21(20)
FromToCountThreshold
Bin0117383481
Bin1017399411

Port:

 CRC_21(19)
FromToCountThreshold
Bin0116944921
Bin1016960891

Port:

 CRC_21(18)
FromToCountThreshold
Bin0117091821
Bin1017107801

Port:

 CRC_21(17)
FromToCountThreshold
Bin0117236681
Bin1017252661

Port:

 CRC_21(16)
FromToCountThreshold
Bin0117364281
Bin1017380271

Port:

 CRC_21(15)
FromToCountThreshold
Bin0117495371
Bin1017511351

Port:

 CRC_21(14)
FromToCountThreshold
Bin0117625071
Bin1017641051

Port:

 CRC_21(13)
FromToCountThreshold
Bin0117774461
Bin1017790441

Port:

 CRC_21(12)
FromToCountThreshold
Bin0117181461
Bin1017197431

Port:

 CRC_21(11)
FromToCountThreshold
Bin0117332931
Bin1017348921

Port:

 CRC_21(10)
FromToCountThreshold
Bin0117239641
Bin1017255601

Port:

 CRC_21(9)
FromToCountThreshold
Bin0117376631
Bin1017392611

Port:

 CRC_21(8)
FromToCountThreshold
Bin0117533501
Bin1017549451

Port:

 CRC_21(7)
FromToCountThreshold
Bin0117685681
Bin1017701681

Port:

 CRC_21(6)
FromToCountThreshold
Bin0117103051
Bin1017119021

Port:

 CRC_21(5)
FromToCountThreshold
Bin0117240001
Bin1017255971

Port:

 CRC_21(4)
FromToCountThreshold
Bin0117371311
Bin1017387291

Port:

 CRC_21(3)
FromToCountThreshold
Bin0117532391
Bin1017548371

Port:

 CRC_21(2)
FromToCountThreshold
Bin0117522041
Bin1017538001

Port:

 CRC_21(1)
FromToCountThreshold
Bin0117648511
Bin1017664491

Port:

 CRC_21(0)
FromToCountThreshold
Bin0117778381
Bin1017794341

Port:

 RX_STUFF_COUNT(3)
FromToCountThreshold
Bin0136491
Bin1052491

Port:

 RX_STUFF_COUNT(2)
FromToCountThreshold
Bin0170841
Bin1086831

Port:

 RX_STUFF_COUNT(1)
FromToCountThreshold
Bin0177511
Bin1093501

Port:

 RX_STUFF_COUNT(0)
FromToCountThreshold
Bin0166951
Bin1082951

Port:

 DST_CTR(2)
FromToCountThreshold
Bin011169201
Bin101185201

Port:

 DST_CTR(1)
FromToCountThreshold
Bin012418781
Bin102434731

Port:

 DST_CTR(0)
FromToCountThreshold
Bin014836491
Bin104852461

Port:

 FIXED_STUFF
FromToCountThreshold
Bin01134661
Bin10150661

Port:

 ERR_POS(3)
FromToCountThreshold
Bin01835381
Bin10819431

Port:

 ERR_POS(2)
FromToCountThreshold
Bin01574141
Bin10558141

Port:

 ERR_POS(1)
FromToCountThreshold
Bin01888751
Bin10872751

Port:

 ERR_POS(0)
FromToCountThreshold
Bin011224921
Bin101208921

Port:

 CRC_CHECK
FromToCountThreshold
Bin01594321
Bin10610321

Port:

 CRC_CLEAR_MATCH_FLAG
FromToCountThreshold
Bin01568171
Bin10584171

Port:

 CRC_SRC(1)
FromToCountThreshold
Bin01245951
Bin10261951

Port:

 CRC_SRC(0)
FromToCountThreshold
Bin01282331
Bin10298291

Port:

 IS_ARBITRATION
FromToCountThreshold
Bin01552481
Bin10568481

Port:

 IS_TRANSMITTER
FromToCountThreshold
Bin01198921
Bin10214921

Port:

 IS_ERR_PASSIVE
FromToCountThreshold
Bin017681
Bin1023681

Port:

 TRAN_FRAME_PARITY_ERROR
FromToCountThreshold
Bin017621
Bin1023621

Port:

 MR_SETTINGS_NISOFD
FromToCountThreshold
Bin011301
Bin1017301

Port:

 ERR_CAPT_ERR_TYPE(2)
FromToCountThreshold
Bin017931
Bin1023921

Port:

 ERR_CAPT_ERR_TYPE(1)
FromToCountThreshold
Bin0112521
Bin1028501

Port:

 ERR_CAPT_ERR_TYPE(0)
FromToCountThreshold
Bin013361
Bin1019351

Port:

 ERR_CAPT_ERR_POS(3)
FromToCountThreshold
Bin0141851
Bin1025911

Port:

 ERR_CAPT_ERR_POS(2)
FromToCountThreshold
Bin0144021
Bin1028031

Port:

 ERR_CAPT_ERR_POS(1)
FromToCountThreshold
Bin0136661
Bin1020701

Port:

 ERR_CAPT_ERR_POS(0)
FromToCountThreshold
Bin0129601
Bin1013611

Port:

 ERR_CAPT_ERR_ERP
FromToCountThreshold
Bin012901
Bin1018901

Port:

 ERR_FRM_REQ
FromToCountThreshold
Bin01308241
Bin10324241

Port:

 ERR_DETECTED
FromToCountThreshold
Bin011232421
Bin101248421

Port:

 CRC_MATCH
FromToCountThreshold
Bin01278031
Bin10294031

Port:

 ERR_CTRS_UNCHANGED
FromToCountThreshold
Bin017911
Bin1023911

Signal:

 ERR_FRM_REQ_I
FromToCountThreshold
Bin011232421
Bin101248421

Signal:

 ERR_CAPT_ERR_TYPE_D(2)
FromToCountThreshold
Bin01144221
Bin10160211

Signal:

 ERR_CAPT_ERR_TYPE_D(1)
FromToCountThreshold
Bin01810511
Bin10826491

Signal:

 ERR_CAPT_ERR_TYPE_D(0)
FromToCountThreshold
Bin01115711
Bin10131701

Signal:

 ERR_CAPT_ERR_TYPE_Q(2)
FromToCountThreshold
Bin017931
Bin1023921

Signal:

 ERR_CAPT_ERR_TYPE_Q(1)
FromToCountThreshold
Bin0112521
Bin1028501

Signal:

 ERR_CAPT_ERR_TYPE_Q(0)
FromToCountThreshold
Bin013361
Bin1019351

Signal:

 ERR_CAPT_ERR_POS_Q(3)
FromToCountThreshold
Bin0141851
Bin1025911

Signal:

 ERR_CAPT_ERR_POS_Q(2)
FromToCountThreshold
Bin0144021
Bin1028031

Signal:

 ERR_CAPT_ERR_POS_Q(1)
FromToCountThreshold
Bin0136661
Bin1020701

Signal:

 ERR_CAPT_ERR_POS_Q(0)
FromToCountThreshold
Bin0129601
Bin1013611

Signal:

 FORM_ERR_I
FromToCountThreshold
Bin01874871
Bin10890871

Signal:

 CRC_MATCH_C
FromToCountThreshold
Bin01734141
Bin10718211

Signal:

 CRC_MATCH_D
FromToCountThreshold
Bin01278341
Bin10294341

Signal:

 CRC_MATCH_Q
FromToCountThreshold
Bin01278031
Bin10294031

Signal:

 DST_CTR_GREY(2)
FromToCountThreshold
Bin014339831
Bin105572831

Signal:

 DST_CTR_GREY(1)
FromToCountThreshold
Bin014887951
Bin105024711

Signal:

 DST_CTR_GREY(0)
FromToCountThreshold
Bin014997411
Bin104915251

Signal:

 DST_PARITY
FromToCountThreshold
Bin014836491
Bin104852461

Signal:

 STUFF_COUNT_CHECK
FromToCountThreshold
Bin01426371
Bin10442331

Signal:

 CRC_15_OK
FromToCountThreshold
Bin01740731
Bin10724821

Signal:

 CRC_17_OK
FromToCountThreshold
Bin01197611
Bin10181681

Signal:

 CRC_21_OK
FromToCountThreshold
Bin01120071
Bin10104161

Signal:

 STUFF_COUNT_OK
FromToCountThreshold
Bin011610561
Bin101594621

Signal:

 RX_CRC_15(14)
FromToCountThreshold
Bin014007571
Bin104023541

Signal:

 RX_CRC_15(13)
FromToCountThreshold
Bin014096851
Bin104112811

Signal:

 RX_CRC_15(12)
FromToCountThreshold
Bin014194961
Bin104210931

Signal:

 RX_CRC_15(11)
FromToCountThreshold
Bin014322741
Bin104338701

Signal:

 RX_CRC_15(10)
FromToCountThreshold
Bin014420971
Bin104436951

Signal:

 RX_CRC_15(9)
FromToCountThreshold
Bin014542521
Bin104558471

Signal:

 RX_CRC_15(8)
FromToCountThreshold
Bin014650411
Bin104666391

Signal:

 RX_CRC_15(7)
FromToCountThreshold
Bin015109431
Bin105125381

Signal:

 RX_CRC_15(6)
FromToCountThreshold
Bin015228131
Bin105244101

Signal:

 RX_CRC_15(5)
FromToCountThreshold
Bin015325571
Bin105341521

Signal:

 RX_CRC_15(4)
FromToCountThreshold
Bin015422241
Bin105438191

Signal:

 RX_CRC_15(3)
FromToCountThreshold
Bin015551001
Bin105566951

Signal:

 RX_CRC_15(2)
FromToCountThreshold
Bin015646071
Bin105662011

Signal:

 RX_CRC_15(1)
FromToCountThreshold
Bin015761641
Bin105777591

Signal:

 RX_CRC_15(0)
FromToCountThreshold
Bin015864271
Bin105880211

Signal:

 RX_CRC_17(16)
FromToCountThreshold
Bin013451501
Bin103467481

Signal:

 RX_CRC_17(15)
FromToCountThreshold
Bin013863461
Bin103879451

Signal:

 RX_CRC_17(14)
FromToCountThreshold
Bin014007571
Bin104023541

Signal:

 RX_CRC_17(13)
FromToCountThreshold
Bin014096851
Bin104112811

Signal:

 RX_CRC_17(12)
FromToCountThreshold
Bin014194961
Bin104210931

Signal:

 RX_CRC_17(11)
FromToCountThreshold
Bin014322741
Bin104338701

Signal:

 RX_CRC_17(10)
FromToCountThreshold
Bin014420971
Bin104436951

Signal:

 RX_CRC_17(9)
FromToCountThreshold
Bin014542521
Bin104558471

Signal:

 RX_CRC_17(8)
FromToCountThreshold
Bin014650411
Bin104666391

Signal:

 RX_CRC_17(7)
FromToCountThreshold
Bin015109431
Bin105125381

Signal:

 RX_CRC_17(6)
FromToCountThreshold
Bin015228131
Bin105244101

Signal:

 RX_CRC_17(5)
FromToCountThreshold
Bin015325571
Bin105341521

Signal:

 RX_CRC_17(4)
FromToCountThreshold
Bin015422241
Bin105438191

Signal:

 RX_CRC_17(3)
FromToCountThreshold
Bin015551001
Bin105566951

Signal:

 RX_CRC_17(2)
FromToCountThreshold
Bin015646071
Bin105662011

Signal:

 RX_CRC_17(1)
FromToCountThreshold
Bin015761641
Bin105777591

Signal:

 RX_CRC_17(0)
FromToCountThreshold
Bin015864271
Bin105880211

Signal:

 RX_CRC_21(20)
FromToCountThreshold
Bin013114931
Bin103130911

Signal:

 RX_CRC_21(19)
FromToCountThreshold
Bin013233611
Bin103249571

Signal:

 RX_CRC_21(18)
FromToCountThreshold
Bin013304831
Bin103320801

Signal:

 RX_CRC_21(17)
FromToCountThreshold
Bin013388891
Bin103404881

Signal:

 RX_CRC_21(16)
FromToCountThreshold
Bin013451501
Bin103467481

Signal:

 RX_CRC_21(15)
FromToCountThreshold
Bin013863461
Bin103879451

Signal:

 RX_CRC_21(14)
FromToCountThreshold
Bin014007571
Bin104023541

Signal:

 RX_CRC_21(13)
FromToCountThreshold
Bin014096851
Bin104112811

Signal:

 RX_CRC_21(12)
FromToCountThreshold
Bin014194961
Bin104210931

Signal:

 RX_CRC_21(11)
FromToCountThreshold
Bin014322741
Bin104338701

Signal:

 RX_CRC_21(10)
FromToCountThreshold
Bin014420971
Bin104436951

Signal:

 RX_CRC_21(9)
FromToCountThreshold
Bin014542521
Bin104558471

Signal:

 RX_CRC_21(8)
FromToCountThreshold
Bin014650411
Bin104666391

Signal:

 RX_CRC_21(7)
FromToCountThreshold
Bin015109431
Bin105125381

Signal:

 RX_CRC_21(6)
FromToCountThreshold
Bin015228131
Bin105244101

Signal:

 RX_CRC_21(5)
FromToCountThreshold
Bin015325571
Bin105341521

Signal:

 RX_CRC_21(4)
FromToCountThreshold
Bin015422241
Bin105438191

Signal:

 RX_CRC_21(3)
FromToCountThreshold
Bin015551001
Bin105566951

Signal:

 RX_CRC_21(2)
FromToCountThreshold
Bin015646071
Bin105662011

Signal:

 RX_CRC_21(1)
FromToCountThreshold
Bin015761641
Bin105777591

Signal:

 RX_CRC_21(0)
FromToCountThreshold
Bin015864271
Bin105880211

Uncovered expressions:

Excluded expressions:

"or" expression

308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
                                       <--------LHS-------->    <--------RHS-------->  
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"and" expression

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"and" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
                                 <-----LHS----->     <--------RHS-------->     
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"and" expression

339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
                                 <-----LHS----->     <--------RHS-------->     
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"or" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"and" expression

340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
                                 <-----LHS----->     <--------RHS-------->     
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"or" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

Covered expressions:

"=" expression

257:    err_frm_req_i <= '1' when (bit_err = '1') else 
Evaluated toCountThreshold
BinFalse2435801
BinTrue94581

"=" expression

258:                     '1' when (stuff_err = '1') else 
Evaluated toCountThreshold
BinFalse2279061
BinTrue156741

"=" expression

259:                     '1' when (form_err = '1' or ack_err = '1') else 
Evaluated toCountThreshold
BinFalse1408231
BinTrue870831

"=" expression

259:                     '1' when (form_err = '1' or ack_err = '1') else 
Evaluated toCountThreshold
BinFalse2199051
BinTrue80011

"or" expression

259:                     '1' when (form_err = '1' or ack_err = '1') else 
                                   <----LHS----->    <----RHS---->       
LHSRHSCountThreshold
BinFalseFalse1328221
BinFalseTrue80011
BinTrueFalse870831

"=" expression

260:                     '1' when (crc_err = '1') else 
Evaluated toCountThreshold
BinFalse1319611
BinTrue8611

"=" expression

261:                     '1' when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinFalse1304041
BinTrue15571

"=" expression

262:                     '1' when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinFalse1296421
BinTrue7621

"=" expression

266:    form_err_i <= '1' when (form_err = '1') else 
Evaluated toCountThreshold
BinFalse1609891
BinTrue870831

"=" expression

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Evaluated toCountThreshold
BinFalse1405001
BinTrue204891

"=" expression

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Evaluated toCountThreshold
BinFalse1471191
BinTrue138701

"and" expression

267:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
                                <-----LHS----->     <------RHS------>       
LHSRHSCountThreshold
BinFalseTrue134661
BinTrueFalse200851
BinTrueTrue4041

"xor" expression

301:    dst_parity <= dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2); 
                      <-----LHS----->     <-----RHS----->                      
LHSRHSCountThreshold
Bin'0''0'2497721
Bin'0''1'2417531
Bin'1''0'2526991
Bin'1''1'2470421

"xor" expression

301:    dst_parity <= dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2); 
                      <---------------LHS--------------->     <-----RHS----->  
LHSRHSCountThreshold
Bin'0''0'2852241
Bin'0''1'2115901
Bin'1''0'2720591
Bin'1''1'2223931

"=" expression

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
Evaluated toCountThreshold
BinFalse33571
BinTrue971771

"or" expression

308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
                                       <--------LHS-------->    <--------RHS-------->  
LHSRHSCountThreshold
BinFalseFalse443631
BinFalseTrue245941

"and" expression

307:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
308:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
LHSRHSCountThreshold
BinTrueFalse443631
BinTrueTrue528141

"=" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
Evaluated toCountThreshold
BinFalse1603791
BinTrue5030571

"and" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
                                 <-----LHS----->     <--------RHS-------->     
LHSRHSCountThreshold
BinTrueFalse3515091
BinTrueTrue1515481

"=" expression

339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
Evaluated toCountThreshold
BinFalse234621
BinTrue4884261

"and" expression

339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
                                 <-----LHS----->     <--------RHS-------->     
LHSRHSCountThreshold
BinTrueFalse3777331
BinTrueTrue1106931

"or" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
LHSRHSCountThreshold
BinFalseFalse4011951
BinFalseTrue1106931

"=" expression

340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
Evaluated toCountThreshold
BinFalse157001
BinTrue3854951

"and" expression

340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
                                 <-----LHS----->     <--------RHS-------->     
LHSRHSCountThreshold
BinTrueFalse1260281
BinTrueTrue2594671

"or" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
LHSRHSCountThreshold
BinFalseFalse1417281
BinFalseTrue2594671

"=" expression

341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
Evaluated toCountThreshold
BinFalse3236901
BinTrue3397461

"=" expression

341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
Evaluated toCountThreshold
BinFalse2818261
BinTrue3816101

"and" expression

341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
                                 <-------LHS-------->     <---------RHS--------->  
LHSRHSCountThreshold
BinFalseTrue1944791
BinTrueFalse1526151
BinTrueTrue1871311

"or" expression

338:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
339:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
340:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
341:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
LHSRHSCountThreshold
BinFalseFalse1279901
BinFalseTrue137381
BinTrueFalse3483151

"=" expression

345:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Evaluated toCountThreshold
BinFalse3514261
BinTrue849611

"=" expression

346:                   crc_match_c when (crc_check = '1') else 
Evaluated toCountThreshold
BinFalse2641911
BinTrue872351

"=" expression

351:        if (res_n = '0') then 
Evaluated toCountThreshold
BinFalse10527585841
BinTrue24184991

"=" expression

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Evaluated toCountThreshold
BinFalse29878601
BinTrue80011

"=" expression

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Evaluated toCountThreshold
BinFalse22954741
BinTrue7003871

"and" expression

368:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
                                        <----LHS---->     <-------RHS-------->  
LHSRHSCountThreshold
BinFalseTrue6999581
BinTrueFalse75721
BinTrueTrue4291

"=" expression

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
Evaluated toCountThreshold
BinFalse29749431
BinTrue204891

"=" expression

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
Evaluated toCountThreshold
BinFalse24066521
BinTrue5887801

"and" expression

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
                                        <-----LHS----->     <-------RHS-------->     
LHSRHSCountThreshold
BinFalseTrue5856171
BinTrueFalse173261
BinTrueTrue31631

"=" expression

371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
Evaluated toCountThreshold
BinFalse16590711
BinTrue13363611

"and" expression

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
LHSRHSCountThreshold
BinFalseTrue13356911
BinTrueFalse24931
BinTrueTrue6701

"=" expression

371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
Evaluated toCountThreshold
BinFalse14762171
BinTrue15192151

"and" expression

370:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
371:                                    is_transmitter = '1' and rx_data = DOMINANT) 
LHSRHSCountThreshold
BinFalseTrue15188531
BinTrueFalse3081
BinTrueTrue3621

"=" expression

382:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Evaluated toCountThreshold
BinFalse1710891
BinTrue896761

"=" expression

383:                           ERC_BIT_ERR when (bit_err = '1') else 
Evaluated toCountThreshold
BinFalse1611081
BinTrue99811

"=" expression

384:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinFalse1592891
BinTrue18191

"=" expression

385:                           ERC_CRC_ERR when (crc_err = '1') else 
Evaluated toCountThreshold
BinFalse1576581
BinTrue16311

"=" expression

386:                           ERC_ACK_ERR when (ack_err = '1') else 
Evaluated toCountThreshold
BinFalse1493901
BinTrue82681

"=" expression

387:                           ERC_STUF_ERR when (stuff_err = '1') else 
Evaluated toCountThreshold
BinFalse1329731
BinTrue164171

"=" expression

388:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinFalse1321611
BinTrue8121

"=" expression

396:        if (res_n = '0') then 
Evaluated toCountThreshold
BinFalse10527585841
BinTrue24184991

"=" expression

401:            if (err_frm_req_i = '1') then 
Evaluated toCountThreshold
BinFalse5263434761
BinTrue308241

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

420:    -- psl err_detect_bit_err_cov : cover 
421:    --  {bit_err = '1'}; 
Count: 9381
Threshold: 1

PSL cover point:

423:    -- psl err_detect_bit_err_arb_cov : cover 
424:    --  {bit_err_arb = '1'}; 
Count: 1557
Threshold: 1

PSL cover point:

426:    -- psl err_detect_stuff_err_cov : cover 
427:    --  {stuff_err = '1'}; 
Count: 20489
Threshold: 1

PSL cover point:

429:    -- psl err_detect_form_err_cov : cover 
430:    --  {form_err = '1'}; 
Count: 2755
Threshold: 1

PSL cover point:

432:    -- psl err_detect_ack_err_cov : cover 
433:    --  {ack_err = '1'}; 
Count: 1315
Threshold: 1

PSL cover point:

435:    -- psl err_detect_crc_err_cov : cover 
436:    --  {crc_err = '1'}; 
Count: 806
Threshold: 1

PSL cover point:

438:    -- psl err_detect_parity_err_cov : cover 
439:    --  {tran_frame_parity_error = '1'}; 
Count: 164
Threshold: 1

PSL cover point:

441:    -- psl err_capt_q_form_err_cov : cover 
442:    --  {err_capt_err_type_q = ERC_FRM_ERR}; 
Count: 35598960
Threshold: 1

PSL cover point:

444:    -- psl err_capt_q_bit_err_cov : cover 
445:    --  {err_capt_err_type_q = ERC_BIT_ERR}; 
Count: 323384360
Threshold: 1

PSL cover point:

447:    -- psl err_capt_q_crc_err_cov : cover 
448:    --  {err_capt_err_type_q = ERC_CRC_ERR}; 
Count: 836260
Threshold: 1

PSL cover point:

450:    -- psl err_capt_q_ack_err_cov : cover 
451:    --  {err_capt_err_type_q = ERC_ACK_ERR}; 
Count: 3776575
Threshold: 1

PSL cover point:

453:    -- psl err_capt_q_stuff_err_cov : cover 
454:    --  {err_capt_err_type_q = ERC_STUF_ERR}; 
Count: 163222947
Threshold: 1

PSL cover point:

456:    -- psl err_capt_q_prt_err_cov : cover 
457:    --  {err_capt_err_type_q = ERC_PRT_ERR}; 
Count: 758167
Threshold: 1