NVC code coverage report

NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)
SYNC_READ_GEN	100.0 % (2/2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST	100.0 % (1/1)	N.A.	100.0 % (1578/1578)	N.A.	N.A.	N.A.	100.0 % (1579/1579)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

191: int_read_data <= ram_memory(to_integer(unsigned(addr_B)));
Count: 33026
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	327716	1
Bin	1	0	327881	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	723	1
Bin	1	0	723	1

Port:

ADDR_A(4)

	From	To	Count	Threshold
Bin	0	1	101815	1
Bin	1	0	4952814	1

Port:

ADDR_A(3)

	From	To	Count	Threshold
Bin	0	1	128238	1
Bin	1	0	4926381	1

Port:

ADDR_A(2)

	From	To	Count	Threshold
Bin	0	1	109944	1
Bin	1	0	4944819	1

Port:

ADDR_A(1)

	From	To	Count	Threshold
Bin	0	1	4814581	1
Bin	1	0	240470	1

Port:

ADDR_A(0)

	From	To	Count	Threshold
Bin	0	1	3622587	1
Bin	1	0	1433086	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	11545	1
Bin	1	0	11747	1

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	16682	1
Bin	1	0	317940	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	18745	1
Bin	1	0	315867	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	16355	1
Bin	1	0	318255	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	24930	1
Bin	1	0	309700	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	19050	1
Bin	1	0	315574	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	21373	1
Bin	1	0	313249	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	26299	1
Bin	1	0	308325	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	21226	1
Bin	1	0	313396	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	20291	1
Bin	1	0	314331	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	23791	1
Bin	1	0	310829	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	22533	1
Bin	1	0	312085	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	20875	1
Bin	1	0	313753	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	33354	1
Bin	1	0	301287	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	43048	1
Bin	1	0	291580	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	40270	1
Bin	1	0	294355	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	83594	1
Bin	1	0	251022	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	18389	1
Bin	1	0	316247	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	21805	1
Bin	1	0	312833	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	19083	1
Bin	1	0	315545	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	22218	1
Bin	1	0	312418	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	40263	1
Bin	1	0	294363	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	41579	1
Bin	1	0	293051	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	49599	1
Bin	1	0	285039	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	50746	1
Bin	1	0	283882	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	44518	1
Bin	1	0	290128	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	42465	1
Bin	1	0	292177	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	44872	1
Bin	1	0	289760	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	48992	1
Bin	1	0	285632	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	52101	1
Bin	1	0	282533	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	54952	1
Bin	1	0	279687	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	94864	1
Bin	1	0	239763	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	81928	1
Bin	1	0	252719	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	5053365	1
Bin	1	0	7925	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	5053445	1
Bin	1	0	7845	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	5039204	1
Bin	1	0	22086	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	5039488	1
Bin	1	0	21802	1

Port:

ADDR_B(4)

	From	To	Count	Threshold
Bin	0	1	3248	1
Bin	1	0	3413	1

Port:

ADDR_B(3)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	329	1

Port:

ADDR_B(2)

	From	To	Count	Threshold
Bin	0	1	5048	1
Bin	1	0	5213	1

Port:

ADDR_B(1)

	From	To	Count	Threshold
Bin	0	1	4010	1
Bin	1	0	4010	1

Port:

ADDR_B(0)

	From	To	Count	Threshold
Bin	0	1	11143	1
Bin	1	0	11308	1

Port:

DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	471	1

Port:

DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	409	1

Port:

DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	403	1

Port:

DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	827	1
Bin	1	0	978	1

Port:

DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	714	1
Bin	1	0	865	1

Port:

DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	715	1
Bin	1	0	863	1

Port:

DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	510	1
Bin	1	0	659	1

Port:

DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	496	1
Bin	1	0	646	1

Port:

DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	902	1

Port:

DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	608	1
Bin	1	0	759	1

Port:

DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	546	1
Bin	1	0	694	1

Port:

DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	920	1

Port:

DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	774	1

Port:

DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	760	1
Bin	1	0	910	1

Port:

DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	449	1
Bin	1	0	600	1

Port:

DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	551	1

Port:

DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	607	1
Bin	1	0	759	1

Port:

DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	398	1
Bin	1	0	552	1

Port:

DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	633	1
Bin	1	0	786	1

Port:

DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	454	1
Bin	1	0	605	1

Port:

DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	796	1

Port:

DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	822	1

Port:

DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	960	1
Bin	1	0	1109	1

Port:

DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	684	1
Bin	1	0	835	1

Port:

DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	1064	1
Bin	1	0	1208	1

Port:

DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	825	1
Bin	1	0	974	1

Port:

DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	504	1
Bin	1	0	654	1

Port:

DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	600	1

Port:

DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	791	1
Bin	1	0	940	1

Port:

DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	946	1

Port:

DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	793	1
Bin	1	0	943	1

Port:

DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	567	1
Bin	1	0	710	1

Signal:

RAM_MEMORY(0)(31)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4116	1

Signal:

RAM_MEMORY(0)(30)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	4095	1

Signal:

RAM_MEMORY(0)(29)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	4095	1

Signal:

RAM_MEMORY(0)(28)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4136	1

Signal:

RAM_MEMORY(0)(27)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4096	1

Signal:

RAM_MEMORY(0)(26)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4116	1

Signal:

RAM_MEMORY(0)(25)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	4096	1

Signal:

RAM_MEMORY(0)(24)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	4095	1

Signal:

RAM_MEMORY(0)(23)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4116	1

Signal:

RAM_MEMORY(0)(22)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	4115	1

Signal:

RAM_MEMORY(0)(21)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	4095	1

Signal:

RAM_MEMORY(0)(20)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4136	1

Signal:

RAM_MEMORY(0)(19)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4115	1

Signal:

RAM_MEMORY(0)(18)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4116	1

Signal:

RAM_MEMORY(0)(17)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	4116	1

Signal:

RAM_MEMORY(0)(16)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	4095	1

Signal:

RAM_MEMORY(0)(15)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3441	1

Signal:

RAM_MEMORY(0)(14)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	3420	1

Signal:

RAM_MEMORY(0)(13)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3421	1

Signal:

RAM_MEMORY(0)(12)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3441	1

Signal:

RAM_MEMORY(0)(11)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3441	1

Signal:

RAM_MEMORY(0)(10)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3461	1

Signal:

RAM_MEMORY(0)(9)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	3857	1

Signal:

RAM_MEMORY(0)(8)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3441	1

Signal:

RAM_MEMORY(0)(7)

	From	To	Count	Threshold
Bin	0	1	338	1
Bin	1	0	3493	1

Signal:

RAM_MEMORY(0)(6)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	3519	1

Signal:

RAM_MEMORY(0)(5)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	3362	1

Signal:

RAM_MEMORY(0)(4)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3299	1

Signal:

RAM_MEMORY(0)(3)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	3432	1

Signal:

RAM_MEMORY(0)(2)

	From	To	Count	Threshold
Bin	0	1	286	1
Bin	1	0	3469	1

Signal:

RAM_MEMORY(0)(1)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	3434	1

Signal:

RAM_MEMORY(0)(0)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	3443	1

Signal:

RAM_MEMORY(1)(31)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3208	1

Signal:

RAM_MEMORY(1)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3208	1

Signal:

RAM_MEMORY(1)(29)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3189	1

Signal:

RAM_MEMORY(1)(28)

	From	To	Count	Threshold
Bin	0	1	309	1
Bin	1	0	3391	1

Signal:

RAM_MEMORY(1)(27)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	3330	1

Signal:

RAM_MEMORY(1)(26)

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	3352	1

Signal:

RAM_MEMORY(1)(25)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	3376	1

Signal:

RAM_MEMORY(1)(24)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	3371	1

Signal:

RAM_MEMORY(1)(23)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	3394	1

Signal:

RAM_MEMORY(1)(22)

	From	To	Count	Threshold
Bin	0	1	280	1
Bin	1	0	3367	1

Signal:

RAM_MEMORY(1)(21)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	3352	1

Signal:

RAM_MEMORY(1)(20)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	3345	1

Signal:

RAM_MEMORY(1)(19)

	From	To	Count	Threshold
Bin	0	1	302	1
Bin	1	0	3390	1

Signal:

RAM_MEMORY(1)(18)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	3323	1

Signal:

RAM_MEMORY(1)(17)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	3307	1

Signal:

RAM_MEMORY(1)(16)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	3315	1

Signal:

RAM_MEMORY(1)(15)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	3597	1

Signal:

RAM_MEMORY(1)(14)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	3594	1

Signal:

RAM_MEMORY(1)(13)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	3599	1

Signal:

RAM_MEMORY(1)(12)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	3573	1

Signal:

RAM_MEMORY(1)(11)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	3598	1

Signal:

RAM_MEMORY(1)(10)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	3567	1

Signal:

RAM_MEMORY(1)(9)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	3588	1

Signal:

RAM_MEMORY(1)(8)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	3636	1

Signal:

RAM_MEMORY(1)(7)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	3507	1

Signal:

RAM_MEMORY(1)(6)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	3549	1

Signal:

RAM_MEMORY(1)(5)

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	3590	1

Signal:

RAM_MEMORY(1)(4)

	From	To	Count	Threshold
Bin	0	1	177	1
Bin	1	0	3551	1

Signal:

RAM_MEMORY(1)(3)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	3570	1

Signal:

RAM_MEMORY(1)(2)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	3642	1

Signal:

RAM_MEMORY(1)(1)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	3622	1

Signal:

RAM_MEMORY(1)(0)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	3592	1

Signal:

RAM_MEMORY(2)(31)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3791	1

Signal:

RAM_MEMORY(2)(30)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3791	1

Signal:

RAM_MEMORY(2)(29)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	3777	1

Signal:

RAM_MEMORY(2)(28)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3787	1

Signal:

RAM_MEMORY(2)(27)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	3795	1

Signal:

RAM_MEMORY(2)(26)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3773	1

Signal:

RAM_MEMORY(2)(25)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3783	1

Signal:

RAM_MEMORY(2)(24)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	3777	1

Signal:

RAM_MEMORY(2)(23)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	3751	1

Signal:

RAM_MEMORY(2)(22)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3663	1

Signal:

RAM_MEMORY(2)(21)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	3685	1

Signal:

RAM_MEMORY(2)(20)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3663	1

Signal:

RAM_MEMORY(2)(19)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	3713	1

Signal:

RAM_MEMORY(2)(18)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3663	1

Signal:

RAM_MEMORY(2)(17)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3673	1

Signal:

RAM_MEMORY(2)(16)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3681	1

Signal:

RAM_MEMORY(2)(15)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	3759	1

Signal:

RAM_MEMORY(2)(14)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	3750	1

Signal:

RAM_MEMORY(2)(13)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	3765	1

Signal:

RAM_MEMORY(2)(12)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3751	1

Signal:

RAM_MEMORY(2)(11)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3757	1

Signal:

RAM_MEMORY(2)(10)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3753	1

Signal:

RAM_MEMORY(2)(9)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3765	1

Signal:

RAM_MEMORY(2)(8)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3755	1

Signal:

RAM_MEMORY(2)(7)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	3726	1

Signal:

RAM_MEMORY(2)(6)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	3720	1

Signal:

RAM_MEMORY(2)(5)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3708	1

Signal:

RAM_MEMORY(2)(4)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3736	1

Signal:

RAM_MEMORY(2)(3)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	3756	1

Signal:

RAM_MEMORY(2)(2)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	3740	1

Signal:

RAM_MEMORY(2)(1)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3730	1

Signal:

RAM_MEMORY(2)(0)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3732	1

Signal:

RAM_MEMORY(3)(31)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3606	1

Signal:

RAM_MEMORY(3)(30)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3623	1

Signal:

RAM_MEMORY(3)(29)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3621	1

Signal:

RAM_MEMORY(3)(28)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3623	1

Signal:

RAM_MEMORY(3)(27)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	3617	1

Signal:

RAM_MEMORY(3)(26)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3627	1

Signal:

RAM_MEMORY(3)(25)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	3617	1

Signal:

RAM_MEMORY(3)(24)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	3611	1

Signal:

RAM_MEMORY(3)(23)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	3616	1

Signal:

RAM_MEMORY(3)(22)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	3633	1

Signal:

RAM_MEMORY(3)(21)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3620	1

Signal:

RAM_MEMORY(3)(20)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	3627	1

Signal:

RAM_MEMORY(3)(19)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	3633	1

Signal:

RAM_MEMORY(3)(18)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	3616	1

Signal:

RAM_MEMORY(3)(17)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3605	1

Signal:

RAM_MEMORY(3)(16)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	3627	1

Signal:

RAM_MEMORY(3)(15)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3590	1

Signal:

RAM_MEMORY(3)(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3589	1

Signal:

RAM_MEMORY(3)(13)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	3596	1

Signal:

RAM_MEMORY(3)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3583	1

Signal:

RAM_MEMORY(3)(11)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3587	1

Signal:

RAM_MEMORY(3)(10)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	3621	1

Signal:

RAM_MEMORY(3)(9)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	3579	1

Signal:

RAM_MEMORY(3)(8)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3590	1

Signal:

RAM_MEMORY(3)(7)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3561	1

Signal:

RAM_MEMORY(3)(6)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	3562	1

Signal:

RAM_MEMORY(3)(5)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	3612	1

Signal:

RAM_MEMORY(3)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3534	1

Signal:

RAM_MEMORY(3)(3)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3540	1

Signal:

RAM_MEMORY(3)(2)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(1)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3561	1

Signal:

RAM_MEMORY(3)(0)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	3551	1

Signal:

RAM_MEMORY(4)(31)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	3028	1

Signal:

RAM_MEMORY(4)(30)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	3072	1

Signal:

RAM_MEMORY(4)(29)

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	2961	1

Signal:

RAM_MEMORY(4)(28)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	3057	1

Signal:

RAM_MEMORY(4)(27)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	3014	1

Signal:

RAM_MEMORY(4)(26)

	From	To	Count	Threshold
Bin	0	1	166	1
Bin	1	0	3000	1

Signal:

RAM_MEMORY(4)(25)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	3053	1

Signal:

RAM_MEMORY(4)(24)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	3065	1

Signal:

RAM_MEMORY(4)(23)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	3020	1

Signal:

RAM_MEMORY(4)(22)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	3013	1

Signal:

RAM_MEMORY(4)(21)

	From	To	Count	Threshold
Bin	0	1	242	1
Bin	1	0	3009	1

Signal:

RAM_MEMORY(4)(20)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	2998	1

Signal:

RAM_MEMORY(4)(19)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	2963	1

Signal:

RAM_MEMORY(4)(18)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	2979	1

Signal:

RAM_MEMORY(4)(17)

	From	To	Count	Threshold
Bin	0	1	219	1
Bin	1	0	3052	1

Signal:

RAM_MEMORY(4)(16)

	From	To	Count	Threshold
Bin	0	1	191	1
Bin	1	0	3033	1

Signal:

RAM_MEMORY(4)(15)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	2982	1

Signal:

RAM_MEMORY(4)(14)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	2983	1

Signal:

RAM_MEMORY(4)(13)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	2935	1

Signal:

RAM_MEMORY(4)(12)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	3057	1

Signal:

RAM_MEMORY(4)(11)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	3006	1

Signal:

RAM_MEMORY(4)(10)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3012	1

Signal:

RAM_MEMORY(4)(9)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	2978	1

Signal:

RAM_MEMORY(4)(8)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	2983	1

Signal:

RAM_MEMORY(4)(7)

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	2980	1

Signal:

RAM_MEMORY(4)(6)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	2923	1

Signal:

RAM_MEMORY(4)(5)

	From	To	Count	Threshold
Bin	0	1	285	1
Bin	1	0	2980	1

Signal:

RAM_MEMORY(4)(4)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	2969	1

Signal:

RAM_MEMORY(4)(3)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	2953	1

Signal:

RAM_MEMORY(4)(2)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	2997	1

Signal:

RAM_MEMORY(4)(1)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	2962	1

Signal:

RAM_MEMORY(4)(0)

	From	To	Count	Threshold
Bin	0	1	194	1
Bin	1	0	2943	1

Signal:

RAM_MEMORY(5)(31)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	2973	1

Signal:

RAM_MEMORY(5)(30)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	2983	1

Signal:

RAM_MEMORY(5)(29)

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	2947	1

Signal:

RAM_MEMORY(5)(28)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	3015	1

Signal:

RAM_MEMORY(5)(27)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	2995	1

Signal:

RAM_MEMORY(5)(26)

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	3017	1

Signal:

RAM_MEMORY(5)(25)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	2978	1

Signal:

RAM_MEMORY(5)(24)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2983	1

Signal:

RAM_MEMORY(5)(23)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	2882	1

Signal:

RAM_MEMORY(5)(22)

	From	To	Count	Threshold
Bin	0	1	222	1
Bin	1	0	3034	1

Signal:

RAM_MEMORY(5)(21)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2907	1

Signal:

RAM_MEMORY(5)(20)

	From	To	Count	Threshold
Bin	0	1	166	1
Bin	1	0	2934	1

Signal:

RAM_MEMORY(5)(19)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	2960	1

Signal:

RAM_MEMORY(5)(18)

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	2932	1

Signal:

RAM_MEMORY(5)(17)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	3004	1

Signal:

RAM_MEMORY(5)(16)

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	3028	1

Signal:

RAM_MEMORY(5)(15)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	2906	1

Signal:

RAM_MEMORY(5)(14)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	2825	1

Signal:

RAM_MEMORY(5)(13)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	2875	1

Signal:

RAM_MEMORY(5)(12)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	2959	1

Signal:

RAM_MEMORY(5)(11)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2904	1

Signal:

RAM_MEMORY(5)(10)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2951	1

Signal:

RAM_MEMORY(5)(9)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	2887	1

Signal:

RAM_MEMORY(5)(8)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2844	1

Signal:

RAM_MEMORY(5)(7)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	2925	1

Signal:

RAM_MEMORY(5)(6)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2904	1

Signal:

RAM_MEMORY(5)(5)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	2925	1

Signal:

RAM_MEMORY(5)(4)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	3001	1

Signal:

RAM_MEMORY(5)(3)

	From	To	Count	Threshold
Bin	0	1	187	1
Bin	1	0	2884	1

Signal:

RAM_MEMORY(5)(2)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	2949	1

Signal:

RAM_MEMORY(5)(1)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	2866	1

Signal:

RAM_MEMORY(5)(0)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	2980	1

Signal:

RAM_MEMORY(6)(31)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2860	1

Signal:

RAM_MEMORY(6)(30)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	2904	1

Signal:

RAM_MEMORY(6)(29)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	2887	1

Signal:

RAM_MEMORY(6)(28)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2853	1

Signal:

RAM_MEMORY(6)(27)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	2925	1

Signal:

RAM_MEMORY(6)(26)

	From	To	Count	Threshold
Bin	0	1	143	1
Bin	1	0	2890	1

Signal:

RAM_MEMORY(6)(25)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2884	1

Signal:

RAM_MEMORY(6)(24)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2835	1

Signal:

RAM_MEMORY(6)(23)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	2874	1

Signal:

RAM_MEMORY(6)(22)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2844	1

Signal:

RAM_MEMORY(6)(21)

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	2901	1

Signal:

RAM_MEMORY(6)(20)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	2880	1

Signal:

RAM_MEMORY(6)(19)

	From	To	Count	Threshold
Bin	0	1	173	1
Bin	1	0	2928	1

Signal:

RAM_MEMORY(6)(18)

	From	To	Count	Threshold
Bin	0	1	155	1
Bin	1	0	2933	1

Signal:

RAM_MEMORY(6)(17)

	From	To	Count	Threshold
Bin	0	1	157	1
Bin	1	0	2916	1

Signal:

RAM_MEMORY(6)(16)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	2902	1

Signal:

RAM_MEMORY(6)(15)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	2932	1

Signal:

RAM_MEMORY(6)(14)

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	2949	1

Signal:

RAM_MEMORY(6)(13)

	From	To	Count	Threshold
Bin	0	1	212	1
Bin	1	0	2890	1

Signal:

RAM_MEMORY(6)(12)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2904	1

Signal:

RAM_MEMORY(6)(11)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	2891	1

Signal:

RAM_MEMORY(6)(10)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	2855	1

Signal:

RAM_MEMORY(6)(9)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2831	1

Signal:

RAM_MEMORY(6)(8)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	2923	1

Signal:

RAM_MEMORY(6)(7)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	2883	1

Signal:

RAM_MEMORY(6)(6)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2847	1

Signal:

RAM_MEMORY(6)(5)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	2850	1

Signal:

RAM_MEMORY(6)(4)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2855	1

Signal:

RAM_MEMORY(6)(3)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	2862	1

Signal:

RAM_MEMORY(6)(2)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	2848	1

Signal:

RAM_MEMORY(6)(1)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	2908	1

Signal:

RAM_MEMORY(6)(0)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	2863	1

Signal:

RAM_MEMORY(7)(31)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	2748	1

Signal:

RAM_MEMORY(7)(30)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2744	1

Signal:

RAM_MEMORY(7)(29)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2721	1

Signal:

RAM_MEMORY(7)(28)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2735	1

Signal:

RAM_MEMORY(7)(27)

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	2777	1

Signal:

RAM_MEMORY(7)(26)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2839	1

Signal:

RAM_MEMORY(7)(25)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2845	1

Signal:

RAM_MEMORY(7)(24)

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	2779	1

Signal:

RAM_MEMORY(7)(23)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2706	1

Signal:

RAM_MEMORY(7)(22)

	From	To	Count	Threshold
Bin	0	1	134	1
Bin	1	0	2845	1

Signal:

RAM_MEMORY(7)(21)

	From	To	Count	Threshold
Bin	0	1	155	1
Bin	1	0	2803	1

Signal:

RAM_MEMORY(7)(20)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2745	1

Signal:

RAM_MEMORY(7)(19)

	From	To	Count	Threshold
Bin	0	1	155	1
Bin	1	0	2721	1

Signal:

RAM_MEMORY(7)(18)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2757	1

Signal:

RAM_MEMORY(7)(17)

	From	To	Count	Threshold
Bin	0	1	143	1
Bin	1	0	2757	1

Signal:

RAM_MEMORY(7)(16)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2781	1

Signal:

RAM_MEMORY(7)(15)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	2761	1

Signal:

RAM_MEMORY(7)(14)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	2744	1

Signal:

RAM_MEMORY(7)(13)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2768	1

Signal:

RAM_MEMORY(7)(12)

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	2850	1

Signal:

RAM_MEMORY(7)(11)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2777	1

Signal:

RAM_MEMORY(7)(10)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2764	1

Signal:

RAM_MEMORY(7)(9)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	2800	1

Signal:

RAM_MEMORY(7)(8)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	2784	1

Signal:

RAM_MEMORY(7)(7)

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	2725	1

Signal:

RAM_MEMORY(7)(6)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(5)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	2783	1

Signal:

RAM_MEMORY(7)(4)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	2783	1

Signal:

RAM_MEMORY(7)(3)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2822	1

Signal:

RAM_MEMORY(7)(2)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	2729	1

Signal:

RAM_MEMORY(7)(1)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2816	1

Signal:

RAM_MEMORY(7)(0)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2731	1

Signal:

RAM_MEMORY(8)(31)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	2575	1

Signal:

RAM_MEMORY(8)(30)

	From	To	Count	Threshold
Bin	0	1	191	1
Bin	1	0	2656	1

Signal:

RAM_MEMORY(8)(29)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2635	1

Signal:

RAM_MEMORY(8)(28)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	2574	1

Signal:

RAM_MEMORY(8)(27)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2599	1

Signal:

RAM_MEMORY(8)(26)

	From	To	Count	Threshold
Bin	0	1	187	1
Bin	1	0	2637	1

Signal:

RAM_MEMORY(8)(25)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	2604	1

Signal:

RAM_MEMORY(8)(24)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2599	1

Signal:

RAM_MEMORY(8)(23)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2572	1

Signal:

RAM_MEMORY(8)(22)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	2642	1

Signal:

RAM_MEMORY(8)(21)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(20)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	2665	1

Signal:

RAM_MEMORY(8)(19)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	2605	1

Signal:

RAM_MEMORY(8)(18)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	2639	1

Signal:

RAM_MEMORY(8)(17)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	2611	1

Signal:

RAM_MEMORY(8)(16)

	From	To	Count	Threshold
Bin	0	1	187	1
Bin	1	0	2596	1

Signal:

RAM_MEMORY(8)(15)

	From	To	Count	Threshold
Bin	0	1	157	1
Bin	1	0	2632	1

Signal:

RAM_MEMORY(8)(14)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	2656	1

Signal:

RAM_MEMORY(8)(13)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2592	1

Signal:

RAM_MEMORY(8)(12)

	From	To	Count	Threshold
Bin	0	1	191	1
Bin	1	0	2591	1

Signal:

RAM_MEMORY(8)(11)

	From	To	Count	Threshold
Bin	0	1	186	1
Bin	1	0	2653	1

Signal:

RAM_MEMORY(8)(10)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2618	1

Signal:

RAM_MEMORY(8)(9)

	From	To	Count	Threshold
Bin	0	1	177	1
Bin	1	0	2640	1

Signal:

RAM_MEMORY(8)(8)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2635	1

Signal:

RAM_MEMORY(8)(7)

	From	To	Count	Threshold
Bin	0	1	126	1
Bin	1	0	2574	1

Signal:

RAM_MEMORY(8)(6)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2572	1

Signal:

RAM_MEMORY(8)(5)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2578	1

Signal:

RAM_MEMORY(8)(4)

	From	To	Count	Threshold
Bin	0	1	148	1
Bin	1	0	2621	1

Signal:

RAM_MEMORY(8)(3)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2620	1

Signal:

RAM_MEMORY(8)(2)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2640	1

Signal:

RAM_MEMORY(8)(1)

	From	To	Count	Threshold
Bin	0	1	194	1
Bin	1	0	2666	1

Signal:

RAM_MEMORY(8)(0)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2582	1

Signal:

RAM_MEMORY(9)(31)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	2477	1

Signal:

RAM_MEMORY(9)(30)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2517	1

Signal:

RAM_MEMORY(9)(29)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2470	1

Signal:

RAM_MEMORY(9)(28)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	2525	1

Signal:

RAM_MEMORY(9)(27)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2470	1

Signal:

RAM_MEMORY(9)(26)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2510	1

Signal:

RAM_MEMORY(9)(25)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2554	1

Signal:

RAM_MEMORY(9)(24)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2510	1

Signal:

RAM_MEMORY(9)(23)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2543	1

Signal:

RAM_MEMORY(9)(22)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2542	1

Signal:

RAM_MEMORY(9)(21)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2481	1

Signal:

RAM_MEMORY(9)(20)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(9)(19)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2525	1

Signal:

RAM_MEMORY(9)(18)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2480	1

Signal:

RAM_MEMORY(9)(17)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2524	1

Signal:

RAM_MEMORY(9)(16)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2497	1

Signal:

RAM_MEMORY(9)(15)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	2564	1

Signal:

RAM_MEMORY(9)(14)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2498	1

Signal:

RAM_MEMORY(9)(13)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2513	1

Signal:

RAM_MEMORY(9)(12)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2495	1

Signal:

RAM_MEMORY(9)(11)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2551	1

Signal:

RAM_MEMORY(9)(10)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2520	1

Signal:

RAM_MEMORY(9)(9)

	From	To	Count	Threshold
Bin	0	1	148	1
Bin	1	0	2511	1

Signal:

RAM_MEMORY(9)(8)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2558	1

Signal:

RAM_MEMORY(9)(7)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	2545	1

Signal:

RAM_MEMORY(9)(6)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2517	1

Signal:

RAM_MEMORY(9)(5)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	2492	1

Signal:

RAM_MEMORY(9)(4)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2560	1

Signal:

RAM_MEMORY(9)(3)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2484	1

Signal:

RAM_MEMORY(9)(2)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	2474	1

Signal:

RAM_MEMORY(9)(1)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2495	1

Signal:

RAM_MEMORY(9)(0)

	From	To	Count	Threshold
Bin	0	1	173	1
Bin	1	0	2508	1

Signal:

RAM_MEMORY(10)(31)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(30)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2405	1

Signal:

RAM_MEMORY(10)(29)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2472	1

Signal:

RAM_MEMORY(10)(28)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2415	1

Signal:

RAM_MEMORY(10)(27)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(26)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(25)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(24)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(23)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2472	1

Signal:

RAM_MEMORY(10)(22)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(21)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(20)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2405	1

Signal:

RAM_MEMORY(10)(19)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(18)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2405	1

Signal:

RAM_MEMORY(10)(17)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(15)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2472	1

Signal:

RAM_MEMORY(10)(14)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(13)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(12)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	2405	1

Signal:

RAM_MEMORY(10)(11)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(10)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(9)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2482	1

Signal:

RAM_MEMORY(10)(8)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2482	1

Signal:

RAM_MEMORY(10)(7)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(5)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(3)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(2)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(1)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2472	1

Signal:

RAM_MEMORY(10)(0)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2472	1

Signal:

RAM_MEMORY(11)(31)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(11)(30)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	2315	1

Signal:

RAM_MEMORY(11)(29)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(28)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(11)(27)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(26)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(11)(25)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(24)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(23)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(22)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(21)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2315	1

Signal:

RAM_MEMORY(11)(20)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(19)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(18)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2306	1

Signal:

RAM_MEMORY(11)(17)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	2265	1

Signal:

RAM_MEMORY(11)(16)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2306	1

Signal:

RAM_MEMORY(11)(15)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(11)(14)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2306	1

Signal:

RAM_MEMORY(11)(13)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2240	1

Signal:

RAM_MEMORY(11)(12)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2306	1

Signal:

RAM_MEMORY(11)(11)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(10)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(9)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(8)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2256	1

Signal:

RAM_MEMORY(11)(7)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2315	1

Signal:

RAM_MEMORY(11)(6)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2322	1

Signal:

RAM_MEMORY(11)(5)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(4)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2315	1

Signal:

RAM_MEMORY(11)(3)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2265	1

Signal:

RAM_MEMORY(11)(2)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(11)(1)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2331	1

Signal:

RAM_MEMORY(11)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(12)(31)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2165	1

Signal:

RAM_MEMORY(12)(30)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2115	1

Signal:

RAM_MEMORY(12)(29)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2100	1

Signal:

RAM_MEMORY(12)(28)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2172	1

Signal:

RAM_MEMORY(12)(27)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	2092	1

Signal:

RAM_MEMORY(12)(26)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2115	1

Signal:

RAM_MEMORY(12)(25)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2165	1

Signal:

RAM_MEMORY(12)(24)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2100	1

Signal:

RAM_MEMORY(12)(23)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2180	1

Signal:

RAM_MEMORY(12)(22)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2092	1

Signal:

RAM_MEMORY(12)(21)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	2092	1

Signal:

RAM_MEMORY(12)(20)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2172	1

Signal:

RAM_MEMORY(12)(19)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2157	1

Signal:

RAM_MEMORY(12)(18)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	2107	1

Signal:

RAM_MEMORY(12)(17)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2165	1

Signal:

RAM_MEMORY(12)(16)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2165	1

Signal:

RAM_MEMORY(12)(15)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2107	1

Signal:

RAM_MEMORY(12)(14)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2092	1

Signal:

RAM_MEMORY(12)(13)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2115	1

Signal:

RAM_MEMORY(12)(12)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2157	1

Signal:

RAM_MEMORY(12)(11)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2172	1

Signal:

RAM_MEMORY(12)(10)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2172	1

Signal:

RAM_MEMORY(12)(9)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2172	1

Signal:

RAM_MEMORY(12)(8)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2180	1

Signal:

RAM_MEMORY(12)(7)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2107	1

Signal:

RAM_MEMORY(12)(6)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2172	1

Signal:

RAM_MEMORY(12)(5)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2180	1

Signal:

RAM_MEMORY(12)(4)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2115	1

Signal:

RAM_MEMORY(12)(3)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2107	1

Signal:

RAM_MEMORY(12)(2)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2157	1

Signal:

RAM_MEMORY(12)(1)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2115	1

Signal:

RAM_MEMORY(12)(0)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2157	1

Signal:

RAM_MEMORY(13)(31)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(30)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(29)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(13)(28)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2008	1

Signal:

RAM_MEMORY(13)(27)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1944	1

Signal:

RAM_MEMORY(13)(26)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(25)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1944	1

Signal:

RAM_MEMORY(13)(24)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(13)(23)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2008	1

Signal:

RAM_MEMORY(13)(22)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(13)(21)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(20)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(19)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	2008	1

Signal:

RAM_MEMORY(13)(18)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1944	1

Signal:

RAM_MEMORY(13)(17)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1944	1

Signal:

RAM_MEMORY(13)(16)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(13)(15)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1944	1

Signal:

RAM_MEMORY(13)(14)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(13)(13)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	1951	1

Signal:

RAM_MEMORY(13)(12)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(11)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(10)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2015	1

Signal:

RAM_MEMORY(13)(9)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2015	1

Signal:

RAM_MEMORY(13)(8)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	1951	1

Signal:

RAM_MEMORY(13)(7)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2015	1

Signal:

RAM_MEMORY(13)(6)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(5)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(13)(4)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(3)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(2)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2008	1

Signal:

RAM_MEMORY(13)(1)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2029	1

Signal:

RAM_MEMORY(13)(0)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2022	1

Signal:

RAM_MEMORY(14)(31)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1859	1

Signal:

RAM_MEMORY(14)(30)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1796	1

Signal:

RAM_MEMORY(14)(29)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1859	1

Signal:

RAM_MEMORY(14)(28)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1872	1

Signal:

RAM_MEMORY(14)(27)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1815	1

Signal:

RAM_MEMORY(14)(26)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1796	1

Signal:

RAM_MEMORY(14)(25)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1815	1

Signal:

RAM_MEMORY(14)(24)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1809	1

Signal:

RAM_MEMORY(14)(23)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	1865	1

Signal:

RAM_MEMORY(14)(22)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1878	1

Signal:

RAM_MEMORY(14)(21)

	From	To	Count	Threshold
Bin	0	1	134	1
Bin	1	0	1878	1

Signal:

RAM_MEMORY(14)(20)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	1878	1

Signal:

RAM_MEMORY(14)(19)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1859	1

Signal:

RAM_MEMORY(14)(18)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1859	1

Signal:

RAM_MEMORY(14)(17)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1802	1

Signal:

RAM_MEMORY(14)(16)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1865	1

Signal:

RAM_MEMORY(14)(15)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	1815	1

Signal:

RAM_MEMORY(14)(14)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	1815	1

Signal:

RAM_MEMORY(14)(13)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	1865	1

Signal:

RAM_MEMORY(14)(12)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	1878	1

Signal:

RAM_MEMORY(14)(11)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	1865	1

Signal:

RAM_MEMORY(14)(10)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	1865	1

Signal:

RAM_MEMORY(14)(9)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1796	1

Signal:

RAM_MEMORY(14)(8)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1802	1

Signal:

RAM_MEMORY(14)(7)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1796	1

Signal:

RAM_MEMORY(14)(6)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1809	1

Signal:

RAM_MEMORY(14)(5)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1815	1

Signal:

RAM_MEMORY(14)(4)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1802	1

Signal:

RAM_MEMORY(14)(3)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1859	1

Signal:

RAM_MEMORY(14)(2)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1815	1

Signal:

RAM_MEMORY(14)(1)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1809	1

Signal:

RAM_MEMORY(14)(0)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1809	1

Signal:

RAM_MEMORY(15)(31)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1653	1

Signal:

RAM_MEMORY(15)(30)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	1727	1

Signal:

RAM_MEMORY(15)(29)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1665	1

Signal:

RAM_MEMORY(15)(28)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(27)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1722	1

Signal:

RAM_MEMORY(15)(26)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(25)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1715	1

Signal:

RAM_MEMORY(15)(24)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(23)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1722	1

Signal:

RAM_MEMORY(15)(22)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1660	1

Signal:

RAM_MEMORY(15)(21)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	1665	1

Signal:

RAM_MEMORY(15)(20)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(19)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	1715	1

Signal:

RAM_MEMORY(15)(18)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1722	1

Signal:

RAM_MEMORY(15)(17)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1710	1

Signal:

RAM_MEMORY(15)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(15)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1653	1

Signal:

RAM_MEMORY(15)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(13)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1660	1

Signal:

RAM_MEMORY(15)(12)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1660	1

Signal:

RAM_MEMORY(15)(11)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1653	1

Signal:

RAM_MEMORY(15)(10)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1665	1

Signal:

RAM_MEMORY(15)(9)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1653	1

Signal:

RAM_MEMORY(15)(8)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	1727	1

Signal:

RAM_MEMORY(15)(7)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	1727	1

Signal:

RAM_MEMORY(15)(6)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	1665	1

Signal:

RAM_MEMORY(15)(5)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1653	1

Signal:

RAM_MEMORY(15)(4)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	1715	1

Signal:

RAM_MEMORY(15)(3)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1648	1

Signal:

RAM_MEMORY(15)(2)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	1727	1

Signal:

RAM_MEMORY(15)(1)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1660	1

Signal:

RAM_MEMORY(15)(0)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1660	1

Signal:

RAM_MEMORY(16)(31)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1530	1

Signal:

RAM_MEMORY(16)(30)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1530	1

Signal:

RAM_MEMORY(16)(29)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(27)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(26)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(25)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(24)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(23)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(22)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(21)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(20)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(19)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(18)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(17)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1530	1

Signal:

RAM_MEMORY(16)(16)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(15)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(14)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(13)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(12)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(11)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1530	1

Signal:

RAM_MEMORY(16)(10)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(9)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(7)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1526	1

Signal:

RAM_MEMORY(16)(5)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(4)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(3)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1587	1

Signal:

RAM_MEMORY(16)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1530	1

Signal:

RAM_MEMORY(16)(1)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(16)(0)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1591	1

Signal:

RAM_MEMORY(17)(31)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(29)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1437	1

Signal:

RAM_MEMORY(17)(28)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(27)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(26)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1377	1

Signal:

RAM_MEMORY(17)(25)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(24)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(23)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(22)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(21)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(20)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1437	1

Signal:

RAM_MEMORY(17)(19)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1437	1

Signal:

RAM_MEMORY(17)(18)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1437	1

Signal:

RAM_MEMORY(17)(17)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(16)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(13)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(12)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(11)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(10)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1377	1

Signal:

RAM_MEMORY(17)(9)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1437	1

Signal:

RAM_MEMORY(17)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(17)(7)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(6)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1437	1

Signal:

RAM_MEMORY(17)(5)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(4)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(3)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(2)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(1)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1440	1

Signal:

RAM_MEMORY(17)(0)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1380	1

Signal:

RAM_MEMORY(18)(31)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(30)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(29)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(28)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(27)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(26)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(25)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1287	1

Signal:

RAM_MEMORY(18)(24)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(23)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(18)(22)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(21)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(19)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(18)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(17)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1287	1

Signal:

RAM_MEMORY(18)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(15)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(18)(14)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(13)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(18)(12)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(18)(11)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(10)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(9)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(8)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1287	1

Signal:

RAM_MEMORY(18)(7)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(6)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(18)(5)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(4)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1289	1

Signal:

RAM_MEMORY(18)(3)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1228	1

Signal:

RAM_MEMORY(18)(2)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1287	1

Signal:

RAM_MEMORY(18)(1)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(18)(0)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1230	1

Signal:

RAM_MEMORY(19)(31)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(30)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(29)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(28)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(27)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(26)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(25)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(24)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(23)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(22)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(21)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(19)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(18)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(17)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(16)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(15)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(13)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(12)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(11)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(10)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(9)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(8)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(7)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1138	1

Signal:

RAM_MEMORY(19)(6)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(5)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1137	1

Signal:

RAM_MEMORY(19)(4)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(3)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(19)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(1)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1080	1

Signal:

RAM_MEMORY(19)(0)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1079	1

Signal:

RAM_MEMORY(20)(31)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1061	1

Signal:

RAM_MEMORY(20)(30)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	1020	1

Signal:

RAM_MEMORY(20)(29)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(28)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(27)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(26)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(25)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1061	1

Signal:

RAM_MEMORY(20)(24)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1020	1

Signal:

RAM_MEMORY(20)(23)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1061	1

Signal:

RAM_MEMORY(20)(22)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	1020	1

Signal:

RAM_MEMORY(20)(21)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(20)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(19)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1041	1

Signal:

RAM_MEMORY(20)(18)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1020	1

Signal:

RAM_MEMORY(20)(17)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1061	1

Signal:

RAM_MEMORY(20)(16)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	1020	1

Signal:

RAM_MEMORY(20)(15)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	819	1

Signal:

RAM_MEMORY(20)(14)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	778	1

Signal:

RAM_MEMORY(20)(13)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	778	1

Signal:

RAM_MEMORY(20)(12)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	779	1

Signal:

RAM_MEMORY(20)(11)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	820	1

Signal:

RAM_MEMORY(20)(10)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	847	1

Signal:

RAM_MEMORY(20)(9)

	From	To	Count	Threshold
Bin	0	1	166	1
Bin	1	0	891	1

Signal:

RAM_MEMORY(20)(8)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	860	1

Signal:

RAM_MEMORY(20)(7)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	811	1

Signal:

RAM_MEMORY(20)(6)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	770	1

Signal:

RAM_MEMORY(20)(5)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	770	1

Signal:

RAM_MEMORY(20)(4)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	770	1

Signal:

RAM_MEMORY(20)(3)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	791	1

Signal:

RAM_MEMORY(20)(2)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	833	1

Signal:

RAM_MEMORY(20)(1)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	818	1

Signal:

RAM_MEMORY(20)(0)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	825	1

Signal:

INT_READ_DATA(31)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	473	1

Signal:

INT_READ_DATA(30)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	410	1

Signal:

INT_READ_DATA(29)

	From	To	Count	Threshold
Bin	0	1	250	1
Bin	1	0	405	1

Signal:

INT_READ_DATA(28)

	From	To	Count	Threshold
Bin	0	1	1179	1
Bin	1	0	1334	1

Signal:

INT_READ_DATA(27)

	From	To	Count	Threshold
Bin	0	1	977	1
Bin	1	0	1132	1

Signal:

INT_READ_DATA(26)

	From	To	Count	Threshold
Bin	0	1	1023	1
Bin	1	0	1178	1

Signal:

INT_READ_DATA(25)

	From	To	Count	Threshold
Bin	0	1	718	1
Bin	1	0	873	1

Signal:

INT_READ_DATA(24)

	From	To	Count	Threshold
Bin	0	1	698	1
Bin	1	0	853	1

Signal:

INT_READ_DATA(23)

	From	To	Count	Threshold
Bin	0	1	1065	1
Bin	1	0	1220	1

Signal:

INT_READ_DATA(22)

	From	To	Count	Threshold
Bin	0	1	892	1
Bin	1	0	1047	1

Signal:

INT_READ_DATA(21)

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	923	1

Signal:

INT_READ_DATA(20)

	From	To	Count	Threshold
Bin	0	1	1102	1
Bin	1	0	1257	1

Signal:

INT_READ_DATA(19)

	From	To	Count	Threshold
Bin	0	1	955	1
Bin	1	0	1110	1

Signal:

INT_READ_DATA(18)

	From	To	Count	Threshold
Bin	0	1	1150	1
Bin	1	0	1305	1

Signal:

INT_READ_DATA(17)

	From	To	Count	Threshold
Bin	0	1	564	1
Bin	1	0	719	1

Signal:

INT_READ_DATA(16)

	From	To	Count	Threshold
Bin	0	1	486	1
Bin	1	0	641	1

Signal:

INT_READ_DATA(15)

	From	To	Count	Threshold
Bin	0	1	801	1
Bin	1	0	956	1

Signal:

INT_READ_DATA(14)

	From	To	Count	Threshold
Bin	0	1	492	1
Bin	1	0	647	1

Signal:

INT_READ_DATA(13)

	From	To	Count	Threshold
Bin	0	1	809	1
Bin	1	0	964	1

Signal:

INT_READ_DATA(12)

	From	To	Count	Threshold
Bin	0	1	549	1
Bin	1	0	704	1

Signal:

INT_READ_DATA(11)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	966	1

Signal:

INT_READ_DATA(10)

	From	To	Count	Threshold
Bin	0	1	855	1
Bin	1	0	1010	1

Signal:

INT_READ_DATA(9)

	From	To	Count	Threshold
Bin	0	1	1187	1
Bin	1	0	1342	1

Signal:

INT_READ_DATA(8)

	From	To	Count	Threshold
Bin	0	1	886	1
Bin	1	0	1041	1

Signal:

INT_READ_DATA(7)

	From	To	Count	Threshold
Bin	0	1	1402	1
Bin	1	0	1557	1

Signal:

INT_READ_DATA(6)

	From	To	Count	Threshold
Bin	0	1	896	1
Bin	1	0	1051	1

Signal:

INT_READ_DATA(5)

	From	To	Count	Threshold
Bin	0	1	647	1
Bin	1	0	802	1

Signal:

INT_READ_DATA(4)

	From	To	Count	Threshold
Bin	0	1	571	1
Bin	1	0	726	1

Signal:

INT_READ_DATA(3)

	From	To	Count	Threshold
Bin	0	1	1020	1
Bin	1	0	1175	1

Signal:

INT_READ_DATA(2)

	From	To	Count	Threshold
Bin	0	1	1053	1
Bin	1	0	1208	1

Signal:

INT_READ_DATA(1)

	From	To	Count	Threshold
Bin	0	1	999	1
Bin	1	0	1154	1

Signal:

INT_READ_DATA(0)

	From	To	Count	Threshold
Bin	0	1	735	1
Bin	1	0	890	1

Signal:

BYTE_WE(3)

	From	To	Count	Threshold
Bin	0	1	11545	1
Bin	1	0	11710	1

Signal:

BYTE_WE(2)

	From	To	Count	Threshold
Bin	0	1	11545	1
Bin	1	0	11710	1

Signal:

BYTE_WE(1)

	From	To	Count	Threshold
Bin	0	1	11545	1
Bin	1	0	11710	1

Signal:

BYTE_WE(0)

	From	To	Count	Threshold
Bin	0	1	11545	1
Bin	1	0	11710	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: