NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_FALSE_GEN

File:  /__w/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_FALSE_GEN 100.0 % (5/5) N.A. N.A. N.A. N.A. N.A. 100.0 % (5/5)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

270:        parity_mismatch <= '0'; 
Count: 940
Threshold: 1

Signal assignment statement:

271:        parity_read_real <= '0'; 
Count: 940
Threshold: 1

Signal assignment statement:

272:        parity_read_exp <= '0'; 
Count: 940
Threshold: 1

Signal assignment statement:

273:        parity_word <= (others => '0'); 
Count: 940
Threshold: 1

Signal assignment statement:

274:        parity_write <= '0'; 
Count: 940
Threshold: 1

Uncovered branches:

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Covered branches:

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Covered toggles:

Uncovered expressions:

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Covered expressions:

Uncovered FSM states:

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Uncovered functional coverage:

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Covered functional coverage: