NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.SSP_CFG_SSP_OFFSET_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (60/60)	100.0 % (6/6)	N.A.	N.A.	100.0 % (67/67)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 277784
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	31028760	1
Bin	1	0	31030360	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	70931	1
Bin	1	0	1018914	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	108138	1
Bin	1	0	981707	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	74867	1
Bin	1	0	1014978	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	80468	1
Bin	1	0	1009377	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	110009	1
Bin	1	0	979836	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	131558	1
Bin	1	0	958287	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	123951	1
Bin	1	0	965894	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	193513	1
Bin	1	0	896332	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	125757	1
Bin	1	0	127357	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	3458	1
Bin	1	0	5058	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

REG_VALUE(7)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1644	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1652	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	4305	1
Bin	1	0	2715	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	527	1
Bin	1	0	2127	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	2899	1
Bin	1	0	1309	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	2397	1
Bin	1	0	3997	1

Signal:

REG_VALUE_R(7)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	8051	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	8051	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	8028	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	8021	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	5279	1
Bin	1	0	2797	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	542	1
Bin	1	0	7534	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	6725	1
Bin	1	0	1351	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	2460	1
Bin	1	0	5616	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	3333	1
Bin	1	0	4933	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	3458	1
Bin	'1'	'0'	135479	1
Bin	'1'	'1'	3383	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	62377	1
Bin	'1'	'0'	50	1
Bin	'1'	'1'	3333	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.SSP_CFG_SSP_OFFSET_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

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Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

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Uncovered functional coverage:

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Covered functional coverage: