NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_FSM_INST	100.0 % (79/79)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (410/410)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready)) 
178:                          else 
179:                      '0';

Count: 4000
Threshold: 1

Signal assignment statement:

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
Count: 2033
Threshold: 1

Signal assignment statement:

179: '0';
Count: 1967
Threshold: 1

If statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED) 
184:                        else 
185:                    '0';

Count: 7564
Threshold: 1

Signal assignment statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

Count: 3044
Threshold: 1

Signal assignment statement:

185: '0';
Count: 4520
Threshold: 1

If statement:

187:    txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') 
188:                                 else 
189:                     (others => '0');

Count: 41584
Threshold: 1

Signal assignment statement:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')
Count: 3864
Threshold: 1

Signal assignment statement:

189: (others => '0');
Count: 37720
Threshold: 1

If statement:

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
192:                   '0';

Count: 1686
Threshold: 1

Signal assignment statement:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else
Count: 183
Threshold: 1

Signal assignment statement:

192: '0';
Count: 1503
Threshold: 1

Signal assignment statement:

203: next_state <= curr_state;
Count: 18389
Threshold: 1

Sequential statement:

205:        case curr_state is 
206: 
...
360: 
361:        end case;

Count: 18389
Threshold: 1

If statement:

213:            if (tx_command_txcr_valid = '1') then 
214:                next_state <= s_txt_ready; 
215:            end if;

Count: 8098
Threshold: 1

Signal assignment statement:

214: next_state <= s_txt_ready;
Count: 413
Threshold: 1

If statement:

223:            if (go_to_failed = '1') then 
224:                next_state <= s_txt_failed; 
...
242:                next_state <= s_txt_aborted; 
243:            end if;

Count: 3860
Threshold: 1

Signal assignment statement:

224: next_state <= s_txt_failed;
Count: 32
Threshold: 1

Signal assignment statement:

228: next_state <= s_txt_parity_err;
Count: 240
Threshold: 1

If statement:

234:                if (abort_applied = '1') then 
235:                    next_state <= s_txt_ab_prog; 
236:                else 
237:                    next_state <= s_txt_tx_prog; 
238:                end if;

Count: 889
Threshold: 1

Signal assignment statement:

235: next_state <= s_txt_ab_prog;
Count: 4
Threshold: 1

Signal assignment statement:

237: next_state <= s_txt_tx_prog;
Count: 885
Threshold: 1

Signal assignment statement:

242: next_state <= s_txt_aborted;
Count: 113
Threshold: 1

If statement:

251:            if (go_to_failed = '1') then 
252:                next_state <= s_txt_failed; 
...
276:                next_state <= s_txt_ab_prog; 
277:            end if;

Count: 3022
Threshold: 1

Signal assignment statement:

252: next_state <= s_txt_failed;
Count: 8
Threshold: 1

Signal assignment statement:

256: next_state <= s_txt_parity_err;
Count: 98
Threshold: 1

Signal assignment statement:

260: next_state <= s_txt_failed;
Count: 245
Threshold: 1

Signal assignment statement:

264: next_state <= s_txt_ok;
Count: 384
Threshold: 1

If statement:

268:                if (abort_applied = '1') then 
269:                    next_state <= s_txt_aborted; 
270:                else 
271:                    next_state <= s_txt_ready; 
272:                end if;

Count: 160
Threshold: 1

Signal assignment statement:

269: next_state <= s_txt_aborted;
Count: 4
Threshold: 1

Signal assignment statement:

271: next_state <= s_txt_ready;
Count: 156
Threshold: 1

Signal assignment statement:

276: next_state <= s_txt_ab_prog;
Count: 130
Threshold: 1

If statement:

285:            if (go_to_failed = '1') then 
286:                next_state <= s_txt_failed; 
...
302:                next_state <= s_txt_aborted; 
303:            end if;

Count: 285
Threshold: 1

Signal assignment statement:

286: next_state <= s_txt_failed;
Count: 4
Threshold: 1

Signal assignment statement:

290: next_state <= s_txt_parity_err;
Count: 15
Threshold: 1

Signal assignment statement:

294: next_state <= s_txt_failed;
Count: 22
Threshold: 1

Signal assignment statement:

298: next_state <= s_txt_ok;
Count: 12
Threshold: 1

Signal assignment statement:

302: next_state <= s_txt_aborted;
Count: 19
Threshold: 1

If statement:

311:            if (tx_command_txcr_valid = '1') then 
312:                next_state <= s_txt_ready; 
...
316:                next_state <= s_txt_empty; 
317:            end if;

Count: 945
Threshold: 1

Signal assignment statement:

312: next_state <= s_txt_ready;
Count: 258
Threshold: 1

Signal assignment statement:

316: next_state <= s_txt_empty;
Count: 20
Threshold: 1

If statement:

325:            if (tx_command_txcr_valid = '1') then 
326:                next_state <= s_txt_ready; 
...
330:                next_state <= s_txt_empty; 
331:            end if;

Count: 536
Threshold: 1

Signal assignment statement:

326: next_state <= s_txt_ready;
Count: 124
Threshold: 1

Signal assignment statement:

330: next_state <= s_txt_empty;
Count: 4
Threshold: 1

If statement:

339:            if (tx_command_txcr_valid = '1') then 
340:                next_state <= s_txt_ready; 
...
344:                next_state <= s_txt_empty; 
345:            end if;

Count: 1193
Threshold: 1

Signal assignment statement:

340: next_state <= s_txt_ready;
Count: 294
Threshold: 1

Signal assignment statement:

344: next_state <= s_txt_empty;
Count: 13
Threshold: 1

If statement:

353:            if (tx_command_txcr_valid = '1') then 
354:                next_state <= s_txt_ready; 
...
358:                next_state <= s_txt_empty; 
359:            end if;

Count: 450
Threshold: 1

Signal assignment statement:

354: next_state <= s_txt_ready;
Count: 54
Threshold: 1

Signal assignment statement:

358: next_state <= s_txt_empty;
Count: 51
Threshold: 1

If statement:

368:    txt_fsm_ce <= '1' when (next_state /= curr_state) else 
369:                  '0';

Count: 8282
Threshold: 1

Signal assignment statement:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else
Count: 3813
Threshold: 1

Signal assignment statement:

369: '0';
Count: 4469
Threshold: 1

If statement:

376:        if (res_n = '0') then 
377:            curr_state <= s_txt_empty; 
...
381:            end if; 
382:        end if;

Count: 162324562
Threshold: 1

Signal assignment statement:

377: curr_state <= s_txt_empty;
Count: 1737046
Threshold: 1

If statement:

379:            if (txt_fsm_ce = '1') then 
380:                curr_state <= next_state; 
381:            end if;

Count: 80292006
Threshold: 1

Signal assignment statement:

380: curr_state <= next_state;
Count: 3044
Threshold: 1

If statement:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog)) 
392:                                  else 
393:                            '1';

Count: 4000
Threshold: 1

Signal assignment statement:

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
Count: 2033
Threshold: 1

Signal assignment statement:

393: '1';
Count: 1967
Threshold: 1

If statement:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
...
406:                           else 
407:                       '0';

Count: 18466
Threshold: 1

Signal assignment statement:

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
Count: 2733
Threshold: 1

Signal assignment statement:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

Count: 40
Threshold: 1

Signal assignment statement:

407: '0';
Count: 15693
Threshold: 1

If statement:

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
412:                            else 
413:                        '0';

Count: 5022
Threshold: 1

Signal assignment statement:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))
Count: 1083
Threshold: 1

Signal assignment statement:

413: '0';
Count: 3939
Threshold: 1

Sequential statement:

416:    with curr_state select txtb_state <= 
417:        TXT_RDY   when s_txt_ready, 
...
423:        TXT_ETY   when s_txt_empty, 
424:        TXT_PER   when s_txt_parity_err;

Count: 4000
Threshold: 1

Signal assignment statement:

417: TXT_RDY when s_txt_ready,
Count: 1083
Threshold: 1

Signal assignment statement:

418: TXT_TRAN when s_txt_tx_prog,
Count: 885
Threshold: 1

Signal assignment statement:

419: TXT_ABTP when s_txt_ab_prog,
Count: 65
Threshold: 1

Signal assignment statement:

420: TXT_TOK when s_txt_ok,
Count: 396
Threshold: 1

Signal assignment statement:

421: TXT_ERR when s_txt_failed,
Count: 295
Threshold: 1

Signal assignment statement:

422: TXT_ABT when s_txt_aborted,
Count: 132
Threshold: 1

Signal assignment statement:

423: TXT_ETY when s_txt_empty,
Count: 1040
Threshold: 1

Signal assignment statement:

424: TXT_PER when s_txt_parity_err;
Count: 104
Threshold: 1

If statement:

432:    txtb_unmask_data_ram <= '1' when (transient_state = '1') 
433:                                else 
434:                            '0';

Count: 3174
Threshold: 1

Signal assignment statement:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')
Count: 927
Threshold: 1

Signal assignment statement:

434: '0';
Count: 2247
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	True	2033	1
Bin	False	1967	1

"if" / "when" / "else" condition:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	3044	1
Bin	False	4520	1

"if" / "when" / "else" condition:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	True	3864	1
Bin	False	37720	1

"if" / "when" / "else" condition:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	True	183	1
Bin	False	1503	1

"case" / "with" / "select" choice:

210: when s_txt_empty =>

	Choice of	Count	Threshold
Bin	`s_txt_empty`	8098	1

"if" / "when" / "else" condition:

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	413	1
Bin	False	7685	1

"case" / "with" / "select" choice:

220: when s_txt_ready =>

	Choice of	Count	Threshold
Bin	`s_txt_ready`	3860	1

"if" / "when" / "else" condition:

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	32	1
Bin	False	3828	1

"if" / "when" / "else" condition:

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	240	1
Bin	False	3588	1

"if" / "when" / "else" condition:

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	889	1
Bin	False	2699	1

"if" / "when" / "else" condition:

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	885	1

"if" / "when" / "else" condition:

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	True	113	1
Bin	False	2586	1

"case" / "with" / "select" choice:

248: when s_txt_tx_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	3022	1

"if" / "when" / "else" condition:

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	8	1
Bin	False	3014	1

"if" / "when" / "else" condition:

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	98	1
Bin	False	2916	1

"if" / "when" / "else" condition:

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	245	1
Bin	False	2671	1

"if" / "when" / "else" condition:

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	384	1
Bin	False	2287	1

"if" / "when" / "else" condition:

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	160	1
Bin	False	2127	1

"if" / "when" / "else" condition:

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	156	1

"if" / "when" / "else" condition:

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	130	1
Bin	False	1997	1

"case" / "with" / "select" choice:

282: when s_txt_ab_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	285	1

"if" / "when" / "else" condition:

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	281	1

"if" / "when" / "else" condition:

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	15	1
Bin	False	266	1

"if" / "when" / "else" condition:

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	22	1
Bin	False	244	1

"if" / "when" / "else" condition:

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	12	1
Bin	False	232	1

"if" / "when" / "else" condition:

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	19	1
Bin	False	213	1

"case" / "with" / "select" choice:

308: when s_txt_failed =>

	Choice of	Count	Threshold
Bin	`s_txt_failed`	945	1

"if" / "when" / "else" condition:

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	258	1
Bin	False	687	1

"if" / "when" / "else" condition:

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	667	1

"case" / "with" / "select" choice:

322: when s_txt_aborted =>

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	536	1

"if" / "when" / "else" condition:

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	124	1
Bin	False	412	1

"if" / "when" / "else" condition:

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	408	1

"case" / "with" / "select" choice:

336: when s_txt_ok =>

	Choice of	Count	Threshold
Bin	`s_txt_ok`	1193	1

"if" / "when" / "else" condition:

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	294	1
Bin	False	899	1

"if" / "when" / "else" condition:

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	13	1
Bin	False	886	1

"case" / "with" / "select" choice:

350: when s_txt_parity_err =>

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	450	1

"if" / "when" / "else" condition:

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	54	1
Bin	False	396	1

"if" / "when" / "else" condition:

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	51	1
Bin	False	345	1

"if" / "when" / "else" condition:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	True	3813	1
Bin	False	4469	1

"if" / "when" / "else" condition:

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	1737046	1
Bin	False	160587516	1

"if" / "when" / "else" condition:

378: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	80292006	1
Bin	False	80295510	1

"if" / "when" / "else" condition:

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	3044	1
Bin	False	80288962	1

"if" / "when" / "else" condition:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	True	2033	1
Bin	False	1967	1

"if" / "when" / "else" condition:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	True	2733	1
Bin	False	15733	1

"if" / "when" / "else" condition:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	15693	1

"if" / "when" / "else" condition:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	True	1083	1
Bin	False	3939	1

"case" / "with" / "select" choice:

417: TXT_RDY when s_txt_ready,

	Choice of	Count	Threshold
Bin	`s_txt_ready`	1083	1

"case" / "with" / "select" choice:

418: TXT_TRAN when s_txt_tx_prog,

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	885	1

"case" / "with" / "select" choice:

419: TXT_ABTP when s_txt_ab_prog,

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	65	1

"case" / "with" / "select" choice:

420: TXT_TOK when s_txt_ok,

	Choice of	Count	Threshold
Bin	`s_txt_ok`	396	1

"case" / "with" / "select" choice:

421: TXT_ERR when s_txt_failed,

	Choice of	Count	Threshold
Bin	`s_txt_failed`	295	1

"case" / "with" / "select" choice:

422: TXT_ABT when s_txt_aborted,

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	132	1

"case" / "with" / "select" choice:

423: TXT_ETY when s_txt_empty,

	Choice of	Count	Threshold
Bin	`s_txt_empty`	1040	1

"case" / "with" / "select" choice:

424: TXT_PER when s_txt_parity_err;

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	104	1

"if" / "when" / "else" condition:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	927	1
Bin	False	2247	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	81158777	1
Bin	1	0	81159437	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	2844	1
Bin	1	0	2844	1

Port:

MR_MODE_BMM

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	672	1

Port:

MR_MODE_ROM

	From	To	Count	Threshold
Bin	0	1	32	1
Bin	1	0	692	1

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold
Bin	0	1	784	1
Bin	1	0	124	1

Port:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	756	1

Port:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	1143	1
Bin	1	0	1803	1

Port:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	841	1

Port:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	841	1

Port:

TXTB_HW_CMD.LOCK

	From	To	Count	Threshold
Bin	0	1	9751	1
Bin	1	0	10411	1

Port:

TXTB_HW_CMD.VALID

	From	To	Count	Threshold
Bin	0	1	3808	1
Bin	1	0	4468	1

Port:

TXTB_HW_CMD.ERR

	From	To	Count	Threshold
Bin	0	1	1091	1
Bin	1	0	1751	1

Port:

TXTB_HW_CMD.ARBL

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	704	1

Port:

TXTB_HW_CMD.FAILED

	From	To	Count	Threshold
Bin	0	1	4800	1
Bin	1	0	5460	1

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold
Bin	0	1	308	1
Bin	1	0	968	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	2960	1
Bin	1	0	2960	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	396	1
Bin	1	0	1056	1

Port:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	1587	1
Bin	1	0	927	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	927	1
Bin	1	0	1587	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	745	1
Bin	1	0	1405	1

Port:

TXTB_STATE(3)

	From	To	Count	Threshold
Bin	0	1	1086	1
Bin	1	0	426	1

Port:

TXTB_STATE(2)

	From	To	Count	Threshold
Bin	0	1	823	1
Bin	1	0	1483	1

Port:

TXTB_STATE(1)

	From	To	Count	Threshold
Bin	0	1	1022	1
Bin	1	0	1682	1

Port:

TXTB_STATE(0)

	From	To	Count	Threshold
Bin	0	1	1017	1
Bin	1	0	1677	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	1083	1
Bin	1	0	1743	1

Port:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	927	1
Bin	1	0	1587	1

Signal:

TXT_FSM_CE

	From	To	Count	Threshold
Bin	0	1	3809	1
Bin	1	0	4469	1

Signal:

GO_TO_FAILED

	From	To	Count	Threshold
Bin	0	1	2944	1
Bin	1	0	2944	1

Signal:

TRANSIENT_STATE

	From	To	Count	Threshold
Bin	0	1	927	1
Bin	1	0	1587	1

Port:

TXTB_HW_CMD_I.LOCK

	From	To	Count	Threshold
Bin	0	1	889	1
Bin	1	0	1549	1

Port:

TXTB_HW_CMD_I.VALID

	From	To	Count	Threshold
Bin	0	1	396	1
Bin	1	0	1056	1

Port:

TXTB_HW_CMD_I.ERR

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	839	1

Port:

TXTB_HW_CMD_I.ARBL

	From	To	Count	Threshold
Bin	0	1	4	1
Bin	1	0	664	1

Port:

TXTB_HW_CMD_I.FAILED

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	970	1

Signal:

ARBL_OR_ERR

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	843	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or

	Evaluated to	Count	Threshold
Bin	False	3935	1
Bin	True	65	1

"=" expression

176: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	3115	1
Bin	True	885	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	3050	1
Bin	False	True	885	1
Bin	True	False	65	1

"=" expression

177: (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	False	2917	1
Bin	True	1083	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	LHS	RHS	Count	Threshold
Bin	False	False	1967	1
Bin	False	True	1083	1
Bin	True	False	950	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	3772	1
Bin	True	3792	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	2268	1
Bin	True	5296	1

"and" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
                                   <-----LHS------>     <----------------------RHS---------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	2316	1
Bin	True	False	812	1
Bin	True	True	2980	1

"=" expression

182: mr_mode_bmm = BMM_ENABLED or

	Evaluated to	Count	Threshold
Bin	False	7524	1
Bin	True	40	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or

	LHS	RHS	Count	Threshold
Bin	False	False	4552	1
Bin	False	True	32	1
Bin	True	False	2972	1

"=" expression

183: mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	False	7504	1
Bin	True	60	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	LHS	RHS	Count	Threshold
Bin	False	False	4520	1
Bin	False	True	32	1
Bin	True	False	2984	1

"=" expression

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	False	37720	1
Bin	True	3864	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	1507	1
Bin	True	179	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	1682	1
Bin	True	4	1

"or" expression

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
                                 <---------LHS--------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	1503	1
Bin	False	True	4	1
Bin	True	False	179	1

"=" expression

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	7685	1
Bin	True	413	1

"=" expression

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	3828	1
Bin	True	32	1

"=" expression

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	3588	1
Bin	True	240	1

"=" expression

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	2699	1
Bin	True	889	1

"=" expression

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	885	1
Bin	True	4	1

"=" expression

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	False	2586	1
Bin	True	113	1

"=" expression

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	3014	1
Bin	True	8	1

"=" expression

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	2916	1
Bin	True	98	1

"=" expression

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	2671	1
Bin	True	245	1

"=" expression

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	2287	1
Bin	True	384	1

"=" expression

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	2127	1
Bin	True	160	1

"=" expression

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	156	1
Bin	True	4	1

"=" expression

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	1997	1
Bin	True	130	1

"=" expression

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	281	1
Bin	True	4	1

"=" expression

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	266	1
Bin	True	15	1

"=" expression

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	244	1
Bin	True	22	1

"=" expression

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	232	1
Bin	True	12	1

"=" expression

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	213	1
Bin	True	19	1

"=" expression

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	687	1
Bin	True	258	1

"=" expression

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	667	1
Bin	True	20	1

"=" expression

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	412	1
Bin	True	124	1

"=" expression

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	408	1
Bin	True	4	1

"=" expression

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	899	1
Bin	True	294	1

"=" expression

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	886	1
Bin	True	13	1

"=" expression

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	396	1
Bin	True	54	1

"=" expression

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	345	1
Bin	True	51	1

"/=" expression

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	False	4469	1
Bin	True	3813	1

"=" expression

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	160587516	1
Bin	True	1737046	1

"=" expression

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	80288962	1
Bin	True	3044	1

"=" expression

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or

	Evaluated to	Count	Threshold
Bin	False	2917	1
Bin	True	1083	1

"=" expression

390: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	3115	1
Bin	True	885	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	2032	1
Bin	False	True	885	1
Bin	True	False	1083	1

"=" expression

391: (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	False	3935	1
Bin	True	65	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	LHS	RHS	Count	Threshold
Bin	False	False	1967	1
Bin	False	True	65	1
Bin	True	False	1968	1

"=" expression

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely

	Evaluated to	Count	Threshold
Bin	False	17355	1
Bin	True	1111	1

"=" expression

397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	Evaluated to	Count	Threshold
Bin	False	16882	1
Bin	True	1584	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	LHS	RHS	Count	Threshold
Bin	False	False	15771	1
Bin	False	True	1584	1
Bin	True	False	1111	1

"=" expression

398: ((txtb_hw_cmd_i.arbl = '1' or

	Evaluated to	Count	Threshold
Bin	False	18450	1
Bin	True	16	1

"=" expression

399: txtb_hw_cmd_i.err = '1') and

	Evaluated to	Count	Threshold
Bin	False	17906	1
Bin	True	560	1

"or" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and

	LHS	RHS	Count	Threshold
Bin	False	False	17890	1
Bin	False	True	560	1
Bin	True	False	16	1

"=" expression

400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	False	18277	1
Bin	True	189	1

"and" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	True	151	1
Bin	True	False	538	1
Bin	True	True	38	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	False	15733	1
Bin	False	True	38	1
Bin	True	False	2695	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	12641	1
Bin	True	3092	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	15195	1
Bin	True	538	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
                                     <-----LHS------>     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	442	1
Bin	True	False	2996	1
Bin	True	True	96	1

"=" expression

405: transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	11255	1
Bin	True	4478	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	4438	1
Bin	True	False	56	1
Bin	True	True	40	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	3826	1
Bin	True	1196	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	1019	1
Bin	True	4003	1

"and" expression

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
                                       <---------LHS---------->       <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	2920	1
Bin	True	False	113	1
Bin	True	True	1083	1

"=" expression

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	2247	1
Bin	True	927	1

	State	Count	Threshold
Bin	S_TXT_EMPTY	1077	1
Bin	S_TXT_READY	1478	1
Bin	S_TXT_TX_PROG	952	1
Bin	S_TXT_AB_PROG	72	1
Bin	S_TXT_OK	486	1
Bin	S_TXT_FAILED	376	1
Bin	S_TXT_ABORTED	140	1
Bin	S_TXT_PARITY_ERR	361	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd

Sub-instances:

Current Instance:

Details:

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Uncovered statements:

Excluded statements:

Covered statements:

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