NVC code coverage report

Signal assignment statement on line 183:

183:    req_input(1) <= exit_segm_req_nbt; 
Count: 32944386
Threshold: 1

---

Signal assignment statement on line 184:

184:    req_input(2) <= exit_segm_req_dbt; 
Count: 19959706
Threshold: 1

---

Signal assignment statement on line 191:

191:    segm_end_req_capt_clr(1) <= segment_end_i; 
Count: 45561038
Threshold: 1

---

Signal assignment statement on line 192:

192:    segm_end_req_capt_clr(2) <= segment_end_i; 
Count: 45561038
Threshold: 1

---

If statement on lines 229 to 231:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 
230:                                            else 
231:                               req_input(1) or segm_end_req_capt_q(1); 
Count: 63928511
Threshold: 1

---

Signal assignment statement on line 229:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 
Count: 28652717
Threshold: 1

---

Signal assignment statement on line 231:

231:                               req_input(1) or segm_end_req_capt_q(1); 
Count: 35275794
Threshold: 1

---

If statement on lines 233 to 235:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 
234:                                            else 
235:                               req_input(2) or segm_end_req_capt_q(2); 
Count: 49356763
Threshold: 1

---

Signal assignment statement on line 233:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 
Count: 24686642
Threshold: 1

---

Signal assignment statement on line 235:

235:                               req_input(2) or segm_end_req_capt_q(2); 
Count: 24670121
Threshold: 1

---

If statement on lines 240 to 242:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 
241:                         else 
242:                     '0'; 
Count: 197915782
Threshold: 1

---

Signal assignment statement on line 240:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 
Count: 76991774
Threshold: 1

---

Signal assignment statement on line 242:

242:                     '0'; 
Count: 120924008
Threshold: 1

---

If statement on lines 244 to 247:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE)) 
246:                         else 
247:                     '0'; 
Count: 69259137
Threshold: 1

---

Signal assignment statement on line 244:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
Count: 33711157
Threshold: 1

---

Signal assignment statement on line 247:

247:                     '0'; 
Count: 35547980
Threshold: 1

---

If statement on lines 253 to 256:

253:    segm_end_nbt_valid <= 
254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 
255:            else 
256:        '0'; 
Count: 186927218
Threshold: 1

---

Signal assignment statement on line 254:

254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 
Count: 13036538
Threshold: 1

---

Signal assignment statement on line 256:

256:        '0'; 
Count: 173890680
Threshold: 1

---

If statement on lines 258 to 261:

258:    segm_end_dbt_valid <= 
259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 
260:            else 
261:        '0'; 
Count: 87376751
Threshold: 1

---

Signal assignment statement on line 259:

259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 
Count: 9733462
Threshold: 1

---

Signal assignment statement on line 261:

261:        '0'; 
Count: 77643289
Threshold: 1

---

If statement on lines 263 to 266:

263:    segm_end_nbt_dbt_valid <= 
264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 
265:            else 
266:        '0'; 
Count: 45543202
Threshold: 1

---

Signal assignment statement on line 264:

264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 
Count: 22770000
Threshold: 1

---

Signal assignment statement on line 266:

266:        '0'; 
Count: 22773202
Threshold: 1

---

If statement on lines 271 to 273:

271:    tseg1_end_req_valid <= 
272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 
273:        '0'; 
Count: 68318643
Threshold: 1

---

Signal assignment statement on line 272:

272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 
Count: 22769580
Threshold: 1

---

Signal assignment statement on line 273:

273:        '0'; 
Count: 45549063
Threshold: 1

---

If statement on lines 275 to 278:

275:    tseg2_end_req_valid <= 
276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 
277:            else 
278:        '0'; 
Count: 68307645
Threshold: 1

---

Signal assignment statement on line 276:

276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 
Count: 22757006
Threshold: 1

---

Signal assignment statement on line 278:

278:        '0'; 
Count: 45550639
Threshold: 1

---

If statement on lines 284 to 286:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 
285:                          else 
286:                      '0'; 
Count: 154099921
Threshold: 1

---

Signal assignment statement on line 284:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 
Count: 56587
Threshold: 1

---

Signal assignment statement on line 286:

286:                      '0'; 
Count: 154043334
Threshold: 1

---

If statement on lines 297 to 301:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1')) 
300:                         else 
301:                     '0'; 
Count: 91175819
Threshold: 1

---

Signal assignment statement on line 297:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
Count: 68296088
Threshold: 1

---

Signal assignment statement on line 301:

301:                     '0'; 
Count: 22879731
Threshold: 1

---

If statement on lines 309 to 311:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 
310:                          else 
311:                      '0'; 
Count: 45663633
Threshold: 1

---

Signal assignment statement on line 309:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 
Count: 22847431
Threshold: 1

---

Signal assignment statement on line 311:

311:                      '0'; 
Count: 22816202
Threshold: 1

---

Signal assignment statement on line 313:

313:    bt_ctr_clear    <= bt_ctr_clear_i; 
Count: 45629202
Threshold: 1

---

Signal assignment statement on line 314:

314:    segm_end        <= segment_end_i; 
Count: 45561038
Threshold: 1

---

Signal assignment statement on line 315:

315:    h_sync_valid    <= h_sync_valid_i; 
Count: 116376
Threshold: 1

"if" / "when" / "else" condition on line 229:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 

	Evaluated to	Count	Threshold
Bin	True	28652717	1
Bin	False	35275794	1

---

"if" / "when" / "else" condition on line 233:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 

	Evaluated to	Count	Threshold
Bin	True	24686642	1
Bin	False	24670121	1

---

"if" / "when" / "else" condition on line 240:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 

	Evaluated to	Count	Threshold
Bin	True	76991774	1
Bin	False	120924008	1

---

"if" / "when" / "else" condition on lines 244 to 245:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE)) 

	Evaluated to	Count	Threshold
Bin	True	33711157	1
Bin	False	35547980	1

---

"if" / "when" / "else" condition on line 254:

254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 

	Evaluated to	Count	Threshold
Bin	True	13036538	1
Bin	False	173890680	1

---

"if" / "when" / "else" condition on line 259:

259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 

	Evaluated to	Count	Threshold
Bin	True	9733462	1
Bin	False	77643289	1

---

"if" / "when" / "else" condition on line 264:

264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 

	Evaluated to	Count	Threshold
Bin	True	22770000	1
Bin	False	22773202	1

---

"if" / "when" / "else" condition on line 272:

272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 

	Evaluated to	Count	Threshold
Bin	True	22769580	1
Bin	False	45549063	1

---

"if" / "when" / "else" condition on line 276:

276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 

	Evaluated to	Count	Threshold
Bin	True	22757006	1
Bin	False	45550639	1

---

"if" / "when" / "else" condition on line 284:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 

	Evaluated to	Count	Threshold
Bin	True	56587	1
Bin	False	154043334	1

---

"if" / "when" / "else" condition on lines 297 to 299:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1')) 

	Evaluated to	Count	Threshold
Bin	True	68296088	1
Bin	False	22879731	1

---

"if" / "when" / "else" condition on line 309:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 

	Evaluated to	Count	Threshold
Bin	True	22847431	1
Bin	False	22816202	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SP_CONTROL

	Element	From	To	Count	Threshold	Excluded due to
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 H_SYNC_EDGE_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 EXIT_SEGM_REQ_NBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 EXIT_SEGM_REQ_DBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TQ_EDGE_NBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TQ_EDGE_DBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

 SEGM_END

	From	To	Count	Threshold
Bin	0	1	22778918	1
Bin	1	0	22780519	1

---

Port:

 H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	56587	1
Bin	1	0	58188	1

---

Port:

 BT_CTR_CLEAR

	From	To	Count	Threshold
Bin	0	1	22813000	1
Bin	1	0	22814601	1

---

Signal:

 REQ_INPUT

	Element	From	To	Count	Threshold
Bin	(2)	0	1	13634388	1
Bin	(2)	1	0	35647371	1
Bin	(1)	0	1	16549949	1
Bin	(1)	1	0	32731810	1

---

Signal:

 SEGM_END_REQ_CAPT_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	10197094	1
Bin	(2)	1	0	35659581	1
Bin	(1)	0	1	13176881	1
Bin	(1)	1	0	32679794	1

---

Signal:

 SEGM_END_REQ_CAPT_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	3399477	1
Bin	(2)	1	0	11283568	1
Bin	(1)	0	1	4147443	1
Bin	(1)	1	0	10535602	1

---

Signal:

 SEGM_END_REQ_CAPT_CE

	Element	From	To	Count	Threshold
Bin	(2)	0	1	32668600	1
Bin	(2)	1	0	35658436	1
Bin	(1)	0	1	35648387	1
Bin	(1)	1	0	32678649	1

---

Signal:

 SEGM_END_REQ_CAPT_CLR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	22778918	1
Bin	(2)	1	0	22780519	1
Bin	(1)	0	1	22778918	1
Bin	(1)	1	0	22780519	1

---

Signal:

 SEGM_END_REQ_CAPT_DQ

	Element	From	To	Count	Threshold
Bin	(2)	0	1	13634120	1
Bin	(2)	1	0	35643347	1
Bin	(1)	0	1	16549507	1
Bin	(1)	1	0	32727960	1

---

Signal:

 SEGM_END_NBT_VALID

	From	To	Count	Threshold
Bin	0	1	13036538	1
Bin	1	0	13038139	1

---

Signal:

 SEGM_END_DBT_VALID

	From	To	Count	Threshold
Bin	0	1	9733462	1
Bin	1	0	9735063	1

---

Signal:

 SEGM_END_NBT_DBT_VALID

	From	To	Count	Threshold
Bin	0	1	22770000	1
Bin	1	0	22771601	1

---

Signal:

 TSEG1_END_REQ_VALID

	From	To	Count	Threshold
Bin	0	1	22769580	1
Bin	1	0	22771181	1

---

Signal:

 TSEG2_END_REQ_VALID

	From	To	Count	Threshold
Bin	0	1	22757006	1
Bin	1	0	22758607	1

---

Signal:

 H_SYNC_VALID_I

	From	To	Count	Threshold
Bin	0	1	56587	1
Bin	1	0	58188	1

---

Signal:

 SEGMENT_END_I

	From	To	Count	Threshold
Bin	0	1	22778918	1
Bin	1	0	22780519	1

---

Signal:

 NBT_TQ_ACTIVE

	From	To	Count	Threshold
Bin	0	1	76991774	1
Bin	1	0	76993372	1

---

Signal:

 DBT_TQ_ACTIVE

	From	To	Count	Threshold
Bin	0	1	33709981	1
Bin	1	0	33711582	1

---

Signal:

 BT_CTR_CLEAR_I

	From	To	Count	Threshold
Bin	0	1	22813000	1
Bin	1	0	22814601	1

"and" expression on lines 244 to 245:

 tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
 <------LHS------>      <--------------------------RHS-------------------------->  

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

---

"or" expression on lines 244 to 245:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------> 

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"=" expression on line 229:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	35275794	1
Bin	True	28652717	1

---

"or" expression on line 231:

 req_input(1) or segm_end_req_capt_q(1) 
 <---LHS---->    <--------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	14733196	1
Bin	'0'	'1'	1155	1
Bin	'1'	'0'	18492903	1

---

"=" expression on line 233:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	24670121	1
Bin	True	24686642	1

---

"or" expression on line 235:

 req_input(2) or segm_end_req_capt_q(2) 
 <---LHS---->    <--------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	11389345	1
Bin	'0'	'1'	1718	1
Bin	'1'	'0'	11619352	1

---

"and" expression on line 240:

 sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1' 
 <-----------LHS----------->     <------RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	True	21965186	1
Bin	True	False	76991989	1
Bin	True	True	76991774	1

---

"=" expression on line 240:

 tq_edge_nbt = '1' 

	Evaluated to	Count	Threshold
Bin	False	98958822	1
Bin	True	98956960	1

---

"and" expression on lines 244 to 245:

 tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
 <------LHS------>      <--------------------------RHS-------------------------->  

	LHS	RHS	Count	Threshold
Bin	True	False	933655	1
Bin	True	True	33711157	1

---

"=" expression on line 244:

 tq_edge_dbt = '1' 

	Evaluated to	Count	Threshold
Bin	False	34614325	1
Bin	True	34644812	1

---

"or" expression on lines 244 to 245:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	933655	1
Bin	False	True	896108	1

---

"and" expression on line 254:

 segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1' 
 <------------LHS------------>     <-------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	True	81982842	1
Bin	True	False	11478368	1
Bin	True	True	13036538	1

---

"=" expression on line 254:

 segm_end_req_capt_dq(1) = '1' 

	Evaluated to	Count	Threshold
Bin	False	162412312	1
Bin	True	24514906	1

---

"=" expression on line 254:

 nbt_tq_active = '1' 

	Evaluated to	Count	Threshold
Bin	False	91907838	1
Bin	True	95019380	1

---

"and" expression on line 259:

 segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1' 
 <------------LHS------------>     <-------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	True	37231733	1
Bin	True	False	6452977	1
Bin	True	True	9733462	1

---

"=" expression on line 259:

 segm_end_req_capt_dq(2) = '1' 

	Evaluated to	Count	Threshold
Bin	False	71190312	1
Bin	True	16186439	1

---

"=" expression on line 259:

 dbt_tq_active = '1' 

	Evaluated to	Count	Threshold
Bin	False	40411556	1
Bin	True	46965195	1

---

"or" expression on line 264:

 segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1' 
 <---------LHS---------->    <---------RHS----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	22773202	1
Bin	False	True	9733462	1
Bin	True	False	13036538	1

---

"=" expression on line 264:

 segm_end_nbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	32506664	1
Bin	True	13036538	1

---

"=" expression on line 264:

 segm_end_dbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	35809740	1
Bin	True	9733462	1

---

"and" expression on line 272:

 is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1' 
 <----LHS----->     <-----------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22757321	1
Bin	True	False	11401205	1
Bin	True	True	22769580	1

---

"=" expression on line 272:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34147858	1
Bin	True	34170785	1

---

"=" expression on line 272:

 segm_end_nbt_dbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	22791742	1
Bin	True	45526901	1

---

"and" expression on line 276:

 is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1' 
 <----LHS----->     <-----------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22770006	1
Bin	True	False	11382216	1
Bin	True	True	22757006	1

---

"=" expression on line 276:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34168423	1
Bin	True	34139222	1

---

"=" expression on line 276:

 segm_end_nbt_dbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	22780633	1
Bin	True	45527012	1

---

"and" expression on line 284:

 (h_sync_edge_valid = '1') and (nbt_tq_active = '1') 
  <---------LHS--------->       <-------RHS------->  

	LHS	RHS	Count	Threshold
Bin	False	True	77043364	1
Bin	True	False	4997	1
Bin	True	True	56587	1

---

"=" expression on line 284:

 h_sync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	154038337	1
Bin	True	61584	1

---

"=" expression on line 284:

 nbt_tq_active = '1' 

	Evaluated to	Count	Threshold
Bin	False	76999970	1
Bin	True	77099951	1

---

"or" expression on lines 297 to 299:

 (tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or tseg2_end_req_valid = '1' or (h_sync_valid_i = '1' and is_tseg2 = '1') 
 <--------------------------------------LHS-------------------------------------->     <-----------------RHS----------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	22879731	1
Bin	False	True	7774	1
Bin	True	False	68285746	1

---

"or" expression on lines 297 to 298:

 (tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or tseg2_end_req_valid = '1' 
  <----------------------LHS----------------------->     <----------RHS----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	22887505	1
Bin	False	True	34133672	1
Bin	True	False	34154642	1

---

"and" expression on line 297:

 tseg1_end_req_valid = '1' and h_sync_valid_i = '0' 
 <----------LHS---------->     <-------RHS--------> 

	LHS	RHS	Count	Threshold
Bin	False	True	56941993	1
Bin	True	False	14508	1
Bin	True	True	34154642	1

---

"=" expression on line 297:

 tseg1_end_req_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	57006669	1
Bin	True	34169150	1

---

"=" expression on line 297:

 h_sync_valid_i = '0' 

	Evaluated to	Count	Threshold
Bin	False	79184	1
Bin	True	91096635	1

---

"=" expression on line 298:

 tseg2_end_req_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	57042147	1
Bin	True	34133672	1

---

"and" expression on line 299:

 h_sync_valid_i = '1' and is_tseg2 = '1' 
 <-------LHS-------->     <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	45520773	1
Bin	True	False	67241	1
Bin	True	True	10342	1

---

"=" expression on line 299:

 h_sync_valid_i = '1' 

	Evaluated to	Count	Threshold
Bin	False	91098236	1
Bin	True	77583	1

---

"=" expression on line 299:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	45644704	1
Bin	True	45531115	1

---

"or" expression on line 309:

 segment_end_i = '1' or h_sync_valid_i = '1' 
 <-------LHS------->    <-------RHS--------> 

	LHS	RHS	Count	Threshold
Bin	False	False	22816202	1
Bin	False	True	52425	1
Bin	True	False	22773402	1

---

"=" expression on line 309:

 segment_end_i = '1' 

	Evaluated to	Count	Threshold
Bin	False	22868627	1
Bin	True	22795006	1

---

"=" expression on line 309:

 h_sync_valid_i = '1' 

	Evaluated to	Count	Threshold
Bin	False	45589604	1
Bin	True	74029	1