NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
SEGM_END_REQ_CAPTURE(1)	100.0 % (10/10)	100.0 % (10/10)	N.A.	100.0 % (13/13)	N.A.	N.A.	100.0 % (33/33)
SEGM_END_REQ_CAPTURE(2)	100.0 % (10/10)	100.0 % (10/10)	N.A.	100.0 % (13/13)	N.A.	N.A.	100.0 % (33/33)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST	100.0 % (36/36)	100.0 % (24/24)	100.0 % (72/72)	100.0 % (94/94)	N.A.	N.A.	100.0 % (226/226)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 
230:                                            else 
231:                               req_input(1) or segm_end_req_capt_q(1);

Count: 61522182
Threshold: 1

Signal assignment statement:

229: segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1')
Count: 27413651
Threshold: 1

Signal assignment statement:

231: req_input(1) or segm_end_req_capt_q(1);
Count: 34108531
Threshold: 1

If statement:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 
234:                                            else 
235:                               req_input(2) or segm_end_req_capt_q(2);

Count: 48814286
Threshold: 1

Signal assignment statement:

233: segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1')
Count: 24414985
Threshold: 1

Signal assignment statement:

235: req_input(2) or segm_end_req_capt_q(2);
Count: 24399301
Threshold: 1

If statement:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 
241:                         else 
242:                     '0';

Count: 193513093
Threshold: 1

Signal assignment statement:

240: nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1')
Count: 74691460
Threshold: 1

Signal assignment statement:

242: '0';
Count: 118821633
Threshold: 1

If statement:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE)) 
246:                         else 
247:                     '0';

Count: 70244549
Threshold: 1

Signal assignment statement:

244: dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or
Count: 34208297
Threshold: 1

Signal assignment statement:

247: '0';
Count: 36036252
Threshold: 1

If statement:

253:    segm_end_nbt_valid <= 
254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 
255:            else 
256:        '0';

Count: 180908542
Threshold: 1

Signal assignment statement:

254: '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1')
Count: 12287101
Threshold: 1

Signal assignment statement:

256: '0';
Count: 168621441
Threshold: 1

If statement:

258:    segm_end_dbt_valid <= 
259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 
260:            else 
261:        '0';

Count: 88475354
Threshold: 1

Signal assignment statement:

259: '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1')
Count: 9788771
Threshold: 1

Signal assignment statement:

261: '0';
Count: 78686583
Threshold: 1

If statement:

263:    segm_end_nbt_dbt_valid <= 
264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 
265:            else 
266:        '0';

Count: 44154944
Threshold: 1

Signal assignment statement:

264: '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1')
Count: 22075872
Threshold: 1

Signal assignment statement:

266: '0';
Count: 22079072
Threshold: 1

If statement:

271:    tseg1_end_req_valid <= 
272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 
273:        '0';

Count: 66236424
Threshold: 1

Signal assignment statement:

272: '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else
Count: 22075459
Threshold: 1

Signal assignment statement:

273: '0';
Count: 44160965
Threshold: 1

If statement:

275:    tseg2_end_req_valid <= 
276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 
277:            else 
278:        '0';

Count: 66225381
Threshold: 1

Signal assignment statement:

276: '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1')
Count: 22063194
Threshold: 1

Signal assignment statement:

278: '0';
Count: 44162187
Threshold: 1

If statement:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 
285:                          else 
286:                      '0';

Count: 149496853
Threshold: 1

Signal assignment statement:

284: h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1'))
Count: 55365
Threshold: 1

Signal assignment statement:

286: '0';
Count: 149441488
Threshold: 1

If statement:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1')) 
300:                         else 
301:                     '0';

Count: 88397278
Threshold: 1

Signal assignment statement:

297: segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or
Count: 66214196
Threshold: 1

Signal assignment statement:

301: '0';
Count: 22183082
Threshold: 1

If statement:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 
310:                          else 
311:                      '0';

Count: 44272445
Threshold: 1

Signal assignment statement:

309: bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1')
Count: 22151125
Threshold: 1

Signal assignment statement:

311: '0';
Count: 22121320
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

229: segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1')

	Evaluated to	Count	Threshold
Bin	True	27413651	1
Bin	False	34108531	1

"if" / "when" / "else" condition:

233: segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1')

	Evaluated to	Count	Threshold
Bin	True	24414985	1
Bin	False	24399301	1

"if" / "when" / "else" condition:

240: nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1')

	Evaluated to	Count	Threshold
Bin	True	74691460	1
Bin	False	118821633	1

"if" / "when" / "else" condition:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	34208297	1
Bin	False	36036252	1

"if" / "when" / "else" condition:

254: '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1')

	Evaluated to	Count	Threshold
Bin	True	12287101	1
Bin	False	168621441	1

"if" / "when" / "else" condition:

259: '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1')

	Evaluated to	Count	Threshold
Bin	True	9788771	1
Bin	False	78686583	1

"if" / "when" / "else" condition:

264: '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	22075872	1
Bin	False	22079072	1

"if" / "when" / "else" condition:

272: '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	22075459	1
Bin	False	44160965	1

"if" / "when" / "else" condition:

276: '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	22063194	1
Bin	False	44162187	1

"if" / "when" / "else" condition:

284: h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1'))

	Evaluated to	Count	Threshold
Bin	True	55365	1
Bin	False	149441488	1

"if" / "when" / "else" condition:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1'))

	Evaluated to	Count	Threshold
Bin	True	66214196	1
Bin	False	22183082	1

"if" / "when" / "else" condition:

309: bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1')

	Evaluated to	Count	Threshold
Bin	True	22151125	1
Bin	False	22121320	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SP_CONTROL(1)

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

SP_CONTROL(0)

	From	To	Count	Threshold
Bin	0	1	25548	1
Bin	1	0	27148	1

Port:

H_SYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	55371	1
Bin	1	0	56971	1

Port:

EXIT_SEGM_REQ_NBT

	From	To	Count	Threshold
Bin	0	1	15761570	1
Bin	1	0	15763169	1

Port:

EXIT_SEGM_REQ_DBT

	From	To	Count	Threshold
Bin	0	1	10030898	1
Bin	1	0	10032498	1

Port:

IS_TSEG1

	From	To	Count	Threshold
Bin	0	1	11041544	1
Bin	1	0	11041536	1

Port:

IS_TSEG2

	From	To	Count	Threshold
Bin	0	1	11035219	1
Bin	1	0	11036818	1

Port:

TQ_EDGE_NBT

	From	To	Count	Threshold
Bin	0	1	96725568	1
Bin	1	0	96727165	1

Port:

TQ_EDGE_DBT

	From	To	Count	Threshold
Bin	0	1	35091299	1
Bin	1	0	35092890	1

Port:

SEGM_END

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Port:

H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	55365	1
Bin	1	0	56965	1

Port:

BT_CTR_CLEAR

	From	To	Count	Threshold
Bin	0	1	22118120	1
Bin	1	0	22119720	1

Signal:

REQ_INPUT(2)

	From	To	Count	Threshold
Bin	0	1	13722636	1
Bin	1	0	34211460	1

Signal:

REQ_INPUT(1)

	From	To	Count	Threshold
Bin	0	1	15845683	1
Bin	1	0	32088413	1

Signal:

SEGM_END_REQ_CAPT_D(2)

	From	To	Count	Threshold
Bin	0	1	10248566	1
Bin	1	0	34223348	1

Signal:

SEGM_END_REQ_CAPT_D(1)

	From	To	Count	Threshold
Bin	0	1	12437098	1
Bin	1	0	32034816	1

Signal:

SEGM_END_REQ_CAPT_Q(2)

	From	To	Count	Threshold
Bin	0	1	3423634	1
Bin	1	0	11006398	1

Signal:

SEGM_END_REQ_CAPT_Q(1)

	From	To	Count	Threshold
Bin	0	1	4004312	1
Bin	1	0	10425720	1

Signal:

SEGM_END_REQ_CAPT_CE(2)

	From	To	Count	Threshold
Bin	0	1	32022909	1
Bin	1	0	34221793	1

Signal:

SEGM_END_REQ_CAPT_CE(1)

	From	To	Count	Threshold
Bin	0	1	34211441	1
Bin	1	0	32033261	1

Signal:

SEGM_END_REQ_CAPT_CLR(2)

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Signal:

SEGM_END_REQ_CAPT_CLR(1)

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Signal:

SEGM_END_REQ_CAPT_DQ(2)

	From	To	Count	Threshold
Bin	0	1	13722373	1
Bin	1	0	34207453	1

Signal:

SEGM_END_REQ_CAPT_DQ(1)

	From	To	Count	Threshold
Bin	0	1	15845237	1
Bin	1	0	32084589	1

Signal:

SEGM_END_NBT_VALID

	From	To	Count	Threshold
Bin	0	1	12287101	1
Bin	1	0	12288701	1

Signal:

SEGM_END_DBT_VALID

	From	To	Count	Threshold
Bin	0	1	9788771	1
Bin	1	0	9790371	1

Signal:

SEGM_END_NBT_DBT_VALID

	From	To	Count	Threshold
Bin	0	1	22075872	1
Bin	1	0	22077472	1

Signal:

TSEG1_END_REQ_VALID

	From	To	Count	Threshold
Bin	0	1	22075459	1
Bin	1	0	22077059	1

Signal:

TSEG2_END_REQ_VALID

	From	To	Count	Threshold
Bin	0	1	22063194	1
Bin	1	0	22064794	1

Signal:

H_SYNC_VALID_I

	From	To	Count	Threshold
Bin	0	1	55365	1
Bin	1	0	56965	1

Signal:

SEGMENT_END_I

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Signal:

NBT_TQ_ACTIVE

	From	To	Count	Threshold
Bin	0	1	74691460	1
Bin	1	0	74693057	1

Signal:

DBT_TQ_ACTIVE

	From	To	Count	Threshold
Bin	0	1	34206771	1
Bin	1	0	34208371	1

Signal:

BT_CTR_CLEAR_I

	From	To	Count	Threshold
Bin	0	1	22118120	1
Bin	1	0	22119720	1

Uncovered expressions:

Excluded expressions:

"or" expression

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

229: segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1')

	Evaluated to	Count	Threshold
Bin	False	34108531	1
Bin	True	27413651	1

"or" expression

231:                               req_input(1) or segm_end_req_capt_q(1); 
                                   <---LHS---->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	14421164	1
Bin	'0'	'1'	1155	1
Bin	'1'	'0'	17710845	1

"=" expression

233: segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1')

	Evaluated to	Count	Threshold
Bin	False	24399301	1
Bin	True	24414985	1

"or" expression

235:                               req_input(2) or segm_end_req_capt_q(2); 
                                   <---LHS---->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	11042518	1
Bin	'0'	'1'	1700	1
Bin	'1'	'0'	11683787	1

"=" expression

240: nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1')

	Evaluated to	Count	Threshold
Bin	False	96757442	1
Bin	True	96755651	1

"and" expression

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 
                                   <-----------LHS----------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	22064191	1
Bin	True	False	74691836	1
Bin	True	True	74691460	1

"=" expression

244: dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or

	Evaluated to	Count	Threshold
Bin	False	35106710	1
Bin	True	35137839	1

"or" expression

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold
Bin	False	False	929542	1
Bin	False	True	1084069	1

"and" expression

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold
Bin	True	False	929542	1
Bin	True	True	34208297	1

"=" expression

254: '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1')

	Evaluated to	Count	Threshold
Bin	False	157407597	1
Bin	True	23500945	1

"=" expression

254: '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1')

	Evaluated to	Count	Threshold
Bin	False	89383411	1
Bin	True	91525131	1

"and" expression

254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 
                      <------------LHS------------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	79238030	1
Bin	True	False	11213844	1
Bin	True	True	12287101	1

"=" expression

259: '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1')

	Evaluated to	Count	Threshold
Bin	False	72186114	1
Bin	True	16289240	1

"=" expression

259: '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1')

	Evaluated to	Count	Threshold
Bin	False	40953183	1
Bin	True	47522171	1

"and" expression

259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 
                      <------------LHS------------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	37733400	1
Bin	True	False	6500469	1
Bin	True	True	9788771	1

"=" expression

264: '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	31867843	1
Bin	True	12287101	1

"=" expression

264: '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	34366173	1
Bin	True	9788771	1

"or" expression

264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 
                      <---------LHS---------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	22079072	1
Bin	False	True	9788771	1
Bin	True	False	12287101	1

"=" expression

272: '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else

	Evaluated to	Count	Threshold
Bin	False	33107052	1
Bin	True	33129372	1

"=" expression

272: '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else

	Evaluated to	Count	Threshold
Bin	False	22097462	1
Bin	True	44138962	1

"and" expression

272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 
                      <----LHS----->     <-----------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	22063503	1
Bin	True	False	11053913	1
Bin	True	True	22075459	1

"=" expression

276: '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	33126974	1
Bin	True	33098407	1

"=" expression

276: '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	22086309	1
Bin	True	44139072	1

"and" expression

276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 
                      <----LHS----->     <-----------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	22075878	1
Bin	True	False	11035213	1
Bin	True	True	22063194	1

"=" expression

284: h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1'))

	Evaluated to	Count	Threshold
Bin	False	149436595	1
Bin	True	60258	1

"=" expression

284: h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1'))

	Evaluated to	Count	Threshold
Bin	False	74699550	1
Bin	True	74797303	1

"and" expression

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 
                                     <---------LHS--------->       <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	74741938	1
Bin	True	False	4893	1
Bin	True	True	55365	1

"=" expression

297: segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or

	Evaluated to	Count	Threshold
Bin	False	55270070	1
Bin	True	33127208	1

"=" expression

297: segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or

	Evaluated to	Count	Threshold
Bin	False	77142	1
Bin	True	88320136	1

"and" expression

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
                                    <----------LHS---------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	55206682	1
Bin	True	False	13754	1
Bin	True	True	33113454	1

"=" expression

298: tseg2_end_req_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	55304010	1
Bin	True	33093268	1

"or" expression

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	22190556	1
Bin	False	True	33093268	1
Bin	True	False	33113454	1

"=" expression

299: (h_sync_valid_i = '1' and is_tseg2 = '1'))

	Evaluated to	Count	Threshold
Bin	False	88321736	1
Bin	True	75542	1

"=" expression

299: (h_sync_valid_i = '1' and is_tseg2 = '1'))

	Evaluated to	Count	Threshold
Bin	False	44254205	1
Bin	True	44143073	1

"and" expression

299:                               (h_sync_valid_i = '1' and is_tseg2 = '1')) 
                                    <-------LHS-------->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	44132899	1
Bin	True	False	65368	1
Bin	True	True	10174	1

"or" expression

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1'))

	LHS	RHS	Count	Threshold
Bin	False	False	22183082	1
Bin	False	True	7474	1
Bin	True	False	66204022	1

"=" expression

309: bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1')

	Evaluated to	Count	Threshold
Bin	False	22172491	1
Bin	True	22099954	1

"=" expression

309: bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1')

	Evaluated to	Count	Threshold
Bin	False	44200426	1
Bin	True	72019	1

"or" expression

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 
                                    <-------LHS------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	22121320	1
Bin	False	True	51171	1
Bin	True	False	22079106	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd

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