NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST_COMB	100.0 % (19/19)	100.0 % (20/20)	100.0 % (46/46)	100.0 % (6/6)	N.A.	N.A.	100.0 % (91/91)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

114: dlc_int <= to_integer(unsigned(dlc));
Count: 4978111
Threshold: 1

If statement:

117:    data_len_8_to_64_integer <= 
118:        12 when (dlc = "1001") else 
...
124:        64 when (dlc = "1111") else 
125:        0;

Count: 4978111
Threshold: 1

Signal assignment statement:

118: 12 when (dlc = "1001") else
Count: 173460
Threshold: 1

Signal assignment statement:

119: 16 when (dlc = "1010") else
Count: 260438
Threshold: 1

Signal assignment statement:

120: 20 when (dlc = "1011") else
Count: 355673
Threshold: 1

Signal assignment statement:

121: 24 when (dlc = "1100") else
Count: 357832
Threshold: 1

Signal assignment statement:

122: 32 when (dlc = "1101") else
Count: 157158
Threshold: 1

Signal assignment statement:

123: 48 when (dlc = "1110") else
Count: 331886
Threshold: 1

Signal assignment statement:

124: 64 when (dlc = "1111") else
Count: 335877
Threshold: 1

Signal assignment statement:

125: 0;
Count: 3005787
Threshold: 1

If statement:

130:    data_len_can_2_0 <= dlc when (dlc_int <= 8) 
131:                            else 
132:                        "1000";

Count: 9953022
Threshold: 1

Signal assignment statement:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)
Count: 6008380
Threshold: 1

Signal assignment statement:

132: "1000";
Count: 3944642
Threshold: 1

If statement:

137:    data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8) 
138:                                     else 
139:                       std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));

Count: 9953022
Threshold: 1

Signal assignment statement:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)
Count: 6008380
Threshold: 1

Signal assignment statement:

139: std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));
Count: 3944642
Threshold: 1

If statement:

142:    data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN) 
143:                                            else 
144:                   data_len_can_fd;

Count: 5674270
Threshold: 1

Signal assignment statement:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)
Count: 2339743
Threshold: 1

Signal assignment statement:

144: data_len_can_fd;
Count: 3334527
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

118: 12 when (dlc = "1001") else

	Evaluated to	Count	Threshold
Bin	True	173460	1
Bin	False	4804651	1

"if" / "when" / "else" condition:

119: 16 when (dlc = "1010") else

	Evaluated to	Count	Threshold
Bin	True	260438	1
Bin	False	4544213	1

"if" / "when" / "else" condition:

120: 20 when (dlc = "1011") else

	Evaluated to	Count	Threshold
Bin	True	355673	1
Bin	False	4188540	1

"if" / "when" / "else" condition:

121: 24 when (dlc = "1100") else

	Evaluated to	Count	Threshold
Bin	True	357832	1
Bin	False	3830708	1

"if" / "when" / "else" condition:

122: 32 when (dlc = "1101") else

	Evaluated to	Count	Threshold
Bin	True	157158	1
Bin	False	3673550	1

"if" / "when" / "else" condition:

123: 48 when (dlc = "1110") else

	Evaluated to	Count	Threshold
Bin	True	331886	1
Bin	False	3341664	1

"if" / "when" / "else" condition:

124: 64 when (dlc = "1111") else

	Evaluated to	Count	Threshold
Bin	True	335877	1
Bin	False	3005787	1

"if" / "when" / "else" condition:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	6008380	1
Bin	False	3944642	1

"if" / "when" / "else" condition:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	6008380	1
Bin	False	3944642	1

"if" / "when" / "else" condition:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	True	2339743	1
Bin	False	3334527	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DLC(3)

	From	To	Count	Threshold
Bin	0	1	564607	1
Bin	1	0	566201	1

Port:

DLC(2)

	From	To	Count	Threshold
Bin	0	1	576164	1
Bin	1	0	577759	1

Port:

DLC(1)

	From	To	Count	Threshold
Bin	0	1	586427	1
Bin	1	0	588021	1

Port:

DLC(0)

	From	To	Count	Threshold
Bin	0	1	1391188	1
Bin	1	0	1389588	1

Port:

FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	28440	1
Bin	1	0	30036	1

Port:

DATA_LENGTH(6)

	From	To	Count	Threshold
Bin	0	1	250443	1
Bin	1	0	252042	1

Port:

DATA_LENGTH(5)

	From	To	Count	Threshold
Bin	0	1	349847	1
Bin	1	0	351446	1

Port:

DATA_LENGTH(4)

	From	To	Count	Threshold
Bin	0	1	450448	1
Bin	1	0	452048	1

Port:

DATA_LENGTH(3)

	From	To	Count	Threshold
Bin	0	1	775174	1
Bin	1	0	776770	1

Port:

DATA_LENGTH(2)

	From	To	Count	Threshold
Bin	0	1	818963	1
Bin	1	0	820562	1

Port:

DATA_LENGTH(1)

	From	To	Count	Threshold
Bin	0	1	598227	1
Bin	1	0	599826	1

Port:

DATA_LENGTH(0)

	From	To	Count	Threshold
Bin	0	1	1185789	1
Bin	1	0	1184195	1

Signal:

DATA_LEN_CAN_2_0(3)

	From	To	Count	Threshold
Bin	0	1	564607	1
Bin	1	0	566201	1

Signal:

DATA_LEN_CAN_2_0(2)

	From	To	Count	Threshold
Bin	0	1	576164	1
Bin	1	0	577763	1

Signal:

DATA_LEN_CAN_2_0(1)

	From	To	Count	Threshold
Bin	0	1	598227	1
Bin	1	0	599826	1

Signal:

DATA_LEN_CAN_2_0(0)

	From	To	Count	Threshold
Bin	0	1	1185789	1
Bin	1	0	1184195	1

Signal:

DATA_LEN_CAN_FD(6)

	From	To	Count	Threshold
Bin	0	1	335877	1
Bin	1	0	337474	1

Signal:

DATA_LEN_CAN_FD(5)

	From	To	Count	Threshold
Bin	0	1	489044	1
Bin	1	0	490643	1

Signal:

DATA_LEN_CAN_FD(4)

	From	To	Count	Threshold
Bin	0	1	750261	1
Bin	1	0	751859	1

Signal:

DATA_LEN_CAN_FD(3)

	From	To	Count	Threshold
Bin	0	1	829122	1
Bin	1	0	830722	1

Signal:

DATA_LEN_CAN_FD(2)

	From	To	Count	Threshold
Bin	0	1	1012522	1
Bin	1	0	1014119	1

Signal:

DATA_LEN_CAN_FD(1)

	From	To	Count	Threshold
Bin	0	1	598227	1
Bin	1	0	599826	1

Signal:

DATA_LEN_CAN_FD(0)

	From	To	Count	Threshold
Bin	0	1	1185789	1
Bin	1	0	1184195	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	False	3944642	1
Bin	True	6008380	1

"<=" expression

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	False	3944642	1
Bin	True	6008380	1

"=" expression

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	False	3334527	1
Bin	True	2339743	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST_COMB

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

"<=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: