NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST_COMB	100.0 % (19/19)	100.0 % (20/20)	100.0 % (46/46)	100.0 % (6/6)	N.A.	N.A.	100.0 % (91/91)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST_COMB

100.0 % (19/19)

100.0 % (20/20)

100.0 % (46/46)

100.0 % (6/6)

N.A.

100.0 % (91/91)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 114:

114: dlc_int <= to_integer(unsigned(dlc));
Count: 5004569
Threshold: 1

If statement on lines 117 to 125:

117:    data_len_8_to_64_integer <= 
118:        12 when (dlc = "1001") else 
...
124:        64 when (dlc = "1111") else 
125:        0;

Count: 5004569
Threshold: 1

Signal assignment statement on line 118:

118: 12 when (dlc = "1001") else
Count: 164274
Threshold: 1

Signal assignment statement on line 119:

119: 16 when (dlc = "1010") else
Count: 257740
Threshold: 1

Signal assignment statement on line 120:

120: 20 when (dlc = "1011") else
Count: 351370
Threshold: 1

Signal assignment statement on line 121:

121: 24 when (dlc = "1100") else
Count: 362827
Threshold: 1

Signal assignment statement on line 122:

122: 32 when (dlc = "1101") else
Count: 158237
Threshold: 1

Signal assignment statement on line 123:

123: 48 when (dlc = "1110") else
Count: 336001
Threshold: 1

Signal assignment statement on line 124:

124: 64 when (dlc = "1111") else
Count: 340442
Threshold: 1

Signal assignment statement on line 125:

125: 0;
Count: 3033678
Threshold: 1

If statement on lines 130 to 132:

130:    data_len_can_2_0 <= dlc when (dlc_int <= 8) 
131:                            else 
132:                        "1000";

Count: 10005936
Threshold: 1

Signal assignment statement on line 130:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)
Count: 6064162
Threshold: 1

Signal assignment statement on line 132:

132: "1000";
Count: 3941774
Threshold: 1

If statement on lines 137 to 139:

137:    data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8) 
138:                                     else 
139:                       std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));

Count: 10005936
Threshold: 1

Signal assignment statement on line 137:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)
Count: 6064162
Threshold: 1

Signal assignment statement on line 139:

139: std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));
Count: 3941774
Threshold: 1

If statement on lines 142 to 144:

142:    data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN) 
143:                                            else 
144:                   data_len_can_fd;

Count: 5693738
Threshold: 1

Signal assignment statement on line 142:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)
Count: 2387558
Threshold: 1

Signal assignment statement on line 144:

144: data_len_can_fd;
Count: 3306180
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 118:

118: 12 when (dlc = "1001") else

	Evaluated to	Count	Threshold
Bin	True	164274	1
Bin	False	4840295	1

"if" / "when" / "else" condition on line 119:

119: 16 when (dlc = "1010") else

	Evaluated to	Count	Threshold
Bin	True	257740	1
Bin	False	4582555	1

"if" / "when" / "else" condition on line 120:

120: 20 when (dlc = "1011") else

	Evaluated to	Count	Threshold
Bin	True	351370	1
Bin	False	4231185	1

"if" / "when" / "else" condition on line 121:

121: 24 when (dlc = "1100") else

	Evaluated to	Count	Threshold
Bin	True	362827	1
Bin	False	3868358	1

"if" / "when" / "else" condition on line 122:

122: 32 when (dlc = "1101") else

	Evaluated to	Count	Threshold
Bin	True	158237	1
Bin	False	3710121	1

"if" / "when" / "else" condition on line 123:

123: 48 when (dlc = "1110") else

	Evaluated to	Count	Threshold
Bin	True	336001	1
Bin	False	3374120	1

"if" / "when" / "else" condition on line 124:

124: 64 when (dlc = "1111") else

	Evaluated to	Count	Threshold
Bin	True	340442	1
Bin	False	3033678	1

"if" / "when" / "else" condition on line 130:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	6064162	1
Bin	False	3941774	1

"if" / "when" / "else" condition on line 137:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	6064162	1
Bin	False	3941774	1

"if" / "when" / "else" condition on line 142:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	True	2387558	1
Bin	False	3306180	1

Uncovered toggles:

Excluded toggles:

Port:

DLC

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

FRAME_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

DATA_LENGTH

	Element	From	To	Count	Threshold
Bin	(6)	0	1	246454	1
Bin	(6)	1	0	248053	1
Bin	(5)	0	1	346442	1
Bin	(5)	1	0	348043	1
Bin	(4)	0	1	446060	1
Bin	(4)	1	0	447661	1
Bin	(3)	0	1	776373	1
Bin	(3)	1	0	777968	1
Bin	(2)	0	1	818778	1
Bin	(2)	1	0	820376	1
Bin	(1)	0	1	598341	1
Bin	(1)	1	0	599940	1
Bin	(0)	0	1	1174827	1
Bin	(0)	1	0	1173234	1

Signal:

DATA_LEN_CAN_2_0

	Element	From	To	Count	Threshold
Bin	(3)	0	1	566357	1
Bin	(3)	1	0	567950	1
Bin	(2)	0	1	577627	1
Bin	(2)	1	0	579225	1
Bin	(1)	0	1	598341	1
Bin	(1)	1	0	599940	1
Bin	(0)	0	1	1174827	1
Bin	(0)	1	0	1173234	1

Signal:

DATA_LEN_CAN_FD

	Element	From	To	Count	Threshold
Bin	(6)	0	1	340442	1
Bin	(6)	1	0	342038	1
Bin	(5)	0	1	494238	1
Bin	(5)	1	0	495838	1
Bin	(4)	0	1	754458	1
Bin	(4)	1	0	756057	1
Bin	(3)	0	1	834019	1
Bin	(3)	1	0	835620	1
Bin	(2)	0	1	1002147	1
Bin	(2)	1	0	1003743	1
Bin	(1)	0	1	598341	1
Bin	(1)	1	0	599940	1
Bin	(0)	0	1	1174827	1
Bin	(0)	1	0	1173234	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression on line 130:

dlc_int <= 8

	Evaluated to	Count	Threshold
Bin	False	3941774	1
Bin	True	6064162	1

"<=" expression on line 137:

dlc_int <= 8

	Evaluated to	Count	Threshold
Bin	False	3941774	1
Bin	True	6064162	1

"=" expression on line 142:

frame_type = NORMAL_CAN

	Evaluated to	Count	Threshold
Bin	False	3306180	1
Bin	True	2387558	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST_COMB

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 114:

If statement on lines 117 to 125:

Signal assignment statement on line 118:

Signal assignment statement on line 119:

Signal assignment statement on line 120:

Signal assignment statement on line 121:

Signal assignment statement on line 122:

Signal assignment statement on line 123:

Signal assignment statement on line 124:

Signal assignment statement on line 125:

If statement on lines 130 to 132:

Signal assignment statement on line 130:

Signal assignment statement on line 132:

If statement on lines 137 to 139:

Signal assignment statement on line 137:

Signal assignment statement on line 139:

If statement on lines 142 to 144:

Signal assignment statement on line 142:

Signal assignment statement on line 144:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 118:

"if" / "when" / "else" condition on line 119:

"if" / "when" / "else" condition on line 120:

"if" / "when" / "else" condition on line 121:

"if" / "when" / "else" condition on line 122:

"if" / "when" / "else" condition on line 123:

"if" / "when" / "else" condition on line 124:

"if" / "when" / "else" condition on line 130:

"if" / "when" / "else" condition on line 137:

"if" / "when" / "else" condition on line 142:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression on line 130:

"<=" expression on line 137:

"=" expression on line 142:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: