NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

155:            if (rising_edge(clk_sys)) then 
156:                for i in 0 to G_WORD_WIDTH/8 - 1 loop 
...
161:                end loop; 
162:            end if;

Count: 27284132
Threshold: 1

Loop statement:

156:                for i in 0 to G_WORD_WIDTH/8 - 1 loop 
157:                    if (byte_we(i) = '1') then 
158:                        ram_memory(to_integer(unsigned(addr_A)))(i * 8 + 7 downto i * 8) 
159:                            <= data_in(i * 8 + 7 downto i * 8); 
160:                    end if; 
161:                end loop;

Count: 13641406
Threshold: 1

If statement:

157:                    if (byte_we(i) = '1') then 
158:                        ram_memory(to_integer(unsigned(addr_A)))(i * 8 + 7 downto i * 8) 
159:                            <= data_in(i * 8 + 7 downto i * 8); 
160:                    end if;

Count: 54565624
Threshold: 1

Signal assignment statement:

158:                        ram_memory(to_integer(unsigned(addr_A)))(i * 8 + 7 downto i * 8) 
159:                            <= data_in(i * 8 + 7 downto i * 8);

Count: 186012
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

155: if (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	13641406	1
Bin	False	13642726	1

"if" / "when" / "else" condition:

157: if (byte_we(i) = '1') then

	Evaluated to	Count	Threshold
Bin	True	186012	1
Bin	False	54379612	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

157: if (byte_we(i) = '1') then

	Evaluated to	Count	Threshold
Bin	False	54379612	1
Bin	True	186012	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.RAM_RST_FALSE_GEN

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Loop statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: