NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.G_EACH_BUF(2).TXT_BUF_EVEN_GEN.FUNC_COV_TXT_BUFFER_EVEN_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_txt_buffer_even.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.G_EACH_BUF(2).TXT_BUF_EVEN_GEN.FUNC_COV_TXT_BUFFER_EVEN_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (16/16) 100.0 % (18/18)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin01811587771
Bin10811594371

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

148:    -- psl txtb_set_ready_cov : cover {mr_tx_command_txcr = '1' and mr_tx_command_txbi = '1'}; 
Count: 927
Threshold: 1

PSL cover point:

149:    -- psl txtb_set_empty_cov : cover {mr_tx_command_txce = '1' and mr_tx_command_txbi = '1'}; 
Count: 88
Threshold: 1

PSL cover point:

150:    -- psl txtb_set_abort_cov : cover {mr_tx_command_txca = '1' and mr_tx_command_txbi = '1'}; 
Count: 181
Threshold: 1

PSL cover point:

156:    -- psl txtb_hw_lock     : cover {txtb_hw_cmd.lock = '1'     and txtb_hw_cmd_cs = '1'}; 
Count: 889
Threshold: 1

PSL cover point:

157:    -- psl txtb_hw_valid    : cover {txtb_hw_cmd.valid = '1'    and txtb_hw_cmd_cs = '1'}; 
Count: 396
Threshold: 1

PSL cover point:

158:    -- psl txtb_hw_err      : cover {txtb_hw_cmd.err = '1'      and txtb_hw_cmd_cs = '1'}; 
Count: 179
Threshold: 1

PSL cover point:

159:    -- psl txtb_hw_arbl     : cover {txtb_hw_cmd.arbl = '1'     and txtb_hw_cmd_cs = '1'}; 
Count: 4
Threshold: 1

PSL cover point:

160:    -- psl txtb_hw_failed   : cover {txtb_hw_cmd.failed = '1'   and txtb_hw_cmd_cs = '1'}; 
Count: 310
Threshold: 1

PSL cover point:

166:    -- psl txtb_perr_txt_ready_cov : cover 
167:    --      {curr_state = s_txt_ready and txtb_parity_error_valid = '1'}; 
Count: 61
Threshold: 1

PSL cover point:

169:    -- psl txtb_perr_txt_tx_prog_cov : cover 
170:    --      {curr_state = s_txt_tx_prog and txtb_parity_error_valid = '1'}; 
Count: 31
Threshold: 1

PSL cover point:

172:    -- psl txtb_perr_txt_ab_prog_cov : cover 
173:    --      {curr_state = s_txt_ab_prog and txtb_parity_error_valid = '1'}; 
Count: 12
Threshold: 1

PSL cover point:

179:    -- psl txtb_hw_sw_cmd_txt_ready_hazard_cov : cover 
180:    --  {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1' and abort_applied = '1' and 
181:    --   curr_state = s_txt_ready}; 
Count: 4
Threshold: 1

PSL cover point:

183:    -- psl txtb_hw_sw_cmd_txt_tx_prog_hazard_cov : cover 
184:    --  {((txtb_hw_cmd_i.valid = '1' or txtb_hw_cmd_i.err = '1' or 
185:    --     txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.failed = '1') and 
186:    --    abort_applied = '1' and curr_state = s_txt_tx_prog)}; 
Count: 4
Threshold: 1

PSL cover point:

192:    -- psl txtb_ready_to_abt_in_progress_cov : cover 
193:    --  {curr_state = s_txt_ready and next_state = s_txt_ab_prog and txt_fsm_ce = '1'}; 
Count: 4
Threshold: 1

PSL cover point:

195:    -- psl txtb_abt_in_progress_to_parity_error_cov : cover 
196:    --  {curr_state = s_txt_ab_prog and next_state = s_txt_parity_err and txt_fsm_ce = '1'}; 
Count: 12
Threshold: 1

PSL cover point:

198:    -- psl txtb_tx_in_progress_to_aborted_cov : cover 
199:    --  {curr_state = s_txt_tx_prog and next_state = s_txt_aborted and txt_fsm_ce = '1'}; 
Count: 4
Threshold: 1