File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_agent.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Functional coverage agent
71: --
72: -- Functional coverage agent implements functional coverage (PSL assertions)
73: -- for CTU CAN FD. The internal signals of the DUT are probed by External
74: -- Names.
75: --
76: --------------------------------------------------------------------------------
77: -- Revision History:
78: -- 27.4.2025 Created file
79: --------------------------------------------------------------------------------
80:
81: Library ctu_can_fd_tb;
82: context ctu_can_fd_tb.ieee_context;
83: context ctu_can_fd_tb.tb_common_context;
84:
85: use ctu_can_fd_tb.clk_gen_agent_pkg.all;
86: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
87:
88: entity func_cov_agent is
89: generic (
90: -- RX Buffer size
91: G_RX_BUFF_SIZE : natural range 32 to 4096;
92:
93: -- Number of TXT Buffers
94: G_TXT_BUFFER_COUNT : natural range 1 to 8
95: );
96: port (
97: -- DUT clock
98: clk : in std_logic
99: );
100: end entity;
101:
102: architecture tb of func_cov_agent is
103:
104: signal clk_delayed : std_logic;
105:
106: begin
107:
108: -- Delay the clock so that we always sample stable signals and
109: -- avoid possible delta-races. 1 ps should be "good enogh" that
110: -- no signals
111: clk_delayed <= clk after 1 ps;
112:
113: func_cov_can_core_inst : entity ctu_can_fd_tb.func_cov_can_core
114: port map (
115: clk => clk_delayed
116: );
117:
118: func_cov_prescaler_inst : entity ctu_can_fd_tb.func_cov_prescaler
119: port map (
120: clk => clk_delayed
121: );
122:
123: func_cov_prescaler_nbt_inst : entity ctu_can_fd_tb.func_cov_prescaler_nbt
124: port map (
125: clk => clk_delayed
126: );
127:
128: func_cov_prescaler_dbt_inst : entity ctu_can_fd_tb.func_cov_prescaler_dbt
129: port map (
130: clk => clk_delayed
131: );
132:
133: func_cov_bus_sampling_inst : entity ctu_can_fd_tb.func_cov_bus_sampling
134: port map (
135: clk => clk_delayed
136: );
137:
138: func_cov_rx_buffer_inst : entity ctu_can_fd_tb.func_cov_rx_buffer
139: generic map (
140: G_RX_BUFF_SIZE => G_RX_BUFF_SIZE
141: )
142: port map (
143: clk => clk_delayed
144: );
145:
146: func_cov_tx_arbitrator_inst : entity ctu_can_fd_tb.func_cov_tx_arbitrator
147: generic map (
148: G_TXT_BUFFER_COUNT => G_TXT_BUFFER_COUNT
149: )
150: port map (
151: clk => clk_delayed
152: );
153:
154: g_each_buf : for i in 0 to G_TXT_BUFFER_COUNT - 1 generate
155: begin
156: txt_buf_even_gen : if ((i mod 2) = 0) generate
157: func_cov_txt_buffer_even_inst : entity ctu_can_fd_tb.func_cov_txt_buffer_even
158: generic map (
159: G_TXT_BUFFER_INDEX => i
160: )
161: port map (
162: clk => clk_delayed
163: );
164: end generate;
165:
166: txt_buf_odd_gen : if ((i mod 2) = 1) generate
167: func_cov_txt_buffer_odd_inst : entity ctu_can_fd_tb.func_cov_txt_buffer_odd
168: generic map (
169: G_TXT_BUFFER_INDEX => i
170: )
171: port map (
172: clk => clk_delayed
173: );
174: end generate;
175:
176: end generate;
177:
178: end architecture;