NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_manager.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST.INT_MODULE_GEN(10).INT_MODULE_INST	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST.INT_MODULE_GEN(10).INT_MODULE_INST

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 159 to 173:

159:        if (res_n = '0') then 
160:            int_status <= '0'; 
...
172:            end if; 
173:        end if;

Count: 1090019739
Threshold: 1

Signal assignment statement on line 160:

160: int_status <= '0';
Count: 67370
Threshold: 1

If statement on lines 165 to 172:

165:            if (int_status_set = '1' and int_mask_i = '0') then 
166:                int_status <= '1'; 
...
171: 
172:            end if;

Count: 544969539
Threshold: 1

Signal assignment statement on line 166:

166: int_status <= '1';
Count: 37270809
Threshold: 1

Signal assignment statement on line 170:

170: int_status <= '0';
Count: 25
Threshold: 1

If statement on lines 183 to 193:

183:        if (res_n = '0') then 
184:            int_mask_i <= '0'; 
...
192: 
193:        end if;

Count: 1090019739
Threshold: 1

Signal assignment statement on line 184:

184: int_mask_i <= '0';
Count: 67370
Threshold: 1

If statement on lines 189 to 191:

189:            if (int_mask_load = '1') then 
190:                int_mask_i <= int_mask_next; 
191:            end if;

Count: 544969539
Threshold: 1

Signal assignment statement on line 190:

190: int_mask_i <= int_mask_next;
Count: 475
Threshold: 1

Signal assignment statement on line 196:

196: int_mask_load <= int_mask_set or int_mask_clear;
Count: 5577
Threshold: 1

If statement on lines 197 to 199:

197:    int_mask_next <= '1' when (int_mask_set = '1') 
198:                         else 
199:                     '0';

Count: 4192
Threshold: 1

Signal assignment statement on line 197:

197: int_mask_next <= '1' when (int_mask_set = '1')
Count: 40
Threshold: 1

Signal assignment statement on line 199:

199: '0';
Count: 4152
Threshold: 1

If statement on lines 206 to 220:

206:        if (res_n = '0') then 
207:            int_ena_i <= '0'; 
...
219:            end if; 
220:        end if;

Count: 1090019739
Threshold: 1

Signal assignment statement on line 207:

207: int_ena_i <= '0';
Count: 67370
Threshold: 1

If statement on lines 212 to 219:

212:            if (int_ena_set = '1') then 
213:                int_ena_i <= '1'; 
...
218: 
219:            end if;

Count: 544969539
Threshold: 1

Signal assignment statement on line 213:

213: int_ena_i <= '1';
Count: 30
Threshold: 1

Signal assignment statement on line 217:

217: int_ena_i <= '0';
Count: 512
Threshold: 1

Signal assignment statement on line 224:

224: int_mask <= int_mask_i;
Count: 3242
Threshold: 1

Signal assignment statement on line 225:

225: int_ena <= int_ena_i;
Count: 3262
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 159:

159: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	67370	1
Bin	False	1089952369	1

"if" / "when" / "else" condition on line 162:

162: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	544969539	1
Bin	False	544982830	1

"if" / "when" / "else" condition on line 165:

165: if (int_status_set = '1' and int_mask_i = '0') then

	Evaluated to	Count	Threshold
Bin	True	37270809	1
Bin	False	507698730	1

"if" / "when" / "else" condition on line 169:

169: elsif (int_status_clear = '1') then

	Evaluated to	Count	Threshold
Bin	True	25	1
Bin	False	507698705	1

"if" / "when" / "else" condition on line 183:

183: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	67370	1
Bin	False	1089952369	1

"if" / "when" / "else" condition on line 186:

186: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	544969539	1
Bin	False	544982830	1

"if" / "when" / "else" condition on line 189:

189: if (int_mask_load = '1') then

	Evaluated to	Count	Threshold
Bin	True	475	1
Bin	False	544969064	1

"if" / "when" / "else" condition on line 197:

197: int_mask_next <= '1' when (int_mask_set = '1')

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	4152	1

"if" / "when" / "else" condition on line 206:

206: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	67370	1
Bin	False	1089952369	1

"if" / "when" / "else" condition on line 209:

209: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	544969539	1
Bin	False	544982830	1

"if" / "when" / "else" condition on line 212:

212: if (int_ena_set = '1') then

	Evaluated to	Count	Threshold
Bin	True	30	1
Bin	False	544969509	1

"if" / "when" / "else" condition on line 216:

216: elsif (int_ena_clear = '1') then

	Evaluated to	Count	Threshold
Bin	True	512	1
Bin	False	544968997	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INT_STATUS_SET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INT_STATUS_CLEAR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INT_MASK_SET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INT_MASK_CLEAR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INT_ENA_SET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INT_ENA_CLEAR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

INT_STATUS

	From	To	Count	Threshold
Bin	0	1	936	1
Bin	1	0	2535	1

Port:

INT_MASK

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1621	1

Port:

INT_ENA

	From	To	Count	Threshold
Bin	0	1	30	1
Bin	1	0	1631	1

Signal:

INT_MASK_I

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1621	1

Signal:

INT_ENA_I

	From	To	Count	Threshold
Bin	0	1	30	1
Bin	1	0	1631	1

Signal:

INT_MASK_LOAD

	From	To	Count	Threshold
Bin	0	1	475	1
Bin	1	0	2551	1

Signal:

INT_MASK_NEXT

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	1641	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 159:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1089952369	1
Bin	True	67370	1

"and" expression on line 165:

 int_status_set = '1' and int_mask_i = '0' 
 <-------LHS-------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	507662228	1
Bin	True	False	2220	1
Bin	True	True	37270809	1

"=" expression on line 165:

int_status_set = '1'

	Evaluated to	Count	Threshold
Bin	False	507696510	1
Bin	True	37273029	1

"=" expression on line 165:

int_mask_i = '0'

	Evaluated to	Count	Threshold
Bin	False	36502	1
Bin	True	544933037	1

"=" expression on line 169:

int_status_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	507698705	1
Bin	True	25	1

"=" expression on line 183:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1089952369	1
Bin	True	67370	1

"=" expression on line 189:

int_mask_load = '1'

	Evaluated to	Count	Threshold
Bin	False	544969064	1
Bin	True	475	1

"or" expression on line 196:

 int_mask_set or int_mask_clear 
 <---LHS---->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	2551	1
Bin	'0'	'1'	435	1
Bin	'1'	'0'	40	1

"=" expression on line 197:

int_mask_set = '1'

	Evaluated to	Count	Threshold
Bin	False	4152	1
Bin	True	40	1

"=" expression on line 206:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1089952369	1
Bin	True	67370	1

"=" expression on line 212:

int_ena_set = '1'

	Evaluated to	Count	Threshold
Bin	False	544969509	1
Bin	True	30	1

"=" expression on line 216:

int_ena_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	544968997	1
Bin	True	512	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST.INT_MODULE_GEN(10).INT_MODULE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_manager.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 159 to 173:

Signal assignment statement on line 160:

If statement on lines 165 to 172:

Signal assignment statement on line 166:

Signal assignment statement on line 170:

If statement on lines 183 to 193:

Signal assignment statement on line 184:

If statement on lines 189 to 191:

Signal assignment statement on line 190:

Signal assignment statement on line 196:

If statement on lines 197 to 199:

Signal assignment statement on line 197:

Signal assignment statement on line 199:

If statement on lines 206 to 220:

Signal assignment statement on line 207:

If statement on lines 212 to 219:

Signal assignment statement on line 213:

Signal assignment statement on line 217:

Signal assignment statement on line 224:

Signal assignment statement on line 225:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 159:

"if" / "when" / "else" condition on line 162:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 183:

"if" / "when" / "else" condition on line 186:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 197:

"if" / "when" / "else" condition on line 206:

"if" / "when" / "else" condition on line 209:

"if" / "when" / "else" condition on line 212:

"if" / "when" / "else" condition on line 216:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 159:

"and" expression on line 165:

"=" expression on line 165:

"=" expression on line 165:

"=" expression on line 169:

"=" expression on line 183:

"=" expression on line 189:

"or" expression on line 196:

"=" expression on line 197:

"=" expression on line 206:

"=" expression on line 212:

"=" expression on line 216:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: