NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_F

File:  /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)

Details:

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Signal assignment statement on line 1610:

1610:        control_registers_out_i.filter_a_mask_bit_mask_a_val <= (others => '0'); 
Count: 941
Threshold: 1

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