File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Register map implementation of: Control_registers
70: --------------------------------------------------------------------------------
71: -- This file is autogenerated, DO NOT EDIT!
72:
73: Library ieee;
74: use ieee.std_logic_1164.all;
75:
76: Library ctu_can_fd_rtl;
77: use ctu_can_fd_rtl.can_registers_pkg.all;
78: use ctu_can_fd_rtl.cmn_reg_map_pkg.all;
79:
80: entity control_registers_reg_map is
81: generic (
82: constant DATA_WIDTH : natural := 32;
83: constant ADDRESS_WIDTH : natural := 8;
84: constant REGISTERED_READ : boolean := true;
85: constant CLEAR_READ_DATA : boolean := true;
86: constant SUP_FILT_A : boolean := true;
87: constant SUP_TRAFFIC_CTRS : boolean := true;
88: constant SUP_RANGE : boolean := true;
89: constant SUP_FILT_C : boolean := true;
90: constant SUP_FILT_B : boolean := true
91: );
92: port (
93: signal clk_sys :in std_logic;
94: signal res_n :in std_logic;
95: signal address :in std_logic_vector(address_width - 1 downto 0);
96: signal w_data :in std_logic_vector(data_width - 1 downto 0);
97: signal r_data :out std_logic_vector(data_width - 1 downto 0);
98: signal cs :in std_logic;
99: signal read :in std_logic;
100: signal write :in std_logic;
101: signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
102: signal lock_1 :in std_logic;
103: signal lock_2 :in std_logic;
104: signal control_registers_out :out Control_registers_out_t;
105: signal control_registers_in :in Control_registers_in_t
106: );
107: end entity control_registers_reg_map;
108:
109:
110: architecture rtl of control_registers_reg_map is
111: signal reg_sel : std_logic_vector(38 downto 0);
112: constant ADDR_VECT
113: : std_logic_vector(233 downto 0) := "100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
114: signal r_data_comb : std_logic_vector(31 downto 0);
115: signal read_data_mask_n : std_logic_vector(31 downto 0);
116: signal control_registers_out_i : Control_registers_out_t;
117: signal write_en : std_logic_vector(3 downto 0);
118: begin
119:
120: write_en <= be when (write = '1' and cs = '1') else (others => '0');
121:
122: ----------------------------------------------------------------------------
123: -- Write address to One-hot decoder
124: ----------------------------------------------------------------------------
125:
126: address_decoder_control_registers_comp : address_decoder
127: generic map(
128: address_width => 6 ,
129: address_entries => 39 ,
130: addr_vect => ADDR_VECT ,
131: registered_out => false
132: )
133: port map(
134: clk_sys => clk_sys ,-- in
135: res_n => res_n ,-- in
136: address => address(7 downto 2) ,-- in
137: enable => cs ,-- in
138: addr_dec => reg_sel -- out
139: );
140:
141: ----------------------------------------------------------------------------
142: -- MODE[RST]
143: ----------------------------------------------------------------------------
144:
145: mode_rst_reg_comp : memory_reg_os
146: generic map(
147: data_width => 1 ,
148: reset_value => "0"
149: )
150: port map(
151: clk_sys => clk_sys ,-- in
152: res_n => res_n ,-- in
153: data_in => w_data(0 downto 0) ,-- in
154: write => write_en(0) ,-- in
155: cs => reg_sel(1) ,-- in
156: reg_value(0) => control_registers_out_i.mode_rst -- out
157: );
158:
159: ----------------------------------------------------------------------------
160: -- MODE[BMM]
161: ----------------------------------------------------------------------------
162:
163: mode_bmm_reg_comp : memory_reg_rw
164: generic map(
165: data_width => 1 ,
166: reset_value => "0"
167: )
168: port map(
169: clk_sys => clk_sys ,-- in
170: res_n => res_n ,-- in
171: data_in => w_data(1 downto 1) ,-- in
172: write => write_en(0) ,-- in
173: cs => reg_sel(1) ,-- in
174: reg_value(0) => control_registers_out_i.mode_bmm -- out
175: );
176:
177: ----------------------------------------------------------------------------
178: -- MODE[STM]
179: ----------------------------------------------------------------------------
180:
181: mode_stm_reg_comp : memory_reg_rw
182: generic map(
183: data_width => 1 ,
184: reset_value => "0"
185: )
186: port map(
187: clk_sys => clk_sys ,-- in
188: res_n => res_n ,-- in
189: data_in => w_data(2 downto 2) ,-- in
190: write => write_en(0) ,-- in
191: cs => reg_sel(1) ,-- in
192: reg_value(0) => control_registers_out_i.mode_stm -- out
193: );
194:
195: ----------------------------------------------------------------------------
196: -- MODE[AFM]
197: ----------------------------------------------------------------------------
198:
199: mode_afm_reg_comp : memory_reg_rw
200: generic map(
201: data_width => 1 ,
202: reset_value => "0"
203: )
204: port map(
205: clk_sys => clk_sys ,-- in
206: res_n => res_n ,-- in
207: data_in => w_data(3 downto 3) ,-- in
208: write => write_en(0) ,-- in
209: cs => reg_sel(1) ,-- in
210: reg_value(0) => control_registers_out_i.mode_afm -- out
211: );
212:
213: ----------------------------------------------------------------------------
214: -- MODE[FDE]
215: ----------------------------------------------------------------------------
216:
217: mode_fde_reg_comp : memory_reg_rw
218: generic map(
219: data_width => 1 ,
220: reset_value => "1"
221: )
222: port map(
223: clk_sys => clk_sys ,-- in
224: res_n => res_n ,-- in
225: data_in => w_data(4 downto 4) ,-- in
226: write => write_en(0) ,-- in
227: cs => reg_sel(1) ,-- in
228: reg_value(0) => control_registers_out_i.mode_fde -- out
229: );
230:
231: ----------------------------------------------------------------------------
232: -- MODE[TTTM]
233: ----------------------------------------------------------------------------
234:
235: mode_tttm_reg_comp : memory_reg_rw
236: generic map(
237: data_width => 1 ,
238: reset_value => "0"
239: )
240: port map(
241: clk_sys => clk_sys ,-- in
242: res_n => res_n ,-- in
243: data_in => w_data(5 downto 5) ,-- in
244: write => write_en(0) ,-- in
245: cs => reg_sel(1) ,-- in
246: reg_value(0) => control_registers_out_i.mode_tttm -- out
247: );
248:
249: ----------------------------------------------------------------------------
250: -- MODE[ROM]
251: ----------------------------------------------------------------------------
252:
253: mode_rom_reg_comp : memory_reg_rw
254: generic map(
255: data_width => 1 ,
256: reset_value => "0"
257: )
258: port map(
259: clk_sys => clk_sys ,-- in
260: res_n => res_n ,-- in
261: data_in => w_data(6 downto 6) ,-- in
262: write => write_en(0) ,-- in
263: cs => reg_sel(1) ,-- in
264: reg_value(0) => control_registers_out_i.mode_rom -- out
265: );
266:
267: ----------------------------------------------------------------------------
268: -- MODE[ACF]
269: ----------------------------------------------------------------------------
270:
271: mode_acf_reg_comp : memory_reg_rw
272: generic map(
273: data_width => 1 ,
274: reset_value => "0"
275: )
276: port map(
277: clk_sys => clk_sys ,-- in
278: res_n => res_n ,-- in
279: data_in => w_data(7 downto 7) ,-- in
280: write => write_en(0) ,-- in
281: cs => reg_sel(1) ,-- in
282: reg_value(0) => control_registers_out_i.mode_acf -- out
283: );
284:
285: ----------------------------------------------------------------------------
286: -- MODE[TSTM]
287: ----------------------------------------------------------------------------
288:
289: mode_tstm_reg_comp : memory_reg_rw
290: generic map(
291: data_width => 1 ,
292: reset_value => "0"
293: )
294: port map(
295: clk_sys => clk_sys ,-- in
296: res_n => res_n ,-- in
297: data_in => w_data(8 downto 8) ,-- in
298: write => write_en(1) ,-- in
299: cs => reg_sel(1) ,-- in
300: reg_value(0) => control_registers_out_i.mode_tstm -- out
301: );
302:
303: ----------------------------------------------------------------------------
304: -- MODE[RXBAM]
305: ----------------------------------------------------------------------------
306:
307: mode_rxbam_reg_comp : memory_reg_rw
308: generic map(
309: data_width => 1 ,
310: reset_value => "1"
311: )
312: port map(
313: clk_sys => clk_sys ,-- in
314: res_n => res_n ,-- in
315: data_in => w_data(9 downto 9) ,-- in
316: write => write_en(1) ,-- in
317: cs => reg_sel(1) ,-- in
318: reg_value(0) => control_registers_out_i.mode_rxbam -- out
319: );
320:
321: ----------------------------------------------------------------------------
322: -- MODE[TXBBM]
323: ----------------------------------------------------------------------------
324:
325: mode_txbbm_reg_comp : memory_reg_rw
326: generic map(
327: data_width => 1 ,
328: reset_value => "0"
329: )
330: port map(
331: clk_sys => clk_sys ,-- in
332: res_n => res_n ,-- in
333: data_in => w_data(10 downto 10) ,-- in
334: write => write_en(1) ,-- in
335: cs => reg_sel(1) ,-- in
336: reg_value(0) => control_registers_out_i.mode_txbbm -- out
337: );
338:
339: ----------------------------------------------------------------------------
340: -- MODE[SAM]
341: ----------------------------------------------------------------------------
342:
343: mode_sam_reg_comp : memory_reg_rw
344: generic map(
345: data_width => 1 ,
346: reset_value => "0"
347: )
348: port map(
349: clk_sys => clk_sys ,-- in
350: res_n => res_n ,-- in
351: data_in => w_data(11 downto 11) ,-- in
352: write => write_en(1) ,-- in
353: cs => reg_sel(1) ,-- in
354: reg_value(0) => control_registers_out_i.mode_sam -- out
355: );
356:
357: ----------------------------------------------------------------------------
358: -- MODE[ERFM]
359: ----------------------------------------------------------------------------
360:
361: mode_erfm_reg_comp : memory_reg_rw
362: generic map(
363: data_width => 1 ,
364: reset_value => "0"
365: )
366: port map(
367: clk_sys => clk_sys ,-- in
368: res_n => res_n ,-- in
369: data_in => w_data(12 downto 12) ,-- in
370: write => write_en(1) ,-- in
371: cs => reg_sel(1) ,-- in
372: reg_value(0) => control_registers_out_i.mode_erfm -- out
373: );
374:
375: ----------------------------------------------------------------------------
376: -- SETTINGS[RTRLE]
377: ----------------------------------------------------------------------------
378:
379: settings_rtrle_reg_comp : memory_reg_rw
380: generic map(
381: data_width => 1 ,
382: reset_value => "0"
383: )
384: port map(
385: clk_sys => clk_sys ,-- in
386: res_n => res_n ,-- in
387: data_in => w_data(16 downto 16) ,-- in
388: write => write_en(2) ,-- in
389: cs => reg_sel(1) ,-- in
390: reg_value(0) => control_registers_out_i.settings_rtrle -- out
391: );
392:
393: ----------------------------------------------------------------------------
394: -- SETTINGS[RTRTH]
395: ----------------------------------------------------------------------------
396:
397: settings_rtrth_reg_comp : memory_reg_rw
398: generic map(
399: data_width => 4 ,
400: reset_value => "0000"
401: )
402: port map(
403: clk_sys => clk_sys ,-- in
404: res_n => res_n ,-- in
405: data_in => w_data(20 downto 17) ,-- in
406: write => write_en(2) ,-- in
407: cs => reg_sel(1) ,-- in
408: reg_value => control_registers_out_i.settings_rtrth -- out
409: );
410:
411: ----------------------------------------------------------------------------
412: -- SETTINGS[ILBP]
413: ----------------------------------------------------------------------------
414:
415: settings_ilbp_reg_comp : memory_reg_rw
416: generic map(
417: data_width => 1 ,
418: reset_value => "0"
419: )
420: port map(
421: clk_sys => clk_sys ,-- in
422: res_n => res_n ,-- in
423: data_in => w_data(21 downto 21) ,-- in
424: write => write_en(2) ,-- in
425: cs => reg_sel(1) ,-- in
426: reg_value(0) => control_registers_out_i.settings_ilbp -- out
427: );
428:
429: ----------------------------------------------------------------------------
430: -- SETTINGS[ENA]
431: ----------------------------------------------------------------------------
432:
433: settings_ena_reg_comp : memory_reg_rw
434: generic map(
435: data_width => 1 ,
436: reset_value => "0"
437: )
438: port map(
439: clk_sys => clk_sys ,-- in
440: res_n => res_n ,-- in
441: data_in => w_data(22 downto 22) ,-- in
442: write => write_en(2) ,-- in
443: cs => reg_sel(1) ,-- in
444: reg_value(0) => control_registers_out_i.settings_ena -- out
445: );
446:
447: ----------------------------------------------------------------------------
448: -- SETTINGS[NISOFD]
449: ----------------------------------------------------------------------------
450:
451: settings_nisofd_reg_comp : memory_reg_rw
452: generic map(
453: data_width => 1 ,
454: reset_value => "0"
455: )
456: port map(
457: clk_sys => clk_sys ,-- in
458: res_n => res_n ,-- in
459: data_in => w_data(23 downto 23) ,-- in
460: write => write_en(2) ,-- in
461: cs => reg_sel(1) ,-- in
462: reg_value(0) => control_registers_out_i.settings_nisofd -- out
463: );
464:
465: ----------------------------------------------------------------------------
466: -- SETTINGS[PEX]
467: ----------------------------------------------------------------------------
468:
469: settings_pex_reg_comp : memory_reg_rw
470: generic map(
471: data_width => 1 ,
472: reset_value => "0"
473: )
474: port map(
475: clk_sys => clk_sys ,-- in
476: res_n => res_n ,-- in
477: data_in => w_data(24 downto 24) ,-- in
478: write => write_en(3) ,-- in
479: cs => reg_sel(1) ,-- in
480: reg_value(0) => control_registers_out_i.settings_pex -- out
481: );
482:
483: ----------------------------------------------------------------------------
484: -- SETTINGS[TBFBO]
485: ----------------------------------------------------------------------------
486:
487: settings_tbfbo_reg_comp : memory_reg_rw
488: generic map(
489: data_width => 1 ,
490: reset_value => "1"
491: )
492: port map(
493: clk_sys => clk_sys ,-- in
494: res_n => res_n ,-- in
495: data_in => w_data(25 downto 25) ,-- in
496: write => write_en(3) ,-- in
497: cs => reg_sel(1) ,-- in
498: reg_value(0) => control_registers_out_i.settings_tbfbo -- out
499: );
500:
501: ----------------------------------------------------------------------------
502: -- SETTINGS[FDRF]
503: ----------------------------------------------------------------------------
504:
505: settings_fdrf_reg_comp : memory_reg_rw
506: generic map(
507: data_width => 1 ,
508: reset_value => "0"
509: )
510: port map(
511: clk_sys => clk_sys ,-- in
512: res_n => res_n ,-- in
513: data_in => w_data(26 downto 26) ,-- in
514: write => write_en(3) ,-- in
515: cs => reg_sel(1) ,-- in
516: reg_value(0) => control_registers_out_i.settings_fdrf -- out
517: );
518:
519: ----------------------------------------------------------------------------
520: -- SETTINGS[PCHKE]
521: ----------------------------------------------------------------------------
522:
523: settings_pchke_reg_comp : memory_reg_rw
524: generic map(
525: data_width => 1 ,
526: reset_value => "0"
527: )
528: port map(
529: clk_sys => clk_sys ,-- in
530: res_n => res_n ,-- in
531: data_in => w_data(27 downto 27) ,-- in
532: write => write_en(3) ,-- in
533: cs => reg_sel(1) ,-- in
534: reg_value(0) => control_registers_out_i.settings_pchke -- out
535: );
536:
537: ----------------------------------------------------------------------------
538: -- COMMAND[RXRPMV]
539: ----------------------------------------------------------------------------
540:
541: command_rxrpmv_reg_comp : memory_reg_os
542: generic map(
543: data_width => 1 ,
544: reset_value => "0"
545: )
546: port map(
547: clk_sys => clk_sys ,-- in
548: res_n => res_n ,-- in
549: data_in => w_data(1 downto 1) ,-- in
550: write => write_en(0) ,-- in
551: cs => reg_sel(3) ,-- in
552: reg_value(0) => control_registers_out_i.command_rxrpmv -- out
553: );
554:
555: ----------------------------------------------------------------------------
556: -- COMMAND[RRB]
557: ----------------------------------------------------------------------------
558:
559: command_rrb_reg_comp : memory_reg_os
560: generic map(
561: data_width => 1 ,
562: reset_value => "0"
563: )
564: port map(
565: clk_sys => clk_sys ,-- in
566: res_n => res_n ,-- in
567: data_in => w_data(2 downto 2) ,-- in
568: write => write_en(0) ,-- in
569: cs => reg_sel(3) ,-- in
570: reg_value(0) => control_registers_out_i.command_rrb -- out
571: );
572:
573: ----------------------------------------------------------------------------
574: -- COMMAND[CDO]
575: ----------------------------------------------------------------------------
576:
577: command_cdo_reg_comp : memory_reg_os
578: generic map(
579: data_width => 1 ,
580: reset_value => "0"
581: )
582: port map(
583: clk_sys => clk_sys ,-- in
584: res_n => res_n ,-- in
585: data_in => w_data(3 downto 3) ,-- in
586: write => write_en(0) ,-- in
587: cs => reg_sel(3) ,-- in
588: reg_value(0) => control_registers_out_i.command_cdo -- out
589: );
590:
591: ----------------------------------------------------------------------------
592: -- COMMAND[ERCRST]
593: ----------------------------------------------------------------------------
594:
595: command_ercrst_reg_comp : memory_reg_os
596: generic map(
597: data_width => 1 ,
598: reset_value => "0"
599: )
600: port map(
601: clk_sys => clk_sys ,-- in
602: res_n => res_n ,-- in
603: data_in => w_data(4 downto 4) ,-- in
604: write => write_en(0) ,-- in
605: cs => reg_sel(3) ,-- in
606: reg_value(0) => control_registers_out_i.command_ercrst -- out
607: );
608:
609: ----------------------------------------------------------------------------
610: -- COMMAND[RXFCRST]
611: ----------------------------------------------------------------------------
612:
613: command_rxfcrst_reg_comp : memory_reg_os
614: generic map(
615: data_width => 1 ,
616: reset_value => "0"
617: )
618: port map(
619: clk_sys => clk_sys ,-- in
620: res_n => res_n ,-- in
621: data_in => w_data(5 downto 5) ,-- in
622: write => write_en(0) ,-- in
623: cs => reg_sel(3) ,-- in
624: reg_value(0) => control_registers_out_i.command_rxfcrst -- out
625: );
626:
627: ----------------------------------------------------------------------------
628: -- COMMAND[TXFCRST]
629: ----------------------------------------------------------------------------
630:
631: command_txfcrst_reg_comp : memory_reg_os
632: generic map(
633: data_width => 1 ,
634: reset_value => "0"
635: )
636: port map(
637: clk_sys => clk_sys ,-- in
638: res_n => res_n ,-- in
639: data_in => w_data(6 downto 6) ,-- in
640: write => write_en(0) ,-- in
641: cs => reg_sel(3) ,-- in
642: reg_value(0) => control_registers_out_i.command_txfcrst -- out
643: );
644:
645: ----------------------------------------------------------------------------
646: -- COMMAND[CPEXS]
647: ----------------------------------------------------------------------------
648:
649: command_cpexs_reg_comp : memory_reg_os
650: generic map(
651: data_width => 1 ,
652: reset_value => "0"
653: )
654: port map(
655: clk_sys => clk_sys ,-- in
656: res_n => res_n ,-- in
657: data_in => w_data(7 downto 7) ,-- in
658: write => write_en(0) ,-- in
659: cs => reg_sel(3) ,-- in
660: reg_value(0) => control_registers_out_i.command_cpexs -- out
661: );
662:
663: ----------------------------------------------------------------------------
664: -- COMMAND[CRXPE]
665: ----------------------------------------------------------------------------
666:
667: command_crxpe_reg_comp : memory_reg_os
668: generic map(
669: data_width => 1 ,
670: reset_value => "0"
671: )
672: port map(
673: clk_sys => clk_sys ,-- in
674: res_n => res_n ,-- in
675: data_in => w_data(8 downto 8) ,-- in
676: write => write_en(1) ,-- in
677: cs => reg_sel(3) ,-- in
678: reg_value(0) => control_registers_out_i.command_crxpe -- out
679: );
680:
681: ----------------------------------------------------------------------------
682: -- COMMAND[CTXPE]
683: ----------------------------------------------------------------------------
684:
685: command_ctxpe_reg_comp : memory_reg_os
686: generic map(
687: data_width => 1 ,
688: reset_value => "0"
689: )
690: port map(
691: clk_sys => clk_sys ,-- in
692: res_n => res_n ,-- in
693: data_in => w_data(9 downto 9) ,-- in
694: write => write_en(1) ,-- in
695: cs => reg_sel(3) ,-- in
696: reg_value(0) => control_registers_out_i.command_ctxpe -- out
697: );
698:
699: ----------------------------------------------------------------------------
700: -- COMMAND[CTXDPE]
701: ----------------------------------------------------------------------------
702:
703: command_ctxdpe_reg_comp : memory_reg_os
704: generic map(
705: data_width => 1 ,
706: reset_value => "0"
707: )
708: port map(
709: clk_sys => clk_sys ,-- in
710: res_n => res_n ,-- in
711: data_in => w_data(10 downto 10) ,-- in
712: write => write_en(1) ,-- in
713: cs => reg_sel(3) ,-- in
714: reg_value(0) => control_registers_out_i.command_ctxdpe -- out
715: );
716:
717: ----------------------------------------------------------------------------
718: -- INT_STAT[RXI]
719: ----------------------------------------------------------------------------
720:
721: int_stat_rxi_reg_comp : memory_reg_os
722: generic map(
723: data_width => 1 ,
724: reset_value => "0"
725: )
726: port map(
727: clk_sys => clk_sys ,-- in
728: res_n => res_n ,-- in
729: data_in => w_data(0 downto 0) ,-- in
730: write => write_en(0) ,-- in
731: cs => reg_sel(4) ,-- in
732: reg_value(0) => control_registers_out_i.int_stat_rxi -- out
733: );
734:
735: ----------------------------------------------------------------------------
736: -- INT_STAT[TXI]
737: ----------------------------------------------------------------------------
738:
739: int_stat_txi_reg_comp : memory_reg_os
740: generic map(
741: data_width => 1 ,
742: reset_value => "0"
743: )
744: port map(
745: clk_sys => clk_sys ,-- in
746: res_n => res_n ,-- in
747: data_in => w_data(1 downto 1) ,-- in
748: write => write_en(0) ,-- in
749: cs => reg_sel(4) ,-- in
750: reg_value(0) => control_registers_out_i.int_stat_txi -- out
751: );
752:
753: ----------------------------------------------------------------------------
754: -- INT_STAT[EWLI]
755: ----------------------------------------------------------------------------
756:
757: int_stat_ewli_reg_comp : memory_reg_os
758: generic map(
759: data_width => 1 ,
760: reset_value => "0"
761: )
762: port map(
763: clk_sys => clk_sys ,-- in
764: res_n => res_n ,-- in
765: data_in => w_data(2 downto 2) ,-- in
766: write => write_en(0) ,-- in
767: cs => reg_sel(4) ,-- in
768: reg_value(0) => control_registers_out_i.int_stat_ewli -- out
769: );
770:
771: ----------------------------------------------------------------------------
772: -- INT_STAT[DOI]
773: ----------------------------------------------------------------------------
774:
775: int_stat_doi_reg_comp : memory_reg_os
776: generic map(
777: data_width => 1 ,
778: reset_value => "0"
779: )
780: port map(
781: clk_sys => clk_sys ,-- in
782: res_n => res_n ,-- in
783: data_in => w_data(3 downto 3) ,-- in
784: write => write_en(0) ,-- in
785: cs => reg_sel(4) ,-- in
786: reg_value(0) => control_registers_out_i.int_stat_doi -- out
787: );
788:
789: ----------------------------------------------------------------------------
790: -- INT_STAT[FCSI]
791: ----------------------------------------------------------------------------
792:
793: int_stat_fcsi_reg_comp : memory_reg_os
794: generic map(
795: data_width => 1 ,
796: reset_value => "0"
797: )
798: port map(
799: clk_sys => clk_sys ,-- in
800: res_n => res_n ,-- in
801: data_in => w_data(4 downto 4) ,-- in
802: write => write_en(0) ,-- in
803: cs => reg_sel(4) ,-- in
804: reg_value(0) => control_registers_out_i.int_stat_fcsi -- out
805: );
806:
807: ----------------------------------------------------------------------------
808: -- INT_STAT[ALI]
809: ----------------------------------------------------------------------------
810:
811: int_stat_ali_reg_comp : memory_reg_os
812: generic map(
813: data_width => 1 ,
814: reset_value => "0"
815: )
816: port map(
817: clk_sys => clk_sys ,-- in
818: res_n => res_n ,-- in
819: data_in => w_data(5 downto 5) ,-- in
820: write => write_en(0) ,-- in
821: cs => reg_sel(4) ,-- in
822: reg_value(0) => control_registers_out_i.int_stat_ali -- out
823: );
824:
825: ----------------------------------------------------------------------------
826: -- INT_STAT[BEI]
827: ----------------------------------------------------------------------------
828:
829: int_stat_bei_reg_comp : memory_reg_os
830: generic map(
831: data_width => 1 ,
832: reset_value => "0"
833: )
834: port map(
835: clk_sys => clk_sys ,-- in
836: res_n => res_n ,-- in
837: data_in => w_data(6 downto 6) ,-- in
838: write => write_en(0) ,-- in
839: cs => reg_sel(4) ,-- in
840: reg_value(0) => control_registers_out_i.int_stat_bei -- out
841: );
842:
843: ----------------------------------------------------------------------------
844: -- INT_STAT[OFI]
845: ----------------------------------------------------------------------------
846:
847: int_stat_ofi_reg_comp : memory_reg_os
848: generic map(
849: data_width => 1 ,
850: reset_value => "0"
851: )
852: port map(
853: clk_sys => clk_sys ,-- in
854: res_n => res_n ,-- in
855: data_in => w_data(7 downto 7) ,-- in
856: write => write_en(0) ,-- in
857: cs => reg_sel(4) ,-- in
858: reg_value(0) => control_registers_out_i.int_stat_ofi -- out
859: );
860:
861: ----------------------------------------------------------------------------
862: -- INT_STAT[RXFI]
863: ----------------------------------------------------------------------------
864:
865: int_stat_rxfi_reg_comp : memory_reg_os
866: generic map(
867: data_width => 1 ,
868: reset_value => "0"
869: )
870: port map(
871: clk_sys => clk_sys ,-- in
872: res_n => res_n ,-- in
873: data_in => w_data(8 downto 8) ,-- in
874: write => write_en(1) ,-- in
875: cs => reg_sel(4) ,-- in
876: reg_value(0) => control_registers_out_i.int_stat_rxfi -- out
877: );
878:
879: ----------------------------------------------------------------------------
880: -- INT_STAT[BSI]
881: ----------------------------------------------------------------------------
882:
883: int_stat_bsi_reg_comp : memory_reg_os
884: generic map(
885: data_width => 1 ,
886: reset_value => "0"
887: )
888: port map(
889: clk_sys => clk_sys ,-- in
890: res_n => res_n ,-- in
891: data_in => w_data(9 downto 9) ,-- in
892: write => write_en(1) ,-- in
893: cs => reg_sel(4) ,-- in
894: reg_value(0) => control_registers_out_i.int_stat_bsi -- out
895: );
896:
897: ----------------------------------------------------------------------------
898: -- INT_STAT[RBNEI]
899: ----------------------------------------------------------------------------
900:
901: int_stat_rbnei_reg_comp : memory_reg_os
902: generic map(
903: data_width => 1 ,
904: reset_value => "0"
905: )
906: port map(
907: clk_sys => clk_sys ,-- in
908: res_n => res_n ,-- in
909: data_in => w_data(10 downto 10) ,-- in
910: write => write_en(1) ,-- in
911: cs => reg_sel(4) ,-- in
912: reg_value(0) => control_registers_out_i.int_stat_rbnei -- out
913: );
914:
915: ----------------------------------------------------------------------------
916: -- INT_STAT[TXBHCI]
917: ----------------------------------------------------------------------------
918:
919: int_stat_txbhci_reg_comp : memory_reg_os
920: generic map(
921: data_width => 1 ,
922: reset_value => "0"
923: )
924: port map(
925: clk_sys => clk_sys ,-- in
926: res_n => res_n ,-- in
927: data_in => w_data(11 downto 11) ,-- in
928: write => write_en(1) ,-- in
929: cs => reg_sel(4) ,-- in
930: reg_value(0) => control_registers_out_i.int_stat_txbhci -- out
931: );
932:
933: ----------------------------------------------------------------------------
934: -- INT_ENA_SET[INT_ENA_SET_SLICE_1]
935: ----------------------------------------------------------------------------
936:
937: int_ena_set_int_ena_set_slice_1_reg_comp : memory_reg_os
938: generic map(
939: data_width => 8 ,
940: reset_value => "00000000"
941: )
942: port map(
943: clk_sys => clk_sys ,-- in
944: res_n => res_n ,-- in
945: data_in => w_data(7 downto 0) ,-- in
946: write => write_en(0) ,-- in
947: cs => reg_sel(5) ,-- in
948: reg_value => control_registers_out_i.int_ena_set_int_ena_set(7 downto 0) -- out
949: );
950:
951: ----------------------------------------------------------------------------
952: -- INT_ENA_SET[INT_ENA_SET_SLICE_2]
953: ----------------------------------------------------------------------------
954:
955: int_ena_set_int_ena_set_slice_2_reg_comp : memory_reg_os
956: generic map(
957: data_width => 4 ,
958: reset_value => "0000"
959: )
960: port map(
961: clk_sys => clk_sys ,-- in
962: res_n => res_n ,-- in
963: data_in => w_data(11 downto 8) ,-- in
964: write => write_en(1) ,-- in
965: cs => reg_sel(5) ,-- in
966: reg_value => control_registers_out_i.int_ena_set_int_ena_set(11 downto 8) -- out
967: );
968:
969: ----------------------------------------------------------------------------
970: -- INT_ENA_CLR[INT_ENA_CLR_SLICE_1]
971: ----------------------------------------------------------------------------
972:
973: int_ena_clr_int_ena_clr_slice_1_reg_comp : memory_reg_os
974: generic map(
975: data_width => 8 ,
976: reset_value => "00000000"
977: )
978: port map(
979: clk_sys => clk_sys ,-- in
980: res_n => res_n ,-- in
981: data_in => w_data(7 downto 0) ,-- in
982: write => write_en(0) ,-- in
983: cs => reg_sel(6) ,-- in
984: reg_value => control_registers_out_i.int_ena_clr_int_ena_clr(7 downto 0) -- out
985: );
986:
987: ----------------------------------------------------------------------------
988: -- INT_ENA_CLR[INT_ENA_CLR_SLICE_2]
989: ----------------------------------------------------------------------------
990:
991: int_ena_clr_int_ena_clr_slice_2_reg_comp : memory_reg_os
992: generic map(
993: data_width => 4 ,
994: reset_value => "0000"
995: )
996: port map(
997: clk_sys => clk_sys ,-- in
998: res_n => res_n ,-- in
999: data_in => w_data(11 downto 8) ,-- in
1000: write => write_en(1) ,-- in
1001: cs => reg_sel(6) ,-- in
1002: reg_value => control_registers_out_i.int_ena_clr_int_ena_clr(11 downto 8) -- out
1003: );
1004:
1005: ----------------------------------------------------------------------------
1006: -- INT_MASK_SET[INT_MASK_SET_SLICE_1]
1007: ----------------------------------------------------------------------------
1008:
1009: int_mask_set_int_mask_set_slice_1_reg_comp : memory_reg_os
1010: generic map(
1011: data_width => 8 ,
1012: reset_value => "00000000"
1013: )
1014: port map(
1015: clk_sys => clk_sys ,-- in
1016: res_n => res_n ,-- in
1017: data_in => w_data(7 downto 0) ,-- in
1018: write => write_en(0) ,-- in
1019: cs => reg_sel(7) ,-- in
1020: reg_value => control_registers_out_i.int_mask_set_int_mask_set(7 downto 0) -- out
1021: );
1022:
1023: ----------------------------------------------------------------------------
1024: -- INT_MASK_SET[INT_MASK_SET_SLICE_2]
1025: ----------------------------------------------------------------------------
1026:
1027: int_mask_set_int_mask_set_slice_2_reg_comp : memory_reg_os
1028: generic map(
1029: data_width => 4 ,
1030: reset_value => "0000"
1031: )
1032: port map(
1033: clk_sys => clk_sys ,-- in
1034: res_n => res_n ,-- in
1035: data_in => w_data(11 downto 8) ,-- in
1036: write => write_en(1) ,-- in
1037: cs => reg_sel(7) ,-- in
1038: reg_value => control_registers_out_i.int_mask_set_int_mask_set(11 downto 8) -- out
1039: );
1040:
1041: ----------------------------------------------------------------------------
1042: -- INT_MASK_CLR[INT_MASK_CLR_SLICE_1]
1043: ----------------------------------------------------------------------------
1044:
1045: int_mask_clr_int_mask_clr_slice_1_reg_comp : memory_reg_os
1046: generic map(
1047: data_width => 8 ,
1048: reset_value => "00000000"
1049: )
1050: port map(
1051: clk_sys => clk_sys ,-- in
1052: res_n => res_n ,-- in
1053: data_in => w_data(7 downto 0) ,-- in
1054: write => write_en(0) ,-- in
1055: cs => reg_sel(8) ,-- in
1056: reg_value => control_registers_out_i.int_mask_clr_int_mask_clr(7 downto 0) -- out
1057: );
1058:
1059: ----------------------------------------------------------------------------
1060: -- INT_MASK_CLR[INT_MASK_CLR_SLICE_2]
1061: ----------------------------------------------------------------------------
1062:
1063: int_mask_clr_int_mask_clr_slice_2_reg_comp : memory_reg_os
1064: generic map(
1065: data_width => 4 ,
1066: reset_value => "0000"
1067: )
1068: port map(
1069: clk_sys => clk_sys ,-- in
1070: res_n => res_n ,-- in
1071: data_in => w_data(11 downto 8) ,-- in
1072: write => write_en(1) ,-- in
1073: cs => reg_sel(8) ,-- in
1074: reg_value => control_registers_out_i.int_mask_clr_int_mask_clr(11 downto 8) -- out
1075: );
1076:
1077: ----------------------------------------------------------------------------
1078: -- BTR[PROP]
1079: ----------------------------------------------------------------------------
1080:
1081: btr_prop_reg_comp : memory_reg_rw_lock
1082: generic map(
1083: data_width => 7 ,
1084: reset_value => "0000101"
1085: )
1086: port map(
1087: clk_sys => clk_sys ,-- in
1088: res_n => res_n ,-- in
1089: data_in => w_data(6 downto 0) ,-- in
1090: write => write_en(0) ,-- in
1091: cs => reg_sel(9) ,-- in
1092: lock => lock_2 ,-- in
1093: reg_value => control_registers_out_i.btr_prop -- out
1094: );
1095:
1096: ----------------------------------------------------------------------------
1097: -- BTR[PH1_SLICE_1]
1098: ----------------------------------------------------------------------------
1099:
1100: btr_ph1_slice_1_reg_comp : memory_reg_rw_lock
1101: generic map(
1102: data_width => 1 ,
1103: reset_value => "1"
1104: )
1105: port map(
1106: clk_sys => clk_sys ,-- in
1107: res_n => res_n ,-- in
1108: data_in => w_data(7 downto 7) ,-- in
1109: write => write_en(0) ,-- in
1110: cs => reg_sel(9) ,-- in
1111: lock => lock_2 ,-- in
1112: reg_value(0) => control_registers_out_i.btr_ph1(0) -- out
1113: );
1114:
1115: ----------------------------------------------------------------------------
1116: -- BTR[PH1_SLICE_2]
1117: ----------------------------------------------------------------------------
1118:
1119: btr_ph1_slice_2_reg_comp : memory_reg_rw_lock
1120: generic map(
1121: data_width => 5 ,
1122: reset_value => "00001"
1123: )
1124: port map(
1125: clk_sys => clk_sys ,-- in
1126: res_n => res_n ,-- in
1127: data_in => w_data(12 downto 8) ,-- in
1128: write => write_en(1) ,-- in
1129: cs => reg_sel(9) ,-- in
1130: lock => lock_2 ,-- in
1131: reg_value => control_registers_out_i.btr_ph1(5 downto 1) -- out
1132: );
1133:
1134: ----------------------------------------------------------------------------
1135: -- BTR[PH2_SLICE_1]
1136: ----------------------------------------------------------------------------
1137:
1138: btr_ph2_slice_1_reg_comp : memory_reg_rw_lock
1139: generic map(
1140: data_width => 3 ,
1141: reset_value => "101"
1142: )
1143: port map(
1144: clk_sys => clk_sys ,-- in
1145: res_n => res_n ,-- in
1146: data_in => w_data(15 downto 13) ,-- in
1147: write => write_en(1) ,-- in
1148: cs => reg_sel(9) ,-- in
1149: lock => lock_2 ,-- in
1150: reg_value => control_registers_out_i.btr_ph2(2 downto 0) -- out
1151: );
1152:
1153: ----------------------------------------------------------------------------
1154: -- BTR[PH2_SLICE_2]
1155: ----------------------------------------------------------------------------
1156:
1157: btr_ph2_slice_2_reg_comp : memory_reg_rw_lock
1158: generic map(
1159: data_width => 3 ,
1160: reset_value => "000"
1161: )
1162: port map(
1163: clk_sys => clk_sys ,-- in
1164: res_n => res_n ,-- in
1165: data_in => w_data(18 downto 16) ,-- in
1166: write => write_en(2) ,-- in
1167: cs => reg_sel(9) ,-- in
1168: lock => lock_2 ,-- in
1169: reg_value => control_registers_out_i.btr_ph2(5 downto 3) -- out
1170: );
1171:
1172: ----------------------------------------------------------------------------
1173: -- BTR[BRP_SLICE_1]
1174: ----------------------------------------------------------------------------
1175:
1176: btr_brp_slice_1_reg_comp : memory_reg_rw_lock
1177: generic map(
1178: data_width => 5 ,
1179: reset_value => "01010"
1180: )
1181: port map(
1182: clk_sys => clk_sys ,-- in
1183: res_n => res_n ,-- in
1184: data_in => w_data(23 downto 19) ,-- in
1185: write => write_en(2) ,-- in
1186: cs => reg_sel(9) ,-- in
1187: lock => lock_2 ,-- in
1188: reg_value => control_registers_out_i.btr_brp(4 downto 0) -- out
1189: );
1190:
1191: ----------------------------------------------------------------------------
1192: -- BTR[BRP_SLICE_2]
1193: ----------------------------------------------------------------------------
1194:
1195: btr_brp_slice_2_reg_comp : memory_reg_rw_lock
1196: generic map(
1197: data_width => 3 ,
1198: reset_value => "000"
1199: )
1200: port map(
1201: clk_sys => clk_sys ,-- in
1202: res_n => res_n ,-- in
1203: data_in => w_data(26 downto 24) ,-- in
1204: write => write_en(3) ,-- in
1205: cs => reg_sel(9) ,-- in
1206: lock => lock_2 ,-- in
1207: reg_value => control_registers_out_i.btr_brp(7 downto 5) -- out
1208: );
1209:
1210: ----------------------------------------------------------------------------
1211: -- BTR[SJW]
1212: ----------------------------------------------------------------------------
1213:
1214: btr_sjw_reg_comp : memory_reg_rw_lock
1215: generic map(
1216: data_width => 5 ,
1217: reset_value => "00010"
1218: )
1219: port map(
1220: clk_sys => clk_sys ,-- in
1221: res_n => res_n ,-- in
1222: data_in => w_data(31 downto 27) ,-- in
1223: write => write_en(3) ,-- in
1224: cs => reg_sel(9) ,-- in
1225: lock => lock_2 ,-- in
1226: reg_value => control_registers_out_i.btr_sjw -- out
1227: );
1228:
1229: ----------------------------------------------------------------------------
1230: -- BTR_FD[PROP_FD]
1231: ----------------------------------------------------------------------------
1232:
1233: btr_fd_prop_fd_reg_comp : memory_reg_rw_lock
1234: generic map(
1235: data_width => 6 ,
1236: reset_value => "000011"
1237: )
1238: port map(
1239: clk_sys => clk_sys ,-- in
1240: res_n => res_n ,-- in
1241: data_in => w_data(5 downto 0) ,-- in
1242: write => write_en(0) ,-- in
1243: cs => reg_sel(10) ,-- in
1244: lock => lock_2 ,-- in
1245: reg_value => control_registers_out_i.btr_fd_prop_fd -- out
1246: );
1247:
1248: ----------------------------------------------------------------------------
1249: -- BTR_FD[PH1_FD_SLICE_1]
1250: ----------------------------------------------------------------------------
1251:
1252: btr_fd_ph1_fd_slice_1_reg_comp : memory_reg_rw_lock
1253: generic map(
1254: data_width => 1 ,
1255: reset_value => "1"
1256: )
1257: port map(
1258: clk_sys => clk_sys ,-- in
1259: res_n => res_n ,-- in
1260: data_in => w_data(7 downto 7) ,-- in
1261: write => write_en(0) ,-- in
1262: cs => reg_sel(10) ,-- in
1263: lock => lock_2 ,-- in
1264: reg_value(0) => control_registers_out_i.btr_fd_ph1_fd(0) -- out
1265: );
1266:
1267: ----------------------------------------------------------------------------
1268: -- BTR_FD[PH1_FD_SLICE_2]
1269: ----------------------------------------------------------------------------
1270:
1271: btr_fd_ph1_fd_slice_2_reg_comp : memory_reg_rw_lock
1272: generic map(
1273: data_width => 4 ,
1274: reset_value => "0001"
1275: )
1276: port map(
1277: clk_sys => clk_sys ,-- in
1278: res_n => res_n ,-- in
1279: data_in => w_data(11 downto 8) ,-- in
1280: write => write_en(1) ,-- in
1281: cs => reg_sel(10) ,-- in
1282: lock => lock_2 ,-- in
1283: reg_value => control_registers_out_i.btr_fd_ph1_fd(4 downto 1) -- out
1284: );
1285:
1286: ----------------------------------------------------------------------------
1287: -- BTR_FD[PH2_FD_SLICE_1]
1288: ----------------------------------------------------------------------------
1289:
1290: btr_fd_ph2_fd_slice_1_reg_comp : memory_reg_rw_lock
1291: generic map(
1292: data_width => 3 ,
1293: reset_value => "011"
1294: )
1295: port map(
1296: clk_sys => clk_sys ,-- in
1297: res_n => res_n ,-- in
1298: data_in => w_data(15 downto 13) ,-- in
1299: write => write_en(1) ,-- in
1300: cs => reg_sel(10) ,-- in
1301: lock => lock_2 ,-- in
1302: reg_value => control_registers_out_i.btr_fd_ph2_fd(2 downto 0) -- out
1303: );
1304:
1305: ----------------------------------------------------------------------------
1306: -- BTR_FD[PH2_FD_SLICE_2]
1307: ----------------------------------------------------------------------------
1308:
1309: btr_fd_ph2_fd_slice_2_reg_comp : memory_reg_rw_lock
1310: generic map(
1311: data_width => 2 ,
1312: reset_value => "00"
1313: )
1314: port map(
1315: clk_sys => clk_sys ,-- in
1316: res_n => res_n ,-- in
1317: data_in => w_data(17 downto 16) ,-- in
1318: write => write_en(2) ,-- in
1319: cs => reg_sel(10) ,-- in
1320: lock => lock_2 ,-- in
1321: reg_value => control_registers_out_i.btr_fd_ph2_fd(4 downto 3) -- out
1322: );
1323:
1324: ----------------------------------------------------------------------------
1325: -- BTR_FD[BRP_FD_SLICE_1]
1326: ----------------------------------------------------------------------------
1327:
1328: btr_fd_brp_fd_slice_1_reg_comp : memory_reg_rw_lock
1329: generic map(
1330: data_width => 5 ,
1331: reset_value => "00100"
1332: )
1333: port map(
1334: clk_sys => clk_sys ,-- in
1335: res_n => res_n ,-- in
1336: data_in => w_data(23 downto 19) ,-- in
1337: write => write_en(2) ,-- in
1338: cs => reg_sel(10) ,-- in
1339: lock => lock_2 ,-- in
1340: reg_value => control_registers_out_i.btr_fd_brp_fd(4 downto 0) -- out
1341: );
1342:
1343: ----------------------------------------------------------------------------
1344: -- BTR_FD[BRP_FD_SLICE_2]
1345: ----------------------------------------------------------------------------
1346:
1347: btr_fd_brp_fd_slice_2_reg_comp : memory_reg_rw_lock
1348: generic map(
1349: data_width => 3 ,
1350: reset_value => "000"
1351: )
1352: port map(
1353: clk_sys => clk_sys ,-- in
1354: res_n => res_n ,-- in
1355: data_in => w_data(26 downto 24) ,-- in
1356: write => write_en(3) ,-- in
1357: cs => reg_sel(10) ,-- in
1358: lock => lock_2 ,-- in
1359: reg_value => control_registers_out_i.btr_fd_brp_fd(7 downto 5) -- out
1360: );
1361:
1362: ----------------------------------------------------------------------------
1363: -- BTR_FD[SJW_FD]
1364: ----------------------------------------------------------------------------
1365:
1366: btr_fd_sjw_fd_reg_comp : memory_reg_rw_lock
1367: generic map(
1368: data_width => 5 ,
1369: reset_value => "00010"
1370: )
1371: port map(
1372: clk_sys => clk_sys ,-- in
1373: res_n => res_n ,-- in
1374: data_in => w_data(31 downto 27) ,-- in
1375: write => write_en(3) ,-- in
1376: cs => reg_sel(10) ,-- in
1377: lock => lock_2 ,-- in
1378: reg_value => control_registers_out_i.btr_fd_sjw_fd -- out
1379: );
1380:
1381: ----------------------------------------------------------------------------
1382: -- EWL[EW_LIMIT]
1383: ----------------------------------------------------------------------------
1384:
1385: ewl_ew_limit_reg_comp : memory_reg_rw_lock
1386: generic map(
1387: data_width => 8 ,
1388: reset_value => "01100000"
1389: )
1390: port map(
1391: clk_sys => clk_sys ,-- in
1392: res_n => res_n ,-- in
1393: data_in => w_data(7 downto 0) ,-- in
1394: write => write_en(0) ,-- in
1395: cs => reg_sel(11) ,-- in
1396: lock => lock_1 ,-- in
1397: reg_value => control_registers_out_i.ewl_ew_limit -- out
1398: );
1399:
1400: ----------------------------------------------------------------------------
1401: -- ERP[ERP_LIMIT]
1402: ----------------------------------------------------------------------------
1403:
1404: erp_erp_limit_reg_comp : memory_reg_rw_lock
1405: generic map(
1406: data_width => 8 ,
1407: reset_value => "10000000"
1408: )
1409: port map(
1410: clk_sys => clk_sys ,-- in
1411: res_n => res_n ,-- in
1412: data_in => w_data(15 downto 8) ,-- in
1413: write => write_en(1) ,-- in
1414: cs => reg_sel(11) ,-- in
1415: lock => lock_1 ,-- in
1416: reg_value => control_registers_out_i.erp_erp_limit -- out
1417: );
1418:
1419: ----------------------------------------------------------------------------
1420: -- CTR_PRES[CTPV_SLICE_1]
1421: ----------------------------------------------------------------------------
1422:
1423: ctr_pres_ctpv_slice_1_reg_comp : memory_reg_rw_lock
1424: generic map(
1425: data_width => 8 ,
1426: reset_value => "00000000"
1427: )
1428: port map(
1429: clk_sys => clk_sys ,-- in
1430: res_n => res_n ,-- in
1431: data_in => w_data(7 downto 0) ,-- in
1432: write => write_en(0) ,-- in
1433: cs => reg_sel(14) ,-- in
1434: lock => lock_1 ,-- in
1435: reg_value => control_registers_out_i.ctr_pres_ctpv(7 downto 0) -- out
1436: );
1437:
1438: ----------------------------------------------------------------------------
1439: -- CTR_PRES[CTPV_SLICE_2]
1440: ----------------------------------------------------------------------------
1441:
1442: ctr_pres_ctpv_slice_2_reg_comp : memory_reg_rw_lock
1443: generic map(
1444: data_width => 1 ,
1445: reset_value => "0"
1446: )
1447: port map(
1448: clk_sys => clk_sys ,-- in
1449: res_n => res_n ,-- in
1450: data_in => w_data(8 downto 8) ,-- in
1451: write => write_en(1) ,-- in
1452: cs => reg_sel(14) ,-- in
1453: lock => lock_1 ,-- in
1454: reg_value(0) => control_registers_out_i.ctr_pres_ctpv(8) -- out
1455: );
1456:
1457: ----------------------------------------------------------------------------
1458: -- CTR_PRES[PTX]
1459: ----------------------------------------------------------------------------
1460:
1461: ctr_pres_ptx_reg_comp : memory_reg_os_lock
1462: generic map(
1463: data_width => 1 ,
1464: reset_value => "0"
1465: )
1466: port map(
1467: clk_sys => clk_sys ,-- in
1468: res_n => res_n ,-- in
1469: data_in => w_data(9 downto 9) ,-- in
1470: write => write_en(1) ,-- in
1471: cs => reg_sel(14) ,-- in
1472: lock => lock_1 ,-- in
1473: reg_value(0) => control_registers_out_i.ctr_pres_ptx -- out
1474: );
1475:
1476: ----------------------------------------------------------------------------
1477: -- CTR_PRES[PRX]
1478: ----------------------------------------------------------------------------
1479:
1480: ctr_pres_prx_reg_comp : memory_reg_os_lock
1481: generic map(
1482: data_width => 1 ,
1483: reset_value => "0"
1484: )
1485: port map(
1486: clk_sys => clk_sys ,-- in
1487: res_n => res_n ,-- in
1488: data_in => w_data(10 downto 10) ,-- in
1489: write => write_en(1) ,-- in
1490: cs => reg_sel(14) ,-- in
1491: lock => lock_1 ,-- in
1492: reg_value(0) => control_registers_out_i.ctr_pres_prx -- out
1493: );
1494:
1495: ----------------------------------------------------------------------------
1496: -- CTR_PRES[ENORM]
1497: ----------------------------------------------------------------------------
1498:
1499: ctr_pres_enorm_reg_comp : memory_reg_os_lock
1500: generic map(
1501: data_width => 1 ,
1502: reset_value => "0"
1503: )
1504: port map(
1505: clk_sys => clk_sys ,-- in
1506: res_n => res_n ,-- in
1507: data_in => w_data(11 downto 11) ,-- in
1508: write => write_en(1) ,-- in
1509: cs => reg_sel(14) ,-- in
1510: lock => lock_1 ,-- in
1511: reg_value(0) => control_registers_out_i.ctr_pres_enorm -- out
1512: );
1513:
1514: ----------------------------------------------------------------------------
1515: -- CTR_PRES[EFD]
1516: ----------------------------------------------------------------------------
1517:
1518: ctr_pres_efd_reg_comp : memory_reg_os_lock
1519: generic map(
1520: data_width => 1 ,
1521: reset_value => "0"
1522: )
1523: port map(
1524: clk_sys => clk_sys ,-- in
1525: res_n => res_n ,-- in
1526: data_in => w_data(12 downto 12) ,-- in
1527: write => write_en(1) ,-- in
1528: cs => reg_sel(14) ,-- in
1529: lock => lock_1 ,-- in
1530: reg_value(0) => control_registers_out_i.ctr_pres_efd -- out
1531: );
1532:
1533: FILTER_A_MASK_present_gen_t : if (SUP_FILT_A = true) generate
1534: ----------------------------------------------------------------------------
1535: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_1]
1536: ----------------------------------------------------------------------------
1537:
1538: filter_a_mask_bit_mask_a_val_slice_1_reg_comp : memory_reg_rw
1539: generic map(
1540: data_width => 8 ,
1541: reset_value => "00000000"
1542: )
1543: port map(
1544: clk_sys => clk_sys ,-- in
1545: res_n => res_n ,-- in
1546: data_in => w_data(7 downto 0) ,-- in
1547: write => write_en(0) ,-- in
1548: cs => reg_sel(15) ,-- in
1549: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(7 downto 0) -- out
1550: );
1551:
1552: ----------------------------------------------------------------------------
1553: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_2]
1554: ----------------------------------------------------------------------------
1555:
1556: filter_a_mask_bit_mask_a_val_slice_2_reg_comp : memory_reg_rw
1557: generic map(
1558: data_width => 8 ,
1559: reset_value => "00000000"
1560: )
1561: port map(
1562: clk_sys => clk_sys ,-- in
1563: res_n => res_n ,-- in
1564: data_in => w_data(15 downto 8) ,-- in
1565: write => write_en(1) ,-- in
1566: cs => reg_sel(15) ,-- in
1567: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(15 downto 8) -- out
1568: );
1569:
1570: ----------------------------------------------------------------------------
1571: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_3]
1572: ----------------------------------------------------------------------------
1573:
1574: filter_a_mask_bit_mask_a_val_slice_3_reg_comp : memory_reg_rw
1575: generic map(
1576: data_width => 8 ,
1577: reset_value => "00000000"
1578: )
1579: port map(
1580: clk_sys => clk_sys ,-- in
1581: res_n => res_n ,-- in
1582: data_in => w_data(23 downto 16) ,-- in
1583: write => write_en(2) ,-- in
1584: cs => reg_sel(15) ,-- in
1585: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(23 downto 16) -- out
1586: );
1587:
1588: ----------------------------------------------------------------------------
1589: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_4]
1590: ----------------------------------------------------------------------------
1591:
1592: filter_a_mask_bit_mask_a_val_slice_4_reg_comp : memory_reg_rw
1593: generic map(
1594: data_width => 5 ,
1595: reset_value => "00000"
1596: )
1597: port map(
1598: clk_sys => clk_sys ,-- in
1599: res_n => res_n ,-- in
1600: data_in => w_data(28 downto 24) ,-- in
1601: write => write_en(3) ,-- in
1602: cs => reg_sel(15) ,-- in
1603: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(28 downto 24) -- out
1604: );
1605:
1606: end generate FILTER_A_MASK_present_gen_t;
1607:
1608: FILTER_A_MASK_present_gen_f : if (SUP_FILT_A = false) generate
1609: control_registers_out_i.filter_a_mask_bit_mask_a_val <= (others => '0');
1610: end generate FILTER_A_MASK_present_gen_f;
1611:
1612: FILTER_A_VAL_present_gen_t : if (SUP_FILT_A = true) generate
1613: ----------------------------------------------------------------------------
1614: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_1]
1615: ----------------------------------------------------------------------------
1616:
1617: filter_a_val_bit_val_a_val_slice_1_reg_comp : memory_reg_rw
1618: generic map(
1619: data_width => 8 ,
1620: reset_value => "00000000"
1621: )
1622: port map(
1623: clk_sys => clk_sys ,-- in
1624: res_n => res_n ,-- in
1625: data_in => w_data(7 downto 0) ,-- in
1626: write => write_en(0) ,-- in
1627: cs => reg_sel(16) ,-- in
1628: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(7 downto 0) -- out
1629: );
1630:
1631: ----------------------------------------------------------------------------
1632: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_2]
1633: ----------------------------------------------------------------------------
1634:
1635: filter_a_val_bit_val_a_val_slice_2_reg_comp : memory_reg_rw
1636: generic map(
1637: data_width => 8 ,
1638: reset_value => "00000000"
1639: )
1640: port map(
1641: clk_sys => clk_sys ,-- in
1642: res_n => res_n ,-- in
1643: data_in => w_data(15 downto 8) ,-- in
1644: write => write_en(1) ,-- in
1645: cs => reg_sel(16) ,-- in
1646: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(15 downto 8) -- out
1647: );
1648:
1649: ----------------------------------------------------------------------------
1650: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_3]
1651: ----------------------------------------------------------------------------
1652:
1653: filter_a_val_bit_val_a_val_slice_3_reg_comp : memory_reg_rw
1654: generic map(
1655: data_width => 8 ,
1656: reset_value => "00000000"
1657: )
1658: port map(
1659: clk_sys => clk_sys ,-- in
1660: res_n => res_n ,-- in
1661: data_in => w_data(23 downto 16) ,-- in
1662: write => write_en(2) ,-- in
1663: cs => reg_sel(16) ,-- in
1664: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(23 downto 16) -- out
1665: );
1666:
1667: ----------------------------------------------------------------------------
1668: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_4]
1669: ----------------------------------------------------------------------------
1670:
1671: filter_a_val_bit_val_a_val_slice_4_reg_comp : memory_reg_rw
1672: generic map(
1673: data_width => 5 ,
1674: reset_value => "00000"
1675: )
1676: port map(
1677: clk_sys => clk_sys ,-- in
1678: res_n => res_n ,-- in
1679: data_in => w_data(28 downto 24) ,-- in
1680: write => write_en(3) ,-- in
1681: cs => reg_sel(16) ,-- in
1682: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(28 downto 24) -- out
1683: );
1684:
1685: end generate FILTER_A_VAL_present_gen_t;
1686:
1687: FILTER_A_VAL_present_gen_f : if (SUP_FILT_A = false) generate
1688: control_registers_out_i.filter_a_val_bit_val_a_val <= (others => '0');
1689: end generate FILTER_A_VAL_present_gen_f;
1690:
1691: FILTER_B_MASK_present_gen_t : if (SUP_FILT_B = true) generate
1692: ----------------------------------------------------------------------------
1693: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_1]
1694: ----------------------------------------------------------------------------
1695:
1696: filter_b_mask_bit_mask_b_val_slice_1_reg_comp : memory_reg_rw
1697: generic map(
1698: data_width => 8 ,
1699: reset_value => "00000000"
1700: )
1701: port map(
1702: clk_sys => clk_sys ,-- in
1703: res_n => res_n ,-- in
1704: data_in => w_data(7 downto 0) ,-- in
1705: write => write_en(0) ,-- in
1706: cs => reg_sel(17) ,-- in
1707: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(7 downto 0) -- out
1708: );
1709:
1710: ----------------------------------------------------------------------------
1711: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_2]
1712: ----------------------------------------------------------------------------
1713:
1714: filter_b_mask_bit_mask_b_val_slice_2_reg_comp : memory_reg_rw
1715: generic map(
1716: data_width => 8 ,
1717: reset_value => "00000000"
1718: )
1719: port map(
1720: clk_sys => clk_sys ,-- in
1721: res_n => res_n ,-- in
1722: data_in => w_data(15 downto 8) ,-- in
1723: write => write_en(1) ,-- in
1724: cs => reg_sel(17) ,-- in
1725: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(15 downto 8) -- out
1726: );
1727:
1728: ----------------------------------------------------------------------------
1729: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_3]
1730: ----------------------------------------------------------------------------
1731:
1732: filter_b_mask_bit_mask_b_val_slice_3_reg_comp : memory_reg_rw
1733: generic map(
1734: data_width => 8 ,
1735: reset_value => "00000000"
1736: )
1737: port map(
1738: clk_sys => clk_sys ,-- in
1739: res_n => res_n ,-- in
1740: data_in => w_data(23 downto 16) ,-- in
1741: write => write_en(2) ,-- in
1742: cs => reg_sel(17) ,-- in
1743: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(23 downto 16) -- out
1744: );
1745:
1746: ----------------------------------------------------------------------------
1747: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_4]
1748: ----------------------------------------------------------------------------
1749:
1750: filter_b_mask_bit_mask_b_val_slice_4_reg_comp : memory_reg_rw
1751: generic map(
1752: data_width => 5 ,
1753: reset_value => "00000"
1754: )
1755: port map(
1756: clk_sys => clk_sys ,-- in
1757: res_n => res_n ,-- in
1758: data_in => w_data(28 downto 24) ,-- in
1759: write => write_en(3) ,-- in
1760: cs => reg_sel(17) ,-- in
1761: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(28 downto 24) -- out
1762: );
1763:
1764: end generate FILTER_B_MASK_present_gen_t;
1765:
1766: FILTER_B_MASK_present_gen_f : if (SUP_FILT_B = false) generate
1767: control_registers_out_i.filter_b_mask_bit_mask_b_val <= (others => '0');
1768: end generate FILTER_B_MASK_present_gen_f;
1769:
1770: FILTER_B_VAL_present_gen_t : if (SUP_FILT_B = true) generate
1771: ----------------------------------------------------------------------------
1772: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_1]
1773: ----------------------------------------------------------------------------
1774:
1775: filter_b_val_bit_val_b_val_slice_1_reg_comp : memory_reg_rw
1776: generic map(
1777: data_width => 8 ,
1778: reset_value => "00000000"
1779: )
1780: port map(
1781: clk_sys => clk_sys ,-- in
1782: res_n => res_n ,-- in
1783: data_in => w_data(7 downto 0) ,-- in
1784: write => write_en(0) ,-- in
1785: cs => reg_sel(18) ,-- in
1786: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(7 downto 0) -- out
1787: );
1788:
1789: ----------------------------------------------------------------------------
1790: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_2]
1791: ----------------------------------------------------------------------------
1792:
1793: filter_b_val_bit_val_b_val_slice_2_reg_comp : memory_reg_rw
1794: generic map(
1795: data_width => 8 ,
1796: reset_value => "00000000"
1797: )
1798: port map(
1799: clk_sys => clk_sys ,-- in
1800: res_n => res_n ,-- in
1801: data_in => w_data(15 downto 8) ,-- in
1802: write => write_en(1) ,-- in
1803: cs => reg_sel(18) ,-- in
1804: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(15 downto 8) -- out
1805: );
1806:
1807: ----------------------------------------------------------------------------
1808: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_3]
1809: ----------------------------------------------------------------------------
1810:
1811: filter_b_val_bit_val_b_val_slice_3_reg_comp : memory_reg_rw
1812: generic map(
1813: data_width => 8 ,
1814: reset_value => "00000000"
1815: )
1816: port map(
1817: clk_sys => clk_sys ,-- in
1818: res_n => res_n ,-- in
1819: data_in => w_data(23 downto 16) ,-- in
1820: write => write_en(2) ,-- in
1821: cs => reg_sel(18) ,-- in
1822: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(23 downto 16) -- out
1823: );
1824:
1825: ----------------------------------------------------------------------------
1826: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_4]
1827: ----------------------------------------------------------------------------
1828:
1829: filter_b_val_bit_val_b_val_slice_4_reg_comp : memory_reg_rw
1830: generic map(
1831: data_width => 5 ,
1832: reset_value => "00000"
1833: )
1834: port map(
1835: clk_sys => clk_sys ,-- in
1836: res_n => res_n ,-- in
1837: data_in => w_data(28 downto 24) ,-- in
1838: write => write_en(3) ,-- in
1839: cs => reg_sel(18) ,-- in
1840: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(28 downto 24) -- out
1841: );
1842:
1843: end generate FILTER_B_VAL_present_gen_t;
1844:
1845: FILTER_B_VAL_present_gen_f : if (SUP_FILT_B = false) generate
1846: control_registers_out_i.filter_b_val_bit_val_b_val <= (others => '0');
1847: end generate FILTER_B_VAL_present_gen_f;
1848:
1849: FILTER_C_MASK_present_gen_t : if (SUP_FILT_C = true) generate
1850: ----------------------------------------------------------------------------
1851: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_1]
1852: ----------------------------------------------------------------------------
1853:
1854: filter_c_mask_bit_mask_c_val_slice_1_reg_comp : memory_reg_rw
1855: generic map(
1856: data_width => 8 ,
1857: reset_value => "00000000"
1858: )
1859: port map(
1860: clk_sys => clk_sys ,-- in
1861: res_n => res_n ,-- in
1862: data_in => w_data(7 downto 0) ,-- in
1863: write => write_en(0) ,-- in
1864: cs => reg_sel(19) ,-- in
1865: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(7 downto 0) -- out
1866: );
1867:
1868: ----------------------------------------------------------------------------
1869: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_2]
1870: ----------------------------------------------------------------------------
1871:
1872: filter_c_mask_bit_mask_c_val_slice_2_reg_comp : memory_reg_rw
1873: generic map(
1874: data_width => 8 ,
1875: reset_value => "00000000"
1876: )
1877: port map(
1878: clk_sys => clk_sys ,-- in
1879: res_n => res_n ,-- in
1880: data_in => w_data(15 downto 8) ,-- in
1881: write => write_en(1) ,-- in
1882: cs => reg_sel(19) ,-- in
1883: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(15 downto 8) -- out
1884: );
1885:
1886: ----------------------------------------------------------------------------
1887: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_3]
1888: ----------------------------------------------------------------------------
1889:
1890: filter_c_mask_bit_mask_c_val_slice_3_reg_comp : memory_reg_rw
1891: generic map(
1892: data_width => 8 ,
1893: reset_value => "00000000"
1894: )
1895: port map(
1896: clk_sys => clk_sys ,-- in
1897: res_n => res_n ,-- in
1898: data_in => w_data(23 downto 16) ,-- in
1899: write => write_en(2) ,-- in
1900: cs => reg_sel(19) ,-- in
1901: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(23 downto 16) -- out
1902: );
1903:
1904: ----------------------------------------------------------------------------
1905: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_4]
1906: ----------------------------------------------------------------------------
1907:
1908: filter_c_mask_bit_mask_c_val_slice_4_reg_comp : memory_reg_rw
1909: generic map(
1910: data_width => 5 ,
1911: reset_value => "00000"
1912: )
1913: port map(
1914: clk_sys => clk_sys ,-- in
1915: res_n => res_n ,-- in
1916: data_in => w_data(28 downto 24) ,-- in
1917: write => write_en(3) ,-- in
1918: cs => reg_sel(19) ,-- in
1919: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(28 downto 24) -- out
1920: );
1921:
1922: end generate FILTER_C_MASK_present_gen_t;
1923:
1924: FILTER_C_MASK_present_gen_f : if (SUP_FILT_C = false) generate
1925: control_registers_out_i.filter_c_mask_bit_mask_c_val <= (others => '0');
1926: end generate FILTER_C_MASK_present_gen_f;
1927:
1928: FILTER_C_VAL_present_gen_t : if (SUP_FILT_C = true) generate
1929: ----------------------------------------------------------------------------
1930: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_1]
1931: ----------------------------------------------------------------------------
1932:
1933: filter_c_val_bit_val_c_val_slice_1_reg_comp : memory_reg_rw
1934: generic map(
1935: data_width => 8 ,
1936: reset_value => "00000000"
1937: )
1938: port map(
1939: clk_sys => clk_sys ,-- in
1940: res_n => res_n ,-- in
1941: data_in => w_data(7 downto 0) ,-- in
1942: write => write_en(0) ,-- in
1943: cs => reg_sel(20) ,-- in
1944: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(7 downto 0) -- out
1945: );
1946:
1947: ----------------------------------------------------------------------------
1948: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_2]
1949: ----------------------------------------------------------------------------
1950:
1951: filter_c_val_bit_val_c_val_slice_2_reg_comp : memory_reg_rw
1952: generic map(
1953: data_width => 8 ,
1954: reset_value => "00000000"
1955: )
1956: port map(
1957: clk_sys => clk_sys ,-- in
1958: res_n => res_n ,-- in
1959: data_in => w_data(15 downto 8) ,-- in
1960: write => write_en(1) ,-- in
1961: cs => reg_sel(20) ,-- in
1962: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(15 downto 8) -- out
1963: );
1964:
1965: ----------------------------------------------------------------------------
1966: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_3]
1967: ----------------------------------------------------------------------------
1968:
1969: filter_c_val_bit_val_c_val_slice_3_reg_comp : memory_reg_rw
1970: generic map(
1971: data_width => 8 ,
1972: reset_value => "00000000"
1973: )
1974: port map(
1975: clk_sys => clk_sys ,-- in
1976: res_n => res_n ,-- in
1977: data_in => w_data(23 downto 16) ,-- in
1978: write => write_en(2) ,-- in
1979: cs => reg_sel(20) ,-- in
1980: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(23 downto 16) -- out
1981: );
1982:
1983: ----------------------------------------------------------------------------
1984: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_4]
1985: ----------------------------------------------------------------------------
1986:
1987: filter_c_val_bit_val_c_val_slice_4_reg_comp : memory_reg_rw
1988: generic map(
1989: data_width => 5 ,
1990: reset_value => "00000"
1991: )
1992: port map(
1993: clk_sys => clk_sys ,-- in
1994: res_n => res_n ,-- in
1995: data_in => w_data(28 downto 24) ,-- in
1996: write => write_en(3) ,-- in
1997: cs => reg_sel(20) ,-- in
1998: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(28 downto 24) -- out
1999: );
2000:
2001: end generate FILTER_C_VAL_present_gen_t;
2002:
2003: FILTER_C_VAL_present_gen_f : if (SUP_FILT_C = false) generate
2004: control_registers_out_i.filter_c_val_bit_val_c_val <= (others => '0');
2005: end generate FILTER_C_VAL_present_gen_f;
2006:
2007: FILTER_RAN_LOW_present_gen_t : if (SUP_RANGE = true) generate
2008: ----------------------------------------------------------------------------
2009: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_1]
2010: ----------------------------------------------------------------------------
2011:
2012: filter_ran_low_bit_ran_low_val_slice_1_reg_comp : memory_reg_rw
2013: generic map(
2014: data_width => 8 ,
2015: reset_value => "00000000"
2016: )
2017: port map(
2018: clk_sys => clk_sys ,-- in
2019: res_n => res_n ,-- in
2020: data_in => w_data(7 downto 0) ,-- in
2021: write => write_en(0) ,-- in
2022: cs => reg_sel(21) ,-- in
2023: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(7 downto 0) -- out
2024: );
2025:
2026: ----------------------------------------------------------------------------
2027: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_2]
2028: ----------------------------------------------------------------------------
2029:
2030: filter_ran_low_bit_ran_low_val_slice_2_reg_comp : memory_reg_rw
2031: generic map(
2032: data_width => 8 ,
2033: reset_value => "00000000"
2034: )
2035: port map(
2036: clk_sys => clk_sys ,-- in
2037: res_n => res_n ,-- in
2038: data_in => w_data(15 downto 8) ,-- in
2039: write => write_en(1) ,-- in
2040: cs => reg_sel(21) ,-- in
2041: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(15 downto 8) -- out
2042: );
2043:
2044: ----------------------------------------------------------------------------
2045: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_3]
2046: ----------------------------------------------------------------------------
2047:
2048: filter_ran_low_bit_ran_low_val_slice_3_reg_comp : memory_reg_rw
2049: generic map(
2050: data_width => 8 ,
2051: reset_value => "00000000"
2052: )
2053: port map(
2054: clk_sys => clk_sys ,-- in
2055: res_n => res_n ,-- in
2056: data_in => w_data(23 downto 16) ,-- in
2057: write => write_en(2) ,-- in
2058: cs => reg_sel(21) ,-- in
2059: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(23 downto 16) -- out
2060: );
2061:
2062: ----------------------------------------------------------------------------
2063: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_4]
2064: ----------------------------------------------------------------------------
2065:
2066: filter_ran_low_bit_ran_low_val_slice_4_reg_comp : memory_reg_rw
2067: generic map(
2068: data_width => 5 ,
2069: reset_value => "00000"
2070: )
2071: port map(
2072: clk_sys => clk_sys ,-- in
2073: res_n => res_n ,-- in
2074: data_in => w_data(28 downto 24) ,-- in
2075: write => write_en(3) ,-- in
2076: cs => reg_sel(21) ,-- in
2077: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(28 downto 24) -- out
2078: );
2079:
2080: end generate FILTER_RAN_LOW_present_gen_t;
2081:
2082: FILTER_RAN_LOW_present_gen_f : if (SUP_RANGE = false) generate
2083: control_registers_out_i.filter_ran_low_bit_ran_low_val <= (others => '0');
2084: end generate FILTER_RAN_LOW_present_gen_f;
2085:
2086: FILTER_RAN_HIGH_present_gen_t : if (SUP_RANGE = true) generate
2087: ----------------------------------------------------------------------------
2088: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_1]
2089: ----------------------------------------------------------------------------
2090:
2091: filter_ran_high_bit_ran_high_val_slice_1_reg_comp : memory_reg_rw
2092: generic map(
2093: data_width => 8 ,
2094: reset_value => "00000000"
2095: )
2096: port map(
2097: clk_sys => clk_sys ,-- in
2098: res_n => res_n ,-- in
2099: data_in => w_data(7 downto 0) ,-- in
2100: write => write_en(0) ,-- in
2101: cs => reg_sel(22) ,-- in
2102: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(7 downto 0) -- out
2103: );
2104:
2105: ----------------------------------------------------------------------------
2106: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_2]
2107: ----------------------------------------------------------------------------
2108:
2109: filter_ran_high_bit_ran_high_val_slice_2_reg_comp : memory_reg_rw
2110: generic map(
2111: data_width => 8 ,
2112: reset_value => "00000000"
2113: )
2114: port map(
2115: clk_sys => clk_sys ,-- in
2116: res_n => res_n ,-- in
2117: data_in => w_data(15 downto 8) ,-- in
2118: write => write_en(1) ,-- in
2119: cs => reg_sel(22) ,-- in
2120: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(15 downto 8) -- out
2121: );
2122:
2123: ----------------------------------------------------------------------------
2124: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_3]
2125: ----------------------------------------------------------------------------
2126:
2127: filter_ran_high_bit_ran_high_val_slice_3_reg_comp : memory_reg_rw
2128: generic map(
2129: data_width => 8 ,
2130: reset_value => "00000000"
2131: )
2132: port map(
2133: clk_sys => clk_sys ,-- in
2134: res_n => res_n ,-- in
2135: data_in => w_data(23 downto 16) ,-- in
2136: write => write_en(2) ,-- in
2137: cs => reg_sel(22) ,-- in
2138: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(23 downto 16) -- out
2139: );
2140:
2141: ----------------------------------------------------------------------------
2142: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_4]
2143: ----------------------------------------------------------------------------
2144:
2145: filter_ran_high_bit_ran_high_val_slice_4_reg_comp : memory_reg_rw
2146: generic map(
2147: data_width => 5 ,
2148: reset_value => "00000"
2149: )
2150: port map(
2151: clk_sys => clk_sys ,-- in
2152: res_n => res_n ,-- in
2153: data_in => w_data(28 downto 24) ,-- in
2154: write => write_en(3) ,-- in
2155: cs => reg_sel(22) ,-- in
2156: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(28 downto 24) -- out
2157: );
2158:
2159: end generate FILTER_RAN_HIGH_present_gen_t;
2160:
2161: FILTER_RAN_HIGH_present_gen_f : if (SUP_RANGE = false) generate
2162: control_registers_out_i.filter_ran_high_bit_ran_high_val <= (others => '0');
2163: end generate FILTER_RAN_HIGH_present_gen_f;
2164:
2165: ----------------------------------------------------------------------------
2166: -- FILTER_CONTROL[FANB]
2167: ----------------------------------------------------------------------------
2168:
2169: filter_control_fanb_reg_comp : memory_reg_rw
2170: generic map(
2171: data_width => 1 ,
2172: reset_value => "1"
2173: )
2174: port map(
2175: clk_sys => clk_sys ,-- in
2176: res_n => res_n ,-- in
2177: data_in => w_data(0 downto 0) ,-- in
2178: write => write_en(0) ,-- in
2179: cs => reg_sel(23) ,-- in
2180: reg_value(0) => control_registers_out_i.filter_control_fanb -- out
2181: );
2182:
2183: ----------------------------------------------------------------------------
2184: -- FILTER_CONTROL[FANE]
2185: ----------------------------------------------------------------------------
2186:
2187: filter_control_fane_reg_comp : memory_reg_rw
2188: generic map(
2189: data_width => 1 ,
2190: reset_value => "1"
2191: )
2192: port map(
2193: clk_sys => clk_sys ,-- in
2194: res_n => res_n ,-- in
2195: data_in => w_data(1 downto 1) ,-- in
2196: write => write_en(0) ,-- in
2197: cs => reg_sel(23) ,-- in
2198: reg_value(0) => control_registers_out_i.filter_control_fane -- out
2199: );
2200:
2201: ----------------------------------------------------------------------------
2202: -- FILTER_CONTROL[FAFB]
2203: ----------------------------------------------------------------------------
2204:
2205: filter_control_fafb_reg_comp : memory_reg_rw
2206: generic map(
2207: data_width => 1 ,
2208: reset_value => "1"
2209: )
2210: port map(
2211: clk_sys => clk_sys ,-- in
2212: res_n => res_n ,-- in
2213: data_in => w_data(2 downto 2) ,-- in
2214: write => write_en(0) ,-- in
2215: cs => reg_sel(23) ,-- in
2216: reg_value(0) => control_registers_out_i.filter_control_fafb -- out
2217: );
2218:
2219: ----------------------------------------------------------------------------
2220: -- FILTER_CONTROL[FAFE]
2221: ----------------------------------------------------------------------------
2222:
2223: filter_control_fafe_reg_comp : memory_reg_rw
2224: generic map(
2225: data_width => 1 ,
2226: reset_value => "1"
2227: )
2228: port map(
2229: clk_sys => clk_sys ,-- in
2230: res_n => res_n ,-- in
2231: data_in => w_data(3 downto 3) ,-- in
2232: write => write_en(0) ,-- in
2233: cs => reg_sel(23) ,-- in
2234: reg_value(0) => control_registers_out_i.filter_control_fafe -- out
2235: );
2236:
2237: ----------------------------------------------------------------------------
2238: -- FILTER_CONTROL[FBNB]
2239: ----------------------------------------------------------------------------
2240:
2241: filter_control_fbnb_reg_comp : memory_reg_rw
2242: generic map(
2243: data_width => 1 ,
2244: reset_value => "0"
2245: )
2246: port map(
2247: clk_sys => clk_sys ,-- in
2248: res_n => res_n ,-- in
2249: data_in => w_data(4 downto 4) ,-- in
2250: write => write_en(0) ,-- in
2251: cs => reg_sel(23) ,-- in
2252: reg_value(0) => control_registers_out_i.filter_control_fbnb -- out
2253: );
2254:
2255: ----------------------------------------------------------------------------
2256: -- FILTER_CONTROL[FBNE]
2257: ----------------------------------------------------------------------------
2258:
2259: filter_control_fbne_reg_comp : memory_reg_rw
2260: generic map(
2261: data_width => 1 ,
2262: reset_value => "0"
2263: )
2264: port map(
2265: clk_sys => clk_sys ,-- in
2266: res_n => res_n ,-- in
2267: data_in => w_data(5 downto 5) ,-- in
2268: write => write_en(0) ,-- in
2269: cs => reg_sel(23) ,-- in
2270: reg_value(0) => control_registers_out_i.filter_control_fbne -- out
2271: );
2272:
2273: ----------------------------------------------------------------------------
2274: -- FILTER_CONTROL[FBFB]
2275: ----------------------------------------------------------------------------
2276:
2277: filter_control_fbfb_reg_comp : memory_reg_rw
2278: generic map(
2279: data_width => 1 ,
2280: reset_value => "0"
2281: )
2282: port map(
2283: clk_sys => clk_sys ,-- in
2284: res_n => res_n ,-- in
2285: data_in => w_data(6 downto 6) ,-- in
2286: write => write_en(0) ,-- in
2287: cs => reg_sel(23) ,-- in
2288: reg_value(0) => control_registers_out_i.filter_control_fbfb -- out
2289: );
2290:
2291: ----------------------------------------------------------------------------
2292: -- FILTER_CONTROL[FBFE]
2293: ----------------------------------------------------------------------------
2294:
2295: filter_control_fbfe_reg_comp : memory_reg_rw
2296: generic map(
2297: data_width => 1 ,
2298: reset_value => "0"
2299: )
2300: port map(
2301: clk_sys => clk_sys ,-- in
2302: res_n => res_n ,-- in
2303: data_in => w_data(7 downto 7) ,-- in
2304: write => write_en(0) ,-- in
2305: cs => reg_sel(23) ,-- in
2306: reg_value(0) => control_registers_out_i.filter_control_fbfe -- out
2307: );
2308:
2309: ----------------------------------------------------------------------------
2310: -- FILTER_CONTROL[FCNB]
2311: ----------------------------------------------------------------------------
2312:
2313: filter_control_fcnb_reg_comp : memory_reg_rw
2314: generic map(
2315: data_width => 1 ,
2316: reset_value => "0"
2317: )
2318: port map(
2319: clk_sys => clk_sys ,-- in
2320: res_n => res_n ,-- in
2321: data_in => w_data(8 downto 8) ,-- in
2322: write => write_en(1) ,-- in
2323: cs => reg_sel(23) ,-- in
2324: reg_value(0) => control_registers_out_i.filter_control_fcnb -- out
2325: );
2326:
2327: ----------------------------------------------------------------------------
2328: -- FILTER_CONTROL[FCNE]
2329: ----------------------------------------------------------------------------
2330:
2331: filter_control_fcne_reg_comp : memory_reg_rw
2332: generic map(
2333: data_width => 1 ,
2334: reset_value => "0"
2335: )
2336: port map(
2337: clk_sys => clk_sys ,-- in
2338: res_n => res_n ,-- in
2339: data_in => w_data(9 downto 9) ,-- in
2340: write => write_en(1) ,-- in
2341: cs => reg_sel(23) ,-- in
2342: reg_value(0) => control_registers_out_i.filter_control_fcne -- out
2343: );
2344:
2345: ----------------------------------------------------------------------------
2346: -- FILTER_CONTROL[FCFB]
2347: ----------------------------------------------------------------------------
2348:
2349: filter_control_fcfb_reg_comp : memory_reg_rw
2350: generic map(
2351: data_width => 1 ,
2352: reset_value => "0"
2353: )
2354: port map(
2355: clk_sys => clk_sys ,-- in
2356: res_n => res_n ,-- in
2357: data_in => w_data(10 downto 10) ,-- in
2358: write => write_en(1) ,-- in
2359: cs => reg_sel(23) ,-- in
2360: reg_value(0) => control_registers_out_i.filter_control_fcfb -- out
2361: );
2362:
2363: ----------------------------------------------------------------------------
2364: -- FILTER_CONTROL[FCFE]
2365: ----------------------------------------------------------------------------
2366:
2367: filter_control_fcfe_reg_comp : memory_reg_rw
2368: generic map(
2369: data_width => 1 ,
2370: reset_value => "0"
2371: )
2372: port map(
2373: clk_sys => clk_sys ,-- in
2374: res_n => res_n ,-- in
2375: data_in => w_data(11 downto 11) ,-- in
2376: write => write_en(1) ,-- in
2377: cs => reg_sel(23) ,-- in
2378: reg_value(0) => control_registers_out_i.filter_control_fcfe -- out
2379: );
2380:
2381: ----------------------------------------------------------------------------
2382: -- FILTER_CONTROL[FRNB]
2383: ----------------------------------------------------------------------------
2384:
2385: filter_control_frnb_reg_comp : memory_reg_rw
2386: generic map(
2387: data_width => 1 ,
2388: reset_value => "0"
2389: )
2390: port map(
2391: clk_sys => clk_sys ,-- in
2392: res_n => res_n ,-- in
2393: data_in => w_data(12 downto 12) ,-- in
2394: write => write_en(1) ,-- in
2395: cs => reg_sel(23) ,-- in
2396: reg_value(0) => control_registers_out_i.filter_control_frnb -- out
2397: );
2398:
2399: ----------------------------------------------------------------------------
2400: -- FILTER_CONTROL[FRNE]
2401: ----------------------------------------------------------------------------
2402:
2403: filter_control_frne_reg_comp : memory_reg_rw
2404: generic map(
2405: data_width => 1 ,
2406: reset_value => "0"
2407: )
2408: port map(
2409: clk_sys => clk_sys ,-- in
2410: res_n => res_n ,-- in
2411: data_in => w_data(13 downto 13) ,-- in
2412: write => write_en(1) ,-- in
2413: cs => reg_sel(23) ,-- in
2414: reg_value(0) => control_registers_out_i.filter_control_frne -- out
2415: );
2416:
2417: ----------------------------------------------------------------------------
2418: -- FILTER_CONTROL[FRFB]
2419: ----------------------------------------------------------------------------
2420:
2421: filter_control_frfb_reg_comp : memory_reg_rw
2422: generic map(
2423: data_width => 1 ,
2424: reset_value => "0"
2425: )
2426: port map(
2427: clk_sys => clk_sys ,-- in
2428: res_n => res_n ,-- in
2429: data_in => w_data(14 downto 14) ,-- in
2430: write => write_en(1) ,-- in
2431: cs => reg_sel(23) ,-- in
2432: reg_value(0) => control_registers_out_i.filter_control_frfb -- out
2433: );
2434:
2435: ----------------------------------------------------------------------------
2436: -- FILTER_CONTROL[FRFE]
2437: ----------------------------------------------------------------------------
2438:
2439: filter_control_frfe_reg_comp : memory_reg_rw
2440: generic map(
2441: data_width => 1 ,
2442: reset_value => "0"
2443: )
2444: port map(
2445: clk_sys => clk_sys ,-- in
2446: res_n => res_n ,-- in
2447: data_in => w_data(15 downto 15) ,-- in
2448: write => write_en(1) ,-- in
2449: cs => reg_sel(23) ,-- in
2450: reg_value(0) => control_registers_out_i.filter_control_frfe -- out
2451: );
2452:
2453: ----------------------------------------------------------------------------
2454: -- RX_SETTINGS[RTSOP]
2455: ----------------------------------------------------------------------------
2456:
2457: rx_settings_rtsop_reg_comp : memory_reg_rw
2458: generic map(
2459: data_width => 1 ,
2460: reset_value => "0"
2461: )
2462: port map(
2463: clk_sys => clk_sys ,-- in
2464: res_n => res_n ,-- in
2465: data_in => w_data(16 downto 16) ,-- in
2466: write => write_en(2) ,-- in
2467: cs => reg_sel(26) ,-- in
2468: reg_value(0) => control_registers_out_i.rx_settings_rtsop -- out
2469: );
2470:
2471: ----------------------------------------------------------------------------
2472: -- RX_DATA access signallization
2473: ----------------------------------------------------------------------------
2474:
2475: rx_data_access_signaller_comp : read_access_signaller
2476: generic map(
2477: data_width => 32
2478: )
2479: port map(
2480: clk_sys => clk_sys ,-- in
2481: res_n => res_n ,-- in
2482: cs => reg_sel(27) ,-- in
2483: read => read ,-- in
2484: be => be(3 downto 0) ,-- in
2485: read_signal => control_registers_out_i.rx_data_read -- out
2486: );
2487:
2488: ----------------------------------------------------------------------------
2489: -- TX_COMMAND[TXCE]
2490: ----------------------------------------------------------------------------
2491:
2492: tx_command_txce_reg_comp : memory_reg_os
2493: generic map(
2494: data_width => 1 ,
2495: reset_value => "0"
2496: )
2497: port map(
2498: clk_sys => clk_sys ,-- in
2499: res_n => res_n ,-- in
2500: data_in => w_data(0 downto 0) ,-- in
2501: write => write_en(0) ,-- in
2502: cs => reg_sel(29) ,-- in
2503: reg_value(0) => control_registers_out_i.tx_command_txce -- out
2504: );
2505:
2506: ----------------------------------------------------------------------------
2507: -- TX_COMMAND[TXCR]
2508: ----------------------------------------------------------------------------
2509:
2510: tx_command_txcr_reg_comp : memory_reg_os
2511: generic map(
2512: data_width => 1 ,
2513: reset_value => "0"
2514: )
2515: port map(
2516: clk_sys => clk_sys ,-- in
2517: res_n => res_n ,-- in
2518: data_in => w_data(1 downto 1) ,-- in
2519: write => write_en(0) ,-- in
2520: cs => reg_sel(29) ,-- in
2521: reg_value(0) => control_registers_out_i.tx_command_txcr -- out
2522: );
2523:
2524: ----------------------------------------------------------------------------
2525: -- TX_COMMAND[TXCA]
2526: ----------------------------------------------------------------------------
2527:
2528: tx_command_txca_reg_comp : memory_reg_os
2529: generic map(
2530: data_width => 1 ,
2531: reset_value => "0"
2532: )
2533: port map(
2534: clk_sys => clk_sys ,-- in
2535: res_n => res_n ,-- in
2536: data_in => w_data(2 downto 2) ,-- in
2537: write => write_en(0) ,-- in
2538: cs => reg_sel(29) ,-- in
2539: reg_value(0) => control_registers_out_i.tx_command_txca -- out
2540: );
2541:
2542: ----------------------------------------------------------------------------
2543: -- TX_COMMAND[TXB1]
2544: ----------------------------------------------------------------------------
2545:
2546: tx_command_txb1_reg_comp : memory_reg_rw
2547: generic map(
2548: data_width => 1 ,
2549: reset_value => "0"
2550: )
2551: port map(
2552: clk_sys => clk_sys ,-- in
2553: res_n => res_n ,-- in
2554: data_in => w_data(8 downto 8) ,-- in
2555: write => write_en(1) ,-- in
2556: cs => reg_sel(29) ,-- in
2557: reg_value(0) => control_registers_out_i.tx_command_txb1 -- out
2558: );
2559:
2560: ----------------------------------------------------------------------------
2561: -- TX_COMMAND[TXB2]
2562: ----------------------------------------------------------------------------
2563:
2564: tx_command_txb2_reg_comp : memory_reg_rw
2565: generic map(
2566: data_width => 1 ,
2567: reset_value => "0"
2568: )
2569: port map(
2570: clk_sys => clk_sys ,-- in
2571: res_n => res_n ,-- in
2572: data_in => w_data(9 downto 9) ,-- in
2573: write => write_en(1) ,-- in
2574: cs => reg_sel(29) ,-- in
2575: reg_value(0) => control_registers_out_i.tx_command_txb2 -- out
2576: );
2577:
2578: ----------------------------------------------------------------------------
2579: -- TX_COMMAND[TXB3]
2580: ----------------------------------------------------------------------------
2581:
2582: tx_command_txb3_reg_comp : memory_reg_rw
2583: generic map(
2584: data_width => 1 ,
2585: reset_value => "0"
2586: )
2587: port map(
2588: clk_sys => clk_sys ,-- in
2589: res_n => res_n ,-- in
2590: data_in => w_data(10 downto 10) ,-- in
2591: write => write_en(1) ,-- in
2592: cs => reg_sel(29) ,-- in
2593: reg_value(0) => control_registers_out_i.tx_command_txb3 -- out
2594: );
2595:
2596: ----------------------------------------------------------------------------
2597: -- TX_COMMAND[TXB4]
2598: ----------------------------------------------------------------------------
2599:
2600: tx_command_txb4_reg_comp : memory_reg_rw
2601: generic map(
2602: data_width => 1 ,
2603: reset_value => "0"
2604: )
2605: port map(
2606: clk_sys => clk_sys ,-- in
2607: res_n => res_n ,-- in
2608: data_in => w_data(11 downto 11) ,-- in
2609: write => write_en(1) ,-- in
2610: cs => reg_sel(29) ,-- in
2611: reg_value(0) => control_registers_out_i.tx_command_txb4 -- out
2612: );
2613:
2614: ----------------------------------------------------------------------------
2615: -- TX_COMMAND[TXB5]
2616: ----------------------------------------------------------------------------
2617:
2618: tx_command_txb5_reg_comp : memory_reg_rw
2619: generic map(
2620: data_width => 1 ,
2621: reset_value => "0"
2622: )
2623: port map(
2624: clk_sys => clk_sys ,-- in
2625: res_n => res_n ,-- in
2626: data_in => w_data(12 downto 12) ,-- in
2627: write => write_en(1) ,-- in
2628: cs => reg_sel(29) ,-- in
2629: reg_value(0) => control_registers_out_i.tx_command_txb5 -- out
2630: );
2631:
2632: ----------------------------------------------------------------------------
2633: -- TX_COMMAND[TXB6]
2634: ----------------------------------------------------------------------------
2635:
2636: tx_command_txb6_reg_comp : memory_reg_rw
2637: generic map(
2638: data_width => 1 ,
2639: reset_value => "0"
2640: )
2641: port map(
2642: clk_sys => clk_sys ,-- in
2643: res_n => res_n ,-- in
2644: data_in => w_data(13 downto 13) ,-- in
2645: write => write_en(1) ,-- in
2646: cs => reg_sel(29) ,-- in
2647: reg_value(0) => control_registers_out_i.tx_command_txb6 -- out
2648: );
2649:
2650: ----------------------------------------------------------------------------
2651: -- TX_COMMAND[TXB7]
2652: ----------------------------------------------------------------------------
2653:
2654: tx_command_txb7_reg_comp : memory_reg_rw
2655: generic map(
2656: data_width => 1 ,
2657: reset_value => "0"
2658: )
2659: port map(
2660: clk_sys => clk_sys ,-- in
2661: res_n => res_n ,-- in
2662: data_in => w_data(14 downto 14) ,-- in
2663: write => write_en(1) ,-- in
2664: cs => reg_sel(29) ,-- in
2665: reg_value(0) => control_registers_out_i.tx_command_txb7 -- out
2666: );
2667:
2668: ----------------------------------------------------------------------------
2669: -- TX_COMMAND[TXB8]
2670: ----------------------------------------------------------------------------
2671:
2672: tx_command_txb8_reg_comp : memory_reg_rw
2673: generic map(
2674: data_width => 1 ,
2675: reset_value => "0"
2676: )
2677: port map(
2678: clk_sys => clk_sys ,-- in
2679: res_n => res_n ,-- in
2680: data_in => w_data(15 downto 15) ,-- in
2681: write => write_en(1) ,-- in
2682: cs => reg_sel(29) ,-- in
2683: reg_value(0) => control_registers_out_i.tx_command_txb8 -- out
2684: );
2685:
2686: ----------------------------------------------------------------------------
2687: -- TX_PRIORITY[TXT1P]
2688: ----------------------------------------------------------------------------
2689:
2690: tx_priority_txt1p_reg_comp : memory_reg_rw
2691: generic map(
2692: data_width => 3 ,
2693: reset_value => "001"
2694: )
2695: port map(
2696: clk_sys => clk_sys ,-- in
2697: res_n => res_n ,-- in
2698: data_in => w_data(2 downto 0) ,-- in
2699: write => write_en(0) ,-- in
2700: cs => reg_sel(30) ,-- in
2701: reg_value => control_registers_out_i.tx_priority_txt1p -- out
2702: );
2703:
2704: ----------------------------------------------------------------------------
2705: -- TX_PRIORITY[TXT2P]
2706: ----------------------------------------------------------------------------
2707:
2708: tx_priority_txt2p_reg_comp : memory_reg_rw
2709: generic map(
2710: data_width => 3 ,
2711: reset_value => "000"
2712: )
2713: port map(
2714: clk_sys => clk_sys ,-- in
2715: res_n => res_n ,-- in
2716: data_in => w_data(6 downto 4) ,-- in
2717: write => write_en(0) ,-- in
2718: cs => reg_sel(30) ,-- in
2719: reg_value => control_registers_out_i.tx_priority_txt2p -- out
2720: );
2721:
2722: ----------------------------------------------------------------------------
2723: -- TX_PRIORITY[TXT3P]
2724: ----------------------------------------------------------------------------
2725:
2726: tx_priority_txt3p_reg_comp : memory_reg_rw
2727: generic map(
2728: data_width => 3 ,
2729: reset_value => "000"
2730: )
2731: port map(
2732: clk_sys => clk_sys ,-- in
2733: res_n => res_n ,-- in
2734: data_in => w_data(10 downto 8) ,-- in
2735: write => write_en(1) ,-- in
2736: cs => reg_sel(30) ,-- in
2737: reg_value => control_registers_out_i.tx_priority_txt3p -- out
2738: );
2739:
2740: ----------------------------------------------------------------------------
2741: -- TX_PRIORITY[TXT4P]
2742: ----------------------------------------------------------------------------
2743:
2744: tx_priority_txt4p_reg_comp : memory_reg_rw
2745: generic map(
2746: data_width => 3 ,
2747: reset_value => "000"
2748: )
2749: port map(
2750: clk_sys => clk_sys ,-- in
2751: res_n => res_n ,-- in
2752: data_in => w_data(14 downto 12) ,-- in
2753: write => write_en(1) ,-- in
2754: cs => reg_sel(30) ,-- in
2755: reg_value => control_registers_out_i.tx_priority_txt4p -- out
2756: );
2757:
2758: ----------------------------------------------------------------------------
2759: -- TX_PRIORITY[TXT5P]
2760: ----------------------------------------------------------------------------
2761:
2762: tx_priority_txt5p_reg_comp : memory_reg_rw
2763: generic map(
2764: data_width => 3 ,
2765: reset_value => "000"
2766: )
2767: port map(
2768: clk_sys => clk_sys ,-- in
2769: res_n => res_n ,-- in
2770: data_in => w_data(18 downto 16) ,-- in
2771: write => write_en(2) ,-- in
2772: cs => reg_sel(30) ,-- in
2773: reg_value => control_registers_out_i.tx_priority_txt5p -- out
2774: );
2775:
2776: ----------------------------------------------------------------------------
2777: -- TX_PRIORITY[TXT6P]
2778: ----------------------------------------------------------------------------
2779:
2780: tx_priority_txt6p_reg_comp : memory_reg_rw
2781: generic map(
2782: data_width => 3 ,
2783: reset_value => "000"
2784: )
2785: port map(
2786: clk_sys => clk_sys ,-- in
2787: res_n => res_n ,-- in
2788: data_in => w_data(22 downto 20) ,-- in
2789: write => write_en(2) ,-- in
2790: cs => reg_sel(30) ,-- in
2791: reg_value => control_registers_out_i.tx_priority_txt6p -- out
2792: );
2793:
2794: ----------------------------------------------------------------------------
2795: -- TX_PRIORITY[TXT7P]
2796: ----------------------------------------------------------------------------
2797:
2798: tx_priority_txt7p_reg_comp : memory_reg_rw
2799: generic map(
2800: data_width => 3 ,
2801: reset_value => "000"
2802: )
2803: port map(
2804: clk_sys => clk_sys ,-- in
2805: res_n => res_n ,-- in
2806: data_in => w_data(26 downto 24) ,-- in
2807: write => write_en(3) ,-- in
2808: cs => reg_sel(30) ,-- in
2809: reg_value => control_registers_out_i.tx_priority_txt7p -- out
2810: );
2811:
2812: ----------------------------------------------------------------------------
2813: -- TX_PRIORITY[TXT8P]
2814: ----------------------------------------------------------------------------
2815:
2816: tx_priority_txt8p_reg_comp : memory_reg_rw
2817: generic map(
2818: data_width => 3 ,
2819: reset_value => "000"
2820: )
2821: port map(
2822: clk_sys => clk_sys ,-- in
2823: res_n => res_n ,-- in
2824: data_in => w_data(30 downto 28) ,-- in
2825: write => write_en(3) ,-- in
2826: cs => reg_sel(30) ,-- in
2827: reg_value => control_registers_out_i.tx_priority_txt8p -- out
2828: );
2829:
2830: ----------------------------------------------------------------------------
2831: -- SSP_CFG[SSP_OFFSET]
2832: ----------------------------------------------------------------------------
2833:
2834: ssp_cfg_ssp_offset_reg_comp : memory_reg_rw_lock
2835: generic map(
2836: data_width => 8 ,
2837: reset_value => "00001010"
2838: )
2839: port map(
2840: clk_sys => clk_sys ,-- in
2841: res_n => res_n ,-- in
2842: data_in => w_data(23 downto 16) ,-- in
2843: write => write_en(2) ,-- in
2844: cs => reg_sel(32) ,-- in
2845: lock => lock_2 ,-- in
2846: reg_value => control_registers_out_i.ssp_cfg_ssp_offset -- out
2847: );
2848:
2849: ----------------------------------------------------------------------------
2850: -- SSP_CFG[SSP_SRC]
2851: ----------------------------------------------------------------------------
2852:
2853: ssp_cfg_ssp_src_reg_comp : memory_reg_rw_lock
2854: generic map(
2855: data_width => 2 ,
2856: reset_value => "00"
2857: )
2858: port map(
2859: clk_sys => clk_sys ,-- in
2860: res_n => res_n ,-- in
2861: data_in => w_data(25 downto 24) ,-- in
2862: write => write_en(3) ,-- in
2863: cs => reg_sel(32) ,-- in
2864: lock => lock_2 ,-- in
2865: reg_value => control_registers_out_i.ssp_cfg_ssp_src -- out
2866: );
2867:
2868: ----------------------------------------------------------------------------
2869: -- Read data multiplexor
2870: ----------------------------------------------------------------------------
2871: with address(7 downto 2) select r_data_comb <=
2872: control_registers_in.version_ver_major &
2873: control_registers_in.version_ver_minor &
2874: control_registers_in.device_id_device_id when "000000",
2875: '0' & '0' & '0' & '0' &
2876: control_registers_out_i.settings_pchke &
2877: control_registers_out_i.settings_fdrf &
2878: control_registers_out_i.settings_tbfbo &
2879: control_registers_out_i.settings_pex &
2880: control_registers_out_i.settings_nisofd &
2881: control_registers_out_i.settings_ena &
2882: control_registers_out_i.settings_ilbp &
2883: control_registers_out_i.settings_rtrth &
2884: control_registers_out_i.settings_rtrle &
2885: '0' & '0' & '0' &
2886: control_registers_out_i.mode_erfm &
2887: control_registers_out_i.mode_sam &
2888: control_registers_out_i.mode_txbbm &
2889: control_registers_out_i.mode_rxbam &
2890: control_registers_out_i.mode_tstm &
2891: control_registers_out_i.mode_acf &
2892: control_registers_out_i.mode_rom &
2893: control_registers_out_i.mode_tttm &
2894: control_registers_out_i.mode_fde &
2895: control_registers_out_i.mode_afm &
2896: control_registers_out_i.mode_stm &
2897: control_registers_out_i.mode_bmm &
2898: control_registers_out_i.mode_rst when "000001",
2899: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2900: control_registers_in.status_sprt &
2901: control_registers_in.status_strgs &
2902: control_registers_in.status_stcnt &
2903: '0' & '0' & '0' & '0' &
2904: control_registers_in.status_txdpe &
2905: control_registers_in.status_txpe &
2906: control_registers_in.status_rxpe &
2907: control_registers_in.status_pexs &
2908: control_registers_in.status_idle &
2909: control_registers_in.status_ewl &
2910: control_registers_in.status_txs &
2911: control_registers_in.status_rxs &
2912: control_registers_in.status_eft &
2913: control_registers_in.status_txnf &
2914: control_registers_in.status_dor &
2915: control_registers_in.status_rxne when "000010",
2916: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000011",
2917: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2918: control_registers_in.int_stat_txbhci &
2919: control_registers_in.int_stat_rbnei &
2920: control_registers_in.int_stat_bsi &
2921: control_registers_in.int_stat_rxfi &
2922: control_registers_in.int_stat_ofi &
2923: control_registers_in.int_stat_bei &
2924: control_registers_in.int_stat_ali &
2925: control_registers_in.int_stat_fcsi &
2926: control_registers_in.int_stat_doi &
2927: control_registers_in.int_stat_ewli &
2928: control_registers_in.int_stat_txi &
2929: control_registers_in.int_stat_rxi when "000100",
2930: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2931: control_registers_in.int_ena_set_int_ena_set when "000101",
2932: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000110",
2933: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2934: control_registers_in.int_mask_set_int_mask_set when "000111",
2935: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001000",
2936: control_registers_out_i.btr_sjw &
2937: control_registers_out_i.btr_brp &
2938: control_registers_out_i.btr_ph2 &
2939: control_registers_out_i.btr_ph1 &
2940: control_registers_out_i.btr_prop when "001001",
2941: control_registers_out_i.btr_fd_sjw_fd &
2942: control_registers_out_i.btr_fd_brp_fd &
2943: '0' &
2944: control_registers_out_i.btr_fd_ph2_fd &
2945: '0' &
2946: control_registers_out_i.btr_fd_ph1_fd &
2947: '0' &
2948: control_registers_out_i.btr_fd_prop_fd when "001010",
2949: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2950: control_registers_in.fault_state_bof &
2951: control_registers_in.fault_state_erp &
2952: control_registers_in.fault_state_era &
2953: control_registers_out_i.erp_erp_limit &
2954: control_registers_out_i.ewl_ew_limit when "001011",
2955: '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2956: control_registers_in.tec_tec_val &
2957: '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2958: control_registers_in.rec_rec_val when "001100",
2959: control_registers_in.err_fd_err_fd_val &
2960: control_registers_in.err_norm_err_norm_val when "001101",
2961: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001110",
2962: '0' & '0' & '0' &
2963: control_registers_out_i.filter_a_mask_bit_mask_a_val when "001111",
2964: '0' & '0' & '0' &
2965: control_registers_out_i.filter_a_val_bit_val_a_val when "010000",
2966: '0' & '0' & '0' &
2967: control_registers_out_i.filter_b_mask_bit_mask_b_val when "010001",
2968: '0' & '0' & '0' &
2969: control_registers_out_i.filter_b_val_bit_val_b_val when "010010",
2970: '0' & '0' & '0' &
2971: control_registers_out_i.filter_c_mask_bit_mask_c_val when "010011",
2972: '0' & '0' & '0' &
2973: control_registers_out_i.filter_c_val_bit_val_c_val when "010100",
2974: '0' & '0' & '0' &
2975: control_registers_out_i.filter_ran_low_bit_ran_low_val when "010101",
2976: '0' & '0' & '0' &
2977: control_registers_out_i.filter_ran_high_bit_ran_high_val when "010110",
2978: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2979: control_registers_in.filter_status_sfr &
2980: control_registers_in.filter_status_sfc &
2981: control_registers_in.filter_status_sfb &
2982: control_registers_in.filter_status_sfa &
2983: control_registers_out_i.filter_control_frfe &
2984: control_registers_out_i.filter_control_frfb &
2985: control_registers_out_i.filter_control_frne &
2986: control_registers_out_i.filter_control_frnb &
2987: control_registers_out_i.filter_control_fcfe &
2988: control_registers_out_i.filter_control_fcfb &
2989: control_registers_out_i.filter_control_fcne &
2990: control_registers_out_i.filter_control_fcnb &
2991: control_registers_out_i.filter_control_fbfe &
2992: control_registers_out_i.filter_control_fbfb &
2993: control_registers_out_i.filter_control_fbne &
2994: control_registers_out_i.filter_control_fbnb &
2995: control_registers_out_i.filter_control_fafe &
2996: control_registers_out_i.filter_control_fafb &
2997: control_registers_out_i.filter_control_fane &
2998: control_registers_out_i.filter_control_fanb when "010111",
2999: '0' & '0' & '0' &
3000: control_registers_in.rx_mem_info_rx_mem_free &
3001: '0' & '0' & '0' &
3002: control_registers_in.rx_mem_info_rx_buff_size when "011000",
3003: '0' & '0' & '0' & '0' &
3004: control_registers_in.rx_pointers_rx_rpp &
3005: '0' & '0' & '0' & '0' &
3006: control_registers_in.rx_pointers_rx_wpp when "011001",
3007: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3008: control_registers_out_i.rx_settings_rtsop &
3009: '0' &
3010: control_registers_in.rx_status_rxfrc &
3011: '0' &
3012: control_registers_in.rx_status_rxmof &
3013: control_registers_in.rx_status_rxf &
3014: control_registers_in.rx_status_rxe when "011010",
3015: control_registers_in.rx_data_rx_data when "011011",
3016: control_registers_in.tx_status_tx8s &
3017: control_registers_in.tx_status_tx7s &
3018: control_registers_in.tx_status_tx6s &
3019: control_registers_in.tx_status_tx5s &
3020: control_registers_in.tx_status_tx4s &
3021: control_registers_in.tx_status_tx3s &
3022: control_registers_in.tx_status_tx2s &
3023: control_registers_in.tx_status_tx1s when "011100",
3024: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3025: control_registers_in.txtb_info_txt_buffer_count &
3026: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "011101",
3027: '0' &
3028: control_registers_out_i.tx_priority_txt8p &
3029: '0' &
3030: control_registers_out_i.tx_priority_txt7p &
3031: '0' &
3032: control_registers_out_i.tx_priority_txt6p &
3033: '0' &
3034: control_registers_out_i.tx_priority_txt5p &
3035: '0' &
3036: control_registers_out_i.tx_priority_txt4p &
3037: '0' &
3038: control_registers_out_i.tx_priority_txt3p &
3039: '0' &
3040: control_registers_out_i.tx_priority_txt2p &
3041: '0' &
3042: control_registers_out_i.tx_priority_txt1p when "011110",
3043: '0' & '0' &
3044: control_registers_in.ts_info_ts_bits &
3045: control_registers_in.alc_alc_id_field &
3046: control_registers_in.alc_alc_bit &
3047: '0' & '0' & '0' & '0' &
3048: control_registers_in.retr_ctr_retr_ctr_val &
3049: control_registers_in.err_capt_err_type &
3050: control_registers_in.err_capt_err_erp &
3051: control_registers_in.err_capt_err_pos when "011111",
3052: '0' & '0' & '0' & '0' & '0' & '0' &
3053: control_registers_out_i.ssp_cfg_ssp_src &
3054: control_registers_out_i.ssp_cfg_ssp_offset &
3055: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3056: control_registers_in.trv_delay_trv_delay_value when "100000",
3057: control_registers_in.rx_fr_ctr_rx_fr_ctr_val when "100001",
3058: control_registers_in.tx_fr_ctr_tx_fr_ctr_val when "100010",
3059: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3060: control_registers_in.debug_register_pc_sof &
3061: control_registers_in.debug_register_pc_ovr &
3062: control_registers_in.debug_register_pc_susp &
3063: control_registers_in.debug_register_pc_int &
3064: control_registers_in.debug_register_pc_eof &
3065: control_registers_in.debug_register_pc_ackd &
3066: control_registers_in.debug_register_pc_ack &
3067: control_registers_in.debug_register_pc_crcd &
3068: control_registers_in.debug_register_pc_crc &
3069: control_registers_in.debug_register_pc_stc &
3070: control_registers_in.debug_register_pc_dat &
3071: control_registers_in.debug_register_pc_con &
3072: control_registers_in.debug_register_pc_arb &
3073: control_registers_in.debug_register_destuff_count &
3074: control_registers_in.debug_register_stuff_count when "100011",
3075: control_registers_in.yolo_reg_yolo_val when "100100",
3076: control_registers_in.timestamp_low_timestamp_low when "100101",
3077: control_registers_in.timestamp_high_timestamp_high when "100110",
3078: (others => '0') when others;
3079:
3080: ----------------------------------------------------------------------------
3081: -- Output register
3082: ----------------------------------------------------------------------------
3083: read_data_reg_proc : process(res_n, clk_sys)
3084: begin
3085: if (res_n = '0') then
3086: r_data <= (others => '0');
3087: elsif (rising_edge(clk_sys)) then
3088: if (cs = '1' and read = '1') then
3089: r_data <= r_data_comb and read_data_mask_n;
3090: end if;
3091: end if;
3092: end process;
3093:
3094: ----------------------------------------------------------------------------
3095: -- Read data mask - Byte enables
3096: ----------------------------------------------------------------------------
3097: read_data_mask_n <=
3098: be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &
3099: be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &
3100: be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &
3101: be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;
3102:
3103: Control_registers_out <= Control_registers_out_i;
3104:
3105: -- <RELEASE_OFF>
3106: ----------------------------------------------------------------------------
3107: -- Functional coverage
3108: ----------------------------------------------------------------------------
3109: -- psl default clock is rising_edge(clk_sys);
3110: -- psl device_id_read_access_cov : cover
3111: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1')))};
3112:
3113: -- psl version_read_access_cov : cover
3114: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(2)='1') or (be(3)='1')))};
3115:
3116: -- psl mode_write_access_cov : cover
3117: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};
3118:
3119: -- psl mode_read_access_cov : cover
3120: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};
3121:
3122: -- psl settings_write_access_cov : cover
3123: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};
3124:
3125: -- psl settings_read_access_cov : cover
3126: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};
3127:
3128: -- psl status_read_access_cov : cover
3129: -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3130:
3131: -- psl command_write_access_cov : cover
3132: -- {((cs='1') and (write='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3133:
3134: -- psl int_stat_write_access_cov : cover
3135: -- {((cs='1') and (write='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};
3136:
3137: -- psl int_stat_read_access_cov : cover
3138: -- {((cs='1') and (read='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};
3139:
3140: -- psl int_ena_set_write_access_cov : cover
3141: -- {((cs='1') and (write='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};
3142:
3143: -- psl int_ena_set_read_access_cov : cover
3144: -- {((cs='1') and (read='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};
3145:
3146: -- psl int_ena_clr_write_access_cov : cover
3147: -- {((cs='1') and (write='1') and (reg_sel(6)='1') and ((be(0)='1') or (be(1)='1')))};
3148:
3149: -- psl int_mask_set_write_access_cov : cover
3150: -- {((cs='1') and (write='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};
3151:
3152: -- psl int_mask_set_read_access_cov : cover
3153: -- {((cs='1') and (read='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};
3154:
3155: -- psl int_mask_clr_write_access_cov : cover
3156: -- {((cs='1') and (write='1') and (reg_sel(8)='1') and ((be(0)='1') or (be(1)='1')))};
3157:
3158: -- psl btr_write_access_cov : cover
3159: -- {((cs='1') and (write='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3160:
3161: -- psl btr_read_access_cov : cover
3162: -- {((cs='1') and (read='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3163:
3164: -- psl btr_fd_write_access_cov : cover
3165: -- {((cs='1') and (write='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3166:
3167: -- psl btr_fd_read_access_cov : cover
3168: -- {((cs='1') and (read='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3169:
3170: -- psl ewl_write_access_cov : cover
3171: -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(0)='1')))};
3172:
3173: -- psl ewl_read_access_cov : cover
3174: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(0)='1')))};
3175:
3176: -- psl erp_write_access_cov : cover
3177: -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(1)='1')))};
3178:
3179: -- psl erp_read_access_cov : cover
3180: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(1)='1')))};
3181:
3182: -- psl fault_state_read_access_cov : cover
3183: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(2)='1') or (be(3)='1')))};
3184:
3185: -- psl rec_read_access_cov : cover
3186: -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(0)='1') or (be(1)='1')))};
3187:
3188: -- psl tec_read_access_cov : cover
3189: -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(2)='1') or (be(3)='1')))};
3190:
3191: -- psl err_norm_read_access_cov : cover
3192: -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(0)='1') or (be(1)='1')))};
3193:
3194: -- psl err_fd_read_access_cov : cover
3195: -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(2)='1') or (be(3)='1')))};
3196:
3197: -- psl ctr_pres_write_access_cov : cover
3198: -- {((cs='1') and (write='1') and (reg_sel(14)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3199:
3200: -- psl filter_a_mask_write_access_cov : cover
3201: -- {((cs='1') and (write='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3202:
3203: -- psl filter_a_mask_read_access_cov : cover
3204: -- {((cs='1') and (read='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3205:
3206: -- psl filter_a_val_write_access_cov : cover
3207: -- {((cs='1') and (write='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3208:
3209: -- psl filter_a_val_read_access_cov : cover
3210: -- {((cs='1') and (read='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3211:
3212: -- psl filter_b_mask_write_access_cov : cover
3213: -- {((cs='1') and (write='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3214:
3215: -- psl filter_b_mask_read_access_cov : cover
3216: -- {((cs='1') and (read='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3217:
3218: -- psl filter_b_val_write_access_cov : cover
3219: -- {((cs='1') and (write='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3220:
3221: -- psl filter_b_val_read_access_cov : cover
3222: -- {((cs='1') and (read='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3223:
3224: -- psl filter_c_mask_write_access_cov : cover
3225: -- {((cs='1') and (write='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3226:
3227: -- psl filter_c_mask_read_access_cov : cover
3228: -- {((cs='1') and (read='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3229:
3230: -- psl filter_c_val_write_access_cov : cover
3231: -- {((cs='1') and (write='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3232:
3233: -- psl filter_c_val_read_access_cov : cover
3234: -- {((cs='1') and (read='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3235:
3236: -- psl filter_ran_low_write_access_cov : cover
3237: -- {((cs='1') and (write='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3238:
3239: -- psl filter_ran_low_read_access_cov : cover
3240: -- {((cs='1') and (read='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3241:
3242: -- psl filter_ran_high_write_access_cov : cover
3243: -- {((cs='1') and (write='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3244:
3245: -- psl filter_ran_high_read_access_cov : cover
3246: -- {((cs='1') and (read='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3247:
3248: -- psl filter_control_write_access_cov : cover
3249: -- {((cs='1') and (write='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))};
3250:
3251: -- psl filter_control_read_access_cov : cover
3252: -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))};
3253:
3254: -- psl filter_status_read_access_cov : cover
3255: -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(2)='1') or (be(3)='1')))};
3256:
3257: -- psl rx_mem_info_read_access_cov : cover
3258: -- {((cs='1') and (read='1') and (reg_sel(24)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3259:
3260: -- psl rx_pointers_read_access_cov : cover
3261: -- {((cs='1') and (read='1') and (reg_sel(25)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3262:
3263: -- psl rx_status_read_access_cov : cover
3264: -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(0)='1') or (be(1)='1')))};
3265:
3266: -- psl rx_settings_write_access_cov : cover
3267: -- {((cs='1') and (write='1') and (reg_sel(26)='1') and ((be(2)='1')))};
3268:
3269: -- psl rx_settings_read_access_cov : cover
3270: -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(2)='1')))};
3271:
3272: -- psl rx_data_read_access_cov : cover
3273: -- {((cs='1') and (read='1') and (reg_sel(27)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3274:
3275: -- psl tx_status_read_access_cov : cover
3276: -- {((cs='1') and (read='1') and (reg_sel(28)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3277:
3278: -- psl tx_command_write_access_cov : cover
3279: -- {((cs='1') and (write='1') and (reg_sel(29)='1') and ((be(0)='1') or (be(1)='1')))};
3280:
3281: -- psl txtb_info_read_access_cov : cover
3282: -- {((cs='1') and (read='1') and (reg_sel(29)='1') and ((be(2)='1') or (be(3)='1')))};
3283:
3284: -- psl tx_priority_write_access_cov : cover
3285: -- {((cs='1') and (write='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3286:
3287: -- psl tx_priority_read_access_cov : cover
3288: -- {((cs='1') and (read='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3289:
3290: -- psl err_capt_read_access_cov : cover
3291: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(0)='1')))};
3292:
3293: -- psl retr_ctr_read_access_cov : cover
3294: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(1)='1')))};
3295:
3296: -- psl alc_read_access_cov : cover
3297: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(2)='1')))};
3298:
3299: -- psl ts_info_read_access_cov : cover
3300: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(3)='1')))};
3301:
3302: -- psl trv_delay_read_access_cov : cover
3303: -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(0)='1') or (be(1)='1')))};
3304:
3305: -- psl ssp_cfg_write_access_cov : cover
3306: -- {((cs='1') and (write='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))};
3307:
3308: -- psl ssp_cfg_read_access_cov : cover
3309: -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))};
3310:
3311: -- psl rx_fr_ctr_read_access_cov : cover
3312: -- {((cs='1') and (read='1') and (reg_sel(33)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3313:
3314: -- psl tx_fr_ctr_read_access_cov : cover
3315: -- {((cs='1') and (read='1') and (reg_sel(34)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3316:
3317: -- psl debug_register_read_access_cov : cover
3318: -- {((cs='1') and (read='1') and (reg_sel(35)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3319:
3320: -- psl yolo_reg_read_access_cov : cover
3321: -- {((cs='1') and (read='1') and (reg_sel(36)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3322:
3323: -- psl timestamp_low_read_access_cov : cover
3324: -- {((cs='1') and (read='1') and (reg_sel(37)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3325:
3326: -- psl timestamp_high_read_access_cov : cover
3327: -- {((cs='1') and (read='1') and (reg_sel(38)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3328:
3329: -- <RELEASE_ON>
3330:
3331: end architecture rtl;