NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_POINTERS_INST	100.0 % (59/59)	100.0 % (60/60)	100.0 % (468/468)	100.0 % (55/55)	N.A.	N.A.	100.0 % (642/642)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

214: read_pointer <= std_logic_vector(read_pointer_i);
Count: 55635
Threshold: 1

Signal assignment statement:

215: read_pointer_inc_1 <= std_logic_vector(read_pointer_inc_1_i);
Count: 57235
Threshold: 1

Signal assignment statement:

216: write_pointer <= std_logic_vector(write_pointer_i);
Count: 17679
Threshold: 1

Signal assignment statement:

217: write_pointer_raw <= std_logic_vector(write_pointer_raw_i);
Count: 210640
Threshold: 1

Signal assignment statement:

218: write_pointer_ts <= std_logic_vector(write_pointer_ts_i);
Count: 30718
Threshold: 1

Signal assignment statement:

219: rx_mem_free_i <= std_logic_vector(rx_mem_free_i_i);
Count: 68530
Threshold: 1

If statement:

221:    abort_applied <= '1' when (rec_abort_f = '1' or commit_overrun_abort = '1') 
222:                         else 
223:                     '0';

Count: 66536
Threshold: 1

Signal assignment statement:

221: abort_applied <= '1' when (rec_abort_f = '1' or commit_overrun_abort = '1')
Count: 30868
Threshold: 1

Signal assignment statement:

223: '0';
Count: 35668
Threshold: 1

If statement:

231:        if (rx_buf_res_n_q_scan = '0') then 
232:            read_pointer_i <= (others => '0'); 
...
236:            end if; 
237:        end if;

Count: 1055177794
Threshold: 1

Signal assignment statement:

232: read_pointer_i <= (others => '0');
Count: 2432531
Threshold: 1

If statement:

234:            if (read_increment = '1') then 
235:                read_pointer_i <= read_pointer_inc_1_i; 
236:            end if;

Count: 526367462
Threshold: 1

Signal assignment statement:

235: read_pointer_i <= read_pointer_inc_1_i;
Count: 51619
Threshold: 1

If statement:

246:        if (rx_buf_res_n_q_scan = '0') then 
247:            write_pointer_i <= (others => '0'); 
...
251:            end if; 
252:        end if;

Count: 1055177794
Threshold: 1

Signal assignment statement:

247: write_pointer_i <= (others => '0');
Count: 2432531
Threshold: 1

If statement:

249:            if (commit_rx_frame = '1') then 
250:                write_pointer_i <= write_pointer_raw_i; 
251:            end if;

Count: 526367462
Threshold: 1

Signal assignment statement:

250: write_pointer_i <= write_pointer_raw_i;
Count: 13310
Threshold: 1

If statement:

262:    write_pointer_raw_d <= write_pointer_raw_i + 1 when (write_raw_OK = '1') 
263:                                                   else 
264:                                   write_pointer_i;

Count: 451568
Threshold: 1

Signal assignment statement:

262: write_pointer_raw_d <= write_pointer_raw_i + 1 when (write_raw_OK = '1')
Count: 305943
Threshold: 1

Signal assignment statement:

264: write_pointer_i;
Count: 145625
Threshold: 1

If statement:

266:    write_pointer_raw_ce <= '1' when (write_raw_OK = '1') else 
267:                            '1' when (rec_abort_f = '1') else 
268:                            '1' when (commit_overrun_abort = '1') else 
269:                            '0';

Count: 292554
Threshold: 1

Signal assignment statement:

266: write_pointer_raw_ce <= '1' when (write_raw_OK = '1') else
Count: 113014
Threshold: 1

Signal assignment statement:

267: '1' when (rec_abort_f = '1') else
Count: 30827
Threshold: 1

Signal assignment statement:

268: '1' when (commit_overrun_abort = '1') else
Count: 48
Threshold: 1

Signal assignment statement:

269: '0';
Count: 148665
Threshold: 1

If statement:

273:        if (rx_buf_res_n_q_scan = '0') then 
274:           write_pointer_raw_i <= (others => '0'); 
...
278:            end if; 
279:        end if;

Count: 1055177794
Threshold: 1

Signal assignment statement:

274: write_pointer_raw_i <= (others => '0');
Count: 2432531
Threshold: 1

If statement:

276:            if (write_pointer_raw_ce = '1') then 
277:                write_pointer_raw_i <= write_pointer_raw_d; 
278:            end if;

Count: 526367462
Threshold: 1

Signal assignment statement:

277: write_pointer_raw_i <= write_pointer_raw_d;
Count: 223802
Threshold: 1

If statement:

286:    write_pointer_ts_d <= write_pointer_raw_i when (store_ts_wr_ptr = '1') 
287:                                              else 
288:                          write_pointer_ts_i + 1;

Count: 278216
Threshold: 1

Signal assignment statement:

286: write_pointer_ts_d <= write_pointer_raw_i when (store_ts_wr_ptr = '1')
Count: 52702
Threshold: 1

Signal assignment statement:

288: write_pointer_ts_i + 1;
Count: 225514
Threshold: 1

If statement:

291:    write_pointer_ts_ce <= '1' when (store_ts_wr_ptr = '1') else 
292:                           '1' when (inc_ts_wr_ptr = '1') else 
293:                           '0';

Count: 81944
Threshold: 1

Signal assignment statement:

291: write_pointer_ts_ce <= '1' when (store_ts_wr_ptr = '1') else
Count: 26351
Threshold: 1

Signal assignment statement:

292: '1' when (inc_ts_wr_ptr = '1') else
Count: 13021
Threshold: 1

Signal assignment statement:

293: '0';
Count: 42572
Threshold: 1

If statement:

297:        if (rx_buf_res_n_q_scan = '0') then 
298:            write_pointer_ts_i  <= (others => '0'); 
...
302:            end if; 
303:        end if;

Count: 1055177794
Threshold: 1

Signal assignment statement:

298: write_pointer_ts_i <= (others => '0');
Count: 2432531
Threshold: 1

If statement:

300:            if (write_pointer_ts_ce = '1') then 
301:                write_pointer_ts_i <= write_pointer_ts_d; 
302:            end if;

Count: 526367462
Threshold: 1

Signal assignment statement:

301: write_pointer_ts_i <= write_pointer_ts_d;
Count: 39372
Threshold: 1

If statement:

312:        if (rx_buf_res_n_q_scan = '0') then 
313:            rx_mem_free_i_i <= to_unsigned(G_RX_BUFF_SIZE, C_FREE_MEM_WIDTH); 
...
363: 
364:        end if;

Count: 1055177794
Threshold: 1

Signal assignment statement:

313: rx_mem_free_i_i <= to_unsigned(G_RX_BUFF_SIZE, C_FREE_MEM_WIDTH);
Count: 2432531
Threshold: 1

Signal assignment statement:

314: rx_mem_free_raw <= to_unsigned(G_RX_BUFF_SIZE, C_FREE_MEM_WIDTH);
Count: 2432531
Threshold: 1

If statement:

321:            if (read_increment = '1') then 
322: 
...
345:                end if; 
346:            end if;

Count: 526367462
Threshold: 1

If statement:

325:                if (abort_applied = '1') then 
326:                    rx_mem_free_raw <= rx_mem_free_i_inc_1; 
...
333:                -- rx_mem_free_raw remains unchanged. 
334:                end if;

Count: 51619
Threshold: 1

Signal assignment statement:

326: rx_mem_free_raw <= rx_mem_free_i_inc_1;
Count: 20
Threshold: 1

Signal assignment statement:

330: rx_mem_free_raw <= rx_mem_free_raw_inc_1;
Count: 51535
Threshold: 1

If statement:

339:                if (abort_applied = '1') then 
340:                    rx_mem_free_raw <= rx_mem_free_i_i; 
...
344:                    rx_mem_free_raw <= rx_mem_free_raw_dec_1; 
345:                end if;

Count: 526315843
Threshold: 1

Signal assignment statement:

340: rx_mem_free_raw <= rx_mem_free_i_i;
Count: 30848
Threshold: 1

Signal assignment statement:

344: rx_mem_free_raw <= rx_mem_free_raw_dec_1;
Count: 192870
Threshold: 1

If statement:

353:            if (read_increment = '1') then 
354:                if (commit_rx_frame = '1') then 
...
361:                rx_mem_free_i_i <= rx_mem_free_raw; 
362:            end if;

Count: 526367462
Threshold: 1

If statement:

354:                if (commit_rx_frame = '1') then 
355:                    rx_mem_free_i_i <= rx_mem_free_raw_inc_1; 
356:                else 
357:                    rx_mem_free_i_i <= rx_mem_free_i_inc_1; 
358:                end if;

Count: 51619
Threshold: 1

Signal assignment statement:

355: rx_mem_free_i_i <= rx_mem_free_raw_inc_1;
Count: 27
Threshold: 1

Signal assignment statement:

357: rx_mem_free_i_i <= rx_mem_free_i_inc_1;
Count: 51592
Threshold: 1

Signal assignment statement:

361: rx_mem_free_i_i <= rx_mem_free_raw;
Count: 13283
Threshold: 1

Signal assignment statement:

373: rx_mem_free_i_inc_1 <= rx_mem_free_i_i + 1;
Count: 274717
Threshold: 1

Signal assignment statement:

374: rx_mem_free_raw_inc_1 <= rx_mem_free_raw + 1;
Count: 274717
Threshold: 1

Signal assignment statement:

375: rx_mem_free_raw_dec_1 <= rx_mem_free_raw - 1;
Count: 274717
Threshold: 1

Signal assignment statement:

386: read_pointer_inc_1_i <= read_pointer_i + 1;
Count: 55635
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

221: abort_applied <= '1' when (rec_abort_f = '1' or commit_overrun_abort = '1')

	Evaluated to	Count	Threshold
Bin	True	30868	1
Bin	False	35668	1

"if" / "when" / "else" condition:

231: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2432531	1
Bin	False	1052745263	1

"if" / "when" / "else" condition:

233: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526367462	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

234: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	True	51619	1
Bin	False	526315843	1

"if" / "when" / "else" condition:

246: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2432531	1
Bin	False	1052745263	1

"if" / "when" / "else" condition:

248: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526367462	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

249: if (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	True	13310	1
Bin	False	526354152	1

"if" / "when" / "else" condition:

262: write_pointer_raw_d <= write_pointer_raw_i + 1 when (write_raw_OK = '1')

	Evaluated to	Count	Threshold
Bin	True	305943	1
Bin	False	145625	1

"if" / "when" / "else" condition:

266: write_pointer_raw_ce <= '1' when (write_raw_OK = '1') else

	Evaluated to	Count	Threshold
Bin	True	113014	1
Bin	False	179540	1

"if" / "when" / "else" condition:

267: '1' when (rec_abort_f = '1') else

	Evaluated to	Count	Threshold
Bin	True	30827	1
Bin	False	148713	1

"if" / "when" / "else" condition:

268: '1' when (commit_overrun_abort = '1') else

	Evaluated to	Count	Threshold
Bin	True	48	1
Bin	False	148665	1

"if" / "when" / "else" condition:

273: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2432531	1
Bin	False	1052745263	1

"if" / "when" / "else" condition:

275: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526367462	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

276: if (write_pointer_raw_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	223802	1
Bin	False	526143660	1

"if" / "when" / "else" condition:

286: write_pointer_ts_d <= write_pointer_raw_i when (store_ts_wr_ptr = '1')

	Evaluated to	Count	Threshold
Bin	True	52702	1
Bin	False	225514	1

"if" / "when" / "else" condition:

291: write_pointer_ts_ce <= '1' when (store_ts_wr_ptr = '1') else

	Evaluated to	Count	Threshold
Bin	True	26351	1
Bin	False	55593	1

"if" / "when" / "else" condition:

292: '1' when (inc_ts_wr_ptr = '1') else

	Evaluated to	Count	Threshold
Bin	True	13021	1
Bin	False	42572	1

"if" / "when" / "else" condition:

297: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2432531	1
Bin	False	1052745263	1

"if" / "when" / "else" condition:

299: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526367462	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

300: if (write_pointer_ts_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	39372	1
Bin	False	526328090	1

"if" / "when" / "else" condition:

312: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2432531	1
Bin	False	1052745263	1

"if" / "when" / "else" condition:

316: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526367462	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

321: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	True	51619	1
Bin	False	526315843	1

"if" / "when" / "else" condition:

325: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	51599	1

"if" / "when" / "else" condition:

329: elsif (write_raw_OK = '0') then

	Evaluated to	Count	Threshold
Bin	True	51535	1
Bin	False	64	1

"if" / "when" / "else" condition:

339: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	30848	1
Bin	False	526284995	1

"if" / "when" / "else" condition:

343: elsif (write_raw_OK = '1') then

	Evaluated to	Count	Threshold
Bin	True	192870	1
Bin	False	526092125	1

"if" / "when" / "else" condition:

353: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	True	51619	1
Bin	False	526315843	1

"if" / "when" / "else" condition:

354: if (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	True	27	1
Bin	False	51592	1

"if" / "when" / "else" condition:

360: elsif (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	True	13283	1
Bin	False	526302560	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RX_BUF_RES_N_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	8437	1
Bin	1	0	8428	1

Port:

REC_ABORT_F

	From	To	Count	Threshold
Bin	0	1	30820	1
Bin	1	0	32420	1

Port:

COMMIT_RX_FRAME

	From	To	Count	Threshold
Bin	0	1	13310	1
Bin	1	0	14910	1

Port:

WRITE_RAW_OK

	From	To	Count	Threshold
Bin	0	1	113009	1
Bin	1	0	114609	1

Port:

COMMIT_OVERRUN_ABORT

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1648	1

Port:

STORE_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	26351	1
Bin	1	0	27951	1

Port:

INC_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	13021	1
Bin	1	0	14621	1

Port:

READ_INCREMENT

	From	To	Count	Threshold
Bin	0	1	51619	1
Bin	1	0	53219	1

Port:

READ_POINTER(11)

	From	To	Count	Threshold
Bin	0	1	3	1
Bin	1	0	168	1

Port:

READ_POINTER(10)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	170	1

Port:

READ_POINTER(9)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Port:

READ_POINTER(8)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	187	1

Port:

READ_POINTER(7)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	208	1

Port:

READ_POINTER(6)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	862	1

Port:

READ_POINTER(5)

	From	To	Count	Threshold
Bin	0	1	426	1
Bin	1	0	1086	1

Port:

READ_POINTER(4)

	From	To	Count	Threshold
Bin	0	1	1582	1
Bin	1	0	3182	1

Port:

READ_POINTER(3)

	From	To	Count	Threshold
Bin	0	1	3172	1
Bin	1	0	4772	1

Port:

READ_POINTER(2)

	From	To	Count	Threshold
Bin	0	1	6629	1
Bin	1	0	8229	1

Port:

READ_POINTER(1)

	From	To	Count	Threshold
Bin	0	1	12979	1
Bin	1	0	14579	1

Port:

READ_POINTER(0)

	From	To	Count	Threshold
Bin	0	1	25949	1
Bin	1	0	27549	1

Port:

READ_POINTER_INC_1(11)

	From	To	Count	Threshold
Bin	0	1	3	1
Bin	1	0	168	1

Port:

READ_POINTER_INC_1(10)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	170	1

Port:

READ_POINTER_INC_1(9)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Port:

READ_POINTER_INC_1(8)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	187	1

Port:

READ_POINTER_INC_1(7)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	208	1

Port:

READ_POINTER_INC_1(6)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	862	1

Port:

READ_POINTER_INC_1(5)

	From	To	Count	Threshold
Bin	0	1	435	1
Bin	1	0	1095	1

Port:

READ_POINTER_INC_1(4)

	From	To	Count	Threshold
Bin	0	1	1594	1
Bin	1	0	3194	1

Port:

READ_POINTER_INC_1(3)

	From	To	Count	Threshold
Bin	0	1	3183	1
Bin	1	0	4783	1

Port:

READ_POINTER_INC_1(2)

	From	To	Count	Threshold
Bin	0	1	6672	1
Bin	1	0	8272	1

Port:

READ_POINTER_INC_1(1)

	From	To	Count	Threshold
Bin	0	1	13177	1
Bin	1	0	14777	1

Port:

READ_POINTER_INC_1(0)

	From	To	Count	Threshold
Bin	0	1	27549	1
Bin	1	0	25949	1

Port:

WRITE_POINTER(11)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	171	1

Port:

WRITE_POINTER(10)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Port:

WRITE_POINTER(9)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Port:

WRITE_POINTER(8)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Port:

WRITE_POINTER(7)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Port:

WRITE_POINTER(6)

	From	To	Count	Threshold
Bin	0	1	308	1
Bin	1	0	968	1

Port:

WRITE_POINTER(5)

	From	To	Count	Threshold
Bin	0	1	659	1
Bin	1	0	1319	1

Port:

WRITE_POINTER(4)

	From	To	Count	Threshold
Bin	0	1	1974	1
Bin	1	0	3574	1

Port:

WRITE_POINTER(3)

	From	To	Count	Threshold
Bin	0	1	3743	1
Bin	1	0	5343	1

Port:

WRITE_POINTER(2)

	From	To	Count	Threshold
Bin	0	1	6142	1
Bin	1	0	7740	1

Port:

WRITE_POINTER(1)

	From	To	Count	Threshold
Bin	0	1	1871	1
Bin	1	0	3471	1

Port:

WRITE_POINTER(0)

	From	To	Count	Threshold
Bin	0	1	1547	1
Bin	1	0	3147	1

Port:

WRITE_POINTER_RAW(11)

	From	To	Count	Threshold
Bin	0	1	7	1
Bin	1	0	172	1

Port:

WRITE_POINTER_RAW(10)

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	177	1

Port:

WRITE_POINTER_RAW(9)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	190	1

Port:

WRITE_POINTER_RAW(8)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	214	1

Port:

WRITE_POINTER_RAW(7)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	261	1

Port:

WRITE_POINTER_RAW(6)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	1008	1

Port:

WRITE_POINTER_RAW(5)

	From	To	Count	Threshold
Bin	0	1	740	1
Bin	1	0	1400	1

Port:

WRITE_POINTER_RAW(4)

	From	To	Count	Threshold
Bin	0	1	4611	1
Bin	1	0	6211	1

Port:

WRITE_POINTER_RAW(3)

	From	To	Count	Threshold
Bin	0	1	11766	1
Bin	1	0	13366	1

Port:

WRITE_POINTER_RAW(2)

	From	To	Count	Threshold
Bin	0	1	26827	1
Bin	1	0	28425	1

Port:

WRITE_POINTER_RAW(1)

	From	To	Count	Threshold
Bin	0	1	49427	1
Bin	1	0	51027	1

Port:

WRITE_POINTER_RAW(0)

	From	To	Count	Threshold
Bin	0	1	99316	1
Bin	1	0	100916	1

Port:

WRITE_POINTER_TS(11)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	171	1

Port:

WRITE_POINTER_TS(10)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Port:

WRITE_POINTER_TS(9)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Port:

WRITE_POINTER_TS(8)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Port:

WRITE_POINTER_TS(7)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Port:

WRITE_POINTER_TS(6)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	961	1

Port:

WRITE_POINTER_TS(5)

	From	To	Count	Threshold
Bin	0	1	637	1
Bin	1	0	1297	1

Port:

WRITE_POINTER_TS(4)

	From	To	Count	Threshold
Bin	0	1	1894	1
Bin	1	0	3494	1

Port:

WRITE_POINTER_TS(3)

	From	To	Count	Threshold
Bin	0	1	3612	1
Bin	1	0	5212	1

Port:

WRITE_POINTER_TS(2)

	From	To	Count	Threshold
Bin	0	1	6193	1
Bin	1	0	7793	1

Port:

WRITE_POINTER_TS(1)

	From	To	Count	Threshold
Bin	0	1	3653	1
Bin	1	0	5247	1

Port:

WRITE_POINTER_TS(0)

	From	To	Count	Threshold
Bin	0	1	11745	1
Bin	1	0	13343	1

Port:

RX_MEM_FREE_I(12)

	From	To	Count	Threshold
Bin	0	1	1204	1
Bin	1	0	1039	1

Port:

RX_MEM_FREE_I(11)

	From	To	Count	Threshold
Bin	0	1	1041	1
Bin	1	0	1206	1

Port:

RX_MEM_FREE_I(10)

	From	To	Count	Threshold
Bin	0	1	1048	1
Bin	1	0	1213	1

Port:

RX_MEM_FREE_I(9)

	From	To	Count	Threshold
Bin	0	1	1062	1
Bin	1	0	1227	1

Port:

RX_MEM_FREE_I(8)

	From	To	Count	Threshold
Bin	0	1	1090	1
Bin	1	0	1255	1

Port:

RX_MEM_FREE_I(7)

	From	To	Count	Threshold
Bin	0	1	4483	1
Bin	1	0	4153	1

Port:

RX_MEM_FREE_I(6)

	From	To	Count	Threshold
Bin	0	1	4110	1
Bin	1	0	4770	1

Port:

RX_MEM_FREE_I(5)

	From	To	Count	Threshold
Bin	0	1	8773	1
Bin	1	0	8495	1

Port:

RX_MEM_FREE_I(4)

	From	To	Count	Threshold
Bin	0	1	8368	1
Bin	1	0	9966	1

Port:

RX_MEM_FREE_I(3)

	From	To	Count	Threshold
Bin	0	1	9899	1
Bin	1	0	11497	1

Port:

RX_MEM_FREE_I(2)

	From	To	Count	Threshold
Bin	0	1	12195	1
Bin	1	0	13793	1

Port:

RX_MEM_FREE_I(1)

	From	To	Count	Threshold
Bin	0	1	15908	1
Bin	1	0	17508	1

Port:

RX_MEM_FREE_I(0)

	From	To	Count	Threshold
Bin	0	1	27214	1
Bin	1	0	28814	1

Signal:

READ_POINTER_I(11)

	From	To	Count	Threshold
Bin	0	1	3	1
Bin	1	0	168	1

Signal:

READ_POINTER_I(10)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	170	1

Signal:

READ_POINTER_I(9)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Signal:

READ_POINTER_I(8)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	187	1

Signal:

READ_POINTER_I(7)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	208	1

Signal:

READ_POINTER_I(6)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	862	1

Signal:

READ_POINTER_I(5)

	From	To	Count	Threshold
Bin	0	1	426	1
Bin	1	0	1086	1

Signal:

READ_POINTER_I(4)

	From	To	Count	Threshold
Bin	0	1	1582	1
Bin	1	0	3182	1

Signal:

READ_POINTER_I(3)

	From	To	Count	Threshold
Bin	0	1	3172	1
Bin	1	0	4772	1

Signal:

READ_POINTER_I(2)

	From	To	Count	Threshold
Bin	0	1	6629	1
Bin	1	0	8229	1

Signal:

READ_POINTER_I(1)

	From	To	Count	Threshold
Bin	0	1	12979	1
Bin	1	0	14579	1

Signal:

READ_POINTER_I(0)

	From	To	Count	Threshold
Bin	0	1	25949	1
Bin	1	0	27549	1

Signal:

READ_POINTER_INC_1_I(11)

	From	To	Count	Threshold
Bin	0	1	3	1
Bin	1	0	168	1

Signal:

READ_POINTER_INC_1_I(10)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	170	1

Signal:

READ_POINTER_INC_1_I(9)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Signal:

READ_POINTER_INC_1_I(8)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	187	1

Signal:

READ_POINTER_INC_1_I(7)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	208	1

Signal:

READ_POINTER_INC_1_I(6)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	862	1

Signal:

READ_POINTER_INC_1_I(5)

	From	To	Count	Threshold
Bin	0	1	435	1
Bin	1	0	1095	1

Signal:

READ_POINTER_INC_1_I(4)

	From	To	Count	Threshold
Bin	0	1	1594	1
Bin	1	0	3194	1

Signal:

READ_POINTER_INC_1_I(3)

	From	To	Count	Threshold
Bin	0	1	3183	1
Bin	1	0	4783	1

Signal:

READ_POINTER_INC_1_I(2)

	From	To	Count	Threshold
Bin	0	1	6672	1
Bin	1	0	8272	1

Signal:

READ_POINTER_INC_1_I(1)

	From	To	Count	Threshold
Bin	0	1	13177	1
Bin	1	0	14777	1

Signal:

READ_POINTER_INC_1_I(0)

	From	To	Count	Threshold
Bin	0	1	27549	1
Bin	1	0	25949	1

Signal:

WRITE_POINTER_I(11)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	171	1

Signal:

WRITE_POINTER_I(10)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Signal:

WRITE_POINTER_I(9)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Signal:

WRITE_POINTER_I(8)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

WRITE_POINTER_I(7)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Signal:

WRITE_POINTER_I(6)

	From	To	Count	Threshold
Bin	0	1	308	1
Bin	1	0	968	1

Signal:

WRITE_POINTER_I(5)

	From	To	Count	Threshold
Bin	0	1	659	1
Bin	1	0	1319	1

Signal:

WRITE_POINTER_I(4)

	From	To	Count	Threshold
Bin	0	1	1974	1
Bin	1	0	3574	1

Signal:

WRITE_POINTER_I(3)

	From	To	Count	Threshold
Bin	0	1	3743	1
Bin	1	0	5343	1

Signal:

WRITE_POINTER_I(2)

	From	To	Count	Threshold
Bin	0	1	6142	1
Bin	1	0	7740	1

Signal:

WRITE_POINTER_I(1)

	From	To	Count	Threshold
Bin	0	1	1871	1
Bin	1	0	3471	1

Signal:

WRITE_POINTER_I(0)

	From	To	Count	Threshold
Bin	0	1	1547	1
Bin	1	0	3147	1

Signal:

WRITE_POINTER_RAW_I(11)

	From	To	Count	Threshold
Bin	0	1	7	1
Bin	1	0	172	1

Signal:

WRITE_POINTER_RAW_I(10)

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	177	1

Signal:

WRITE_POINTER_RAW_I(9)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	190	1

Signal:

WRITE_POINTER_RAW_I(8)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	214	1

Signal:

WRITE_POINTER_RAW_I(7)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	261	1

Signal:

WRITE_POINTER_RAW_I(6)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	1008	1

Signal:

WRITE_POINTER_RAW_I(5)

	From	To	Count	Threshold
Bin	0	1	740	1
Bin	1	0	1400	1

Signal:

WRITE_POINTER_RAW_I(4)

	From	To	Count	Threshold
Bin	0	1	4611	1
Bin	1	0	6211	1

Signal:

WRITE_POINTER_RAW_I(3)

	From	To	Count	Threshold
Bin	0	1	11766	1
Bin	1	0	13366	1

Signal:

WRITE_POINTER_RAW_I(2)

	From	To	Count	Threshold
Bin	0	1	26827	1
Bin	1	0	28425	1

Signal:

WRITE_POINTER_RAW_I(1)

	From	To	Count	Threshold
Bin	0	1	49427	1
Bin	1	0	51027	1

Signal:

WRITE_POINTER_RAW_I(0)

	From	To	Count	Threshold
Bin	0	1	99316	1
Bin	1	0	100916	1

Signal:

WRITE_POINTER_RAW_D(11)

	From	To	Count	Threshold
Bin	0	1	33	1
Bin	1	0	198	1

Signal:

WRITE_POINTER_RAW_D(10)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	239	1

Signal:

WRITE_POINTER_RAW_D(9)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	316	1

Signal:

WRITE_POINTER_RAW_D(8)

	From	To	Count	Threshold
Bin	0	1	302	1
Bin	1	0	467	1

Signal:

WRITE_POINTER_RAW_D(7)

	From	To	Count	Threshold
Bin	0	1	612	1
Bin	1	0	777	1

Signal:

WRITE_POINTER_RAW_D(6)

	From	To	Count	Threshold
Bin	0	1	1830	1
Bin	1	0	2490	1

Signal:

WRITE_POINTER_RAW_D(5)

	From	To	Count	Threshold
Bin	0	1	3990	1
Bin	1	0	4650	1

Signal:

WRITE_POINTER_RAW_D(4)

	From	To	Count	Threshold
Bin	0	1	21950	1
Bin	1	0	23550	1

Signal:

WRITE_POINTER_RAW_D(3)

	From	To	Count	Threshold
Bin	0	1	68795	1
Bin	1	0	70395	1

Signal:

WRITE_POINTER_RAW_D(2)

	From	To	Count	Threshold
Bin	0	1	89232	1
Bin	1	0	90830	1

Signal:

WRITE_POINTER_RAW_D(1)

	From	To	Count	Threshold
Bin	0	1	101731	1
Bin	1	0	103331	1

Signal:

WRITE_POINTER_RAW_D(0)

	From	To	Count	Threshold
Bin	0	1	167866	1
Bin	1	0	169466	1

Signal:

WRITE_POINTER_RAW_CE

	From	To	Count	Threshold
Bin	0	1	143865	1
Bin	1	0	145465	1

Signal:

WRITE_POINTER_TS_I(11)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	171	1

Signal:

WRITE_POINTER_TS_I(10)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Signal:

WRITE_POINTER_TS_I(9)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Signal:

WRITE_POINTER_TS_I(8)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

WRITE_POINTER_TS_I(7)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Signal:

WRITE_POINTER_TS_I(6)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	961	1

Signal:

WRITE_POINTER_TS_I(5)

	From	To	Count	Threshold
Bin	0	1	637	1
Bin	1	0	1297	1

Signal:

WRITE_POINTER_TS_I(4)

	From	To	Count	Threshold
Bin	0	1	1894	1
Bin	1	0	3494	1

Signal:

WRITE_POINTER_TS_I(3)

	From	To	Count	Threshold
Bin	0	1	3612	1
Bin	1	0	5212	1

Signal:

WRITE_POINTER_TS_I(2)

	From	To	Count	Threshold
Bin	0	1	6193	1
Bin	1	0	7793	1

Signal:

WRITE_POINTER_TS_I(1)

	From	To	Count	Threshold
Bin	0	1	3653	1
Bin	1	0	5247	1

Signal:

WRITE_POINTER_TS_I(0)

	From	To	Count	Threshold
Bin	0	1	11745	1
Bin	1	0	13343	1

Signal:

WRITE_POINTER_TS_D(11)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	171	1

Signal:

WRITE_POINTER_TS_D(10)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	176	1

Signal:

WRITE_POINTER_TS_D(9)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Signal:

WRITE_POINTER_TS_D(8)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

WRITE_POINTER_TS_D(7)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Signal:

WRITE_POINTER_TS_D(6)

	From	To	Count	Threshold
Bin	0	1	303	1
Bin	1	0	963	1

Signal:

WRITE_POINTER_TS_D(5)

	From	To	Count	Threshold
Bin	0	1	644	1
Bin	1	0	1304	1

Signal:

WRITE_POINTER_TS_D(4)

	From	To	Count	Threshold
Bin	0	1	1967	1
Bin	1	0	3567	1

Signal:

WRITE_POINTER_TS_D(3)

	From	To	Count	Threshold
Bin	0	1	3789	1
Bin	1	0	5389	1

Signal:

WRITE_POINTER_TS_D(2)

	From	To	Count	Threshold
Bin	0	1	7485	1
Bin	1	0	9083	1

Signal:

WRITE_POINTER_TS_D(1)

	From	To	Count	Threshold
Bin	0	1	11959	1
Bin	1	0	13555	1

Signal:

WRITE_POINTER_TS_D(0)

	From	To	Count	Threshold
Bin	0	1	30008	1
Bin	1	0	28410	1

Signal:

WRITE_POINTER_TS_CE

	From	To	Count	Threshold
Bin	0	1	39372	1
Bin	1	0	40972	1

Signal:

RX_MEM_FREE_I_I(12)

	From	To	Count	Threshold
Bin	0	1	1204	1
Bin	1	0	1039	1

Signal:

RX_MEM_FREE_I_I(11)

	From	To	Count	Threshold
Bin	0	1	1041	1
Bin	1	0	1206	1

Signal:

RX_MEM_FREE_I_I(10)

	From	To	Count	Threshold
Bin	0	1	1048	1
Bin	1	0	1213	1

Signal:

RX_MEM_FREE_I_I(9)

	From	To	Count	Threshold
Bin	0	1	1062	1
Bin	1	0	1227	1

Signal:

RX_MEM_FREE_I_I(8)

	From	To	Count	Threshold
Bin	0	1	1090	1
Bin	1	0	1255	1

Signal:

RX_MEM_FREE_I_I(7)

	From	To	Count	Threshold
Bin	0	1	4483	1
Bin	1	0	4153	1

Signal:

RX_MEM_FREE_I_I(6)

	From	To	Count	Threshold
Bin	0	1	4110	1
Bin	1	0	4770	1

Signal:

RX_MEM_FREE_I_I(5)

	From	To	Count	Threshold
Bin	0	1	8773	1
Bin	1	0	8495	1

Signal:

RX_MEM_FREE_I_I(4)

	From	To	Count	Threshold
Bin	0	1	8368	1
Bin	1	0	9966	1

Signal:

RX_MEM_FREE_I_I(3)

	From	To	Count	Threshold
Bin	0	1	9899	1
Bin	1	0	11497	1

Signal:

RX_MEM_FREE_I_I(2)

	From	To	Count	Threshold
Bin	0	1	12195	1
Bin	1	0	13793	1

Signal:

RX_MEM_FREE_I_I(1)

	From	To	Count	Threshold
Bin	0	1	15908	1
Bin	1	0	17508	1

Signal:

RX_MEM_FREE_I_I(0)

	From	To	Count	Threshold
Bin	0	1	27214	1
Bin	1	0	28814	1

Signal:

RX_MEM_FREE_RAW(12)

	From	To	Count	Threshold
Bin	0	1	1155	1
Bin	1	0	990	1

Signal:

RX_MEM_FREE_RAW(11)

	From	To	Count	Threshold
Bin	0	1	992	1
Bin	1	0	1157	1

Signal:

RX_MEM_FREE_RAW(10)

	From	To	Count	Threshold
Bin	0	1	999	1
Bin	1	0	1164	1

Signal:

RX_MEM_FREE_RAW(9)

	From	To	Count	Threshold
Bin	0	1	1013	1
Bin	1	0	1178	1

Signal:

RX_MEM_FREE_RAW(8)

	From	To	Count	Threshold
Bin	0	1	1041	1
Bin	1	0	1206	1

Signal:

RX_MEM_FREE_RAW(7)

	From	To	Count	Threshold
Bin	0	1	4253	1
Bin	1	0	3923	1

Signal:

RX_MEM_FREE_RAW(6)

	From	To	Count	Threshold
Bin	0	1	3880	1
Bin	1	0	4540	1

Signal:

RX_MEM_FREE_RAW(5)

	From	To	Count	Threshold
Bin	0	1	20894	1
Bin	1	0	20616	1

Signal:

RX_MEM_FREE_RAW(4)

	From	To	Count	Threshold
Bin	0	1	20631	1
Bin	1	0	22229	1

Signal:

RX_MEM_FREE_RAW(3)

	From	To	Count	Threshold
Bin	0	1	24767	1
Bin	1	0	26365	1

Signal:

RX_MEM_FREE_RAW(2)

	From	To	Count	Threshold
Bin	0	1	39087	1
Bin	1	0	40685	1

Signal:

RX_MEM_FREE_RAW(1)

	From	To	Count	Threshold
Bin	0	1	66448	1
Bin	1	0	68048	1

Signal:

RX_MEM_FREE_RAW(0)

	From	To	Count	Threshold
Bin	0	1	124925	1
Bin	1	0	126525	1

Signal:

RX_MEM_FREE_RAW_INC_1(12)

	From	To	Count	Threshold
Bin	0	1	1157	1
Bin	1	0	992	1

Signal:

RX_MEM_FREE_RAW_INC_1(11)

	From	To	Count	Threshold
Bin	0	1	994	1
Bin	1	0	1159	1

Signal:

RX_MEM_FREE_RAW_INC_1(10)

	From	To	Count	Threshold
Bin	0	1	1001	1
Bin	1	0	1166	1

Signal:

RX_MEM_FREE_RAW_INC_1(9)

	From	To	Count	Threshold
Bin	0	1	1015	1
Bin	1	0	1180	1

Signal:

RX_MEM_FREE_RAW_INC_1(8)

	From	To	Count	Threshold
Bin	0	1	1043	1
Bin	1	0	1208	1

Signal:

RX_MEM_FREE_RAW_INC_1(7)

	From	To	Count	Threshold
Bin	0	1	4259	1
Bin	1	0	3929	1

Signal:

RX_MEM_FREE_RAW_INC_1(6)

	From	To	Count	Threshold
Bin	0	1	3886	1
Bin	1	0	4546	1

Signal:

RX_MEM_FREE_RAW_INC_1(5)

	From	To	Count	Threshold
Bin	0	1	20903	1
Bin	1	0	20625	1

Signal:

RX_MEM_FREE_RAW_INC_1(4)

	From	To	Count	Threshold
Bin	0	1	20636	1
Bin	1	0	22234	1

Signal:

RX_MEM_FREE_RAW_INC_1(3)

	From	To	Count	Threshold
Bin	0	1	23994	1
Bin	1	0	25592	1

Signal:

RX_MEM_FREE_RAW_INC_1(2)

	From	To	Count	Threshold
Bin	0	1	35806	1
Bin	1	0	37404	1

Signal:

RX_MEM_FREE_RAW_INC_1(1)

	From	To	Count	Threshold
Bin	0	1	61061	1
Bin	1	0	62661	1

Signal:

RX_MEM_FREE_RAW_INC_1(0)

	From	To	Count	Threshold
Bin	0	1	126525	1
Bin	1	0	124925	1

Signal:

RX_MEM_FREE_RAW_DEC_1(12)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	170	1

Signal:

RX_MEM_FREE_RAW_DEC_1(11)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	7	1

Signal:

RX_MEM_FREE_RAW_DEC_1(10)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	14	1

Signal:

RX_MEM_FREE_RAW_DEC_1(9)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	28	1

Signal:

RX_MEM_FREE_RAW_DEC_1(8)

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	56	1

Signal:

RX_MEM_FREE_RAW_DEC_1(7)

	From	To	Count	Threshold
Bin	0	1	292	1
Bin	1	0	622	1

Signal:

RX_MEM_FREE_RAW_DEC_1(6)

	From	To	Count	Threshold
Bin	0	1	910	1
Bin	1	0	250	1

Signal:

RX_MEM_FREE_RAW_DEC_1(5)

	From	To	Count	Threshold
Bin	0	1	1183	1
Bin	1	0	1463	1

Signal:

RX_MEM_FREE_RAW_DEC_1(4)

	From	To	Count	Threshold
Bin	0	1	5275	1
Bin	1	0	3675	1

Signal:

RX_MEM_FREE_RAW_DEC_1(3)

	From	To	Count	Threshold
Bin	0	1	13495	1
Bin	1	0	11895	1

Signal:

RX_MEM_FREE_RAW_DEC_1(2)

	From	To	Count	Threshold
Bin	0	1	33218	1
Bin	1	0	31620	1

Signal:

RX_MEM_FREE_RAW_DEC_1(1)

	From	To	Count	Threshold
Bin	0	1	62661	1
Bin	1	0	61061	1

Signal:

RX_MEM_FREE_RAW_DEC_1(0)

	From	To	Count	Threshold
Bin	0	1	126525	1
Bin	1	0	124925	1

Signal:

RX_MEM_FREE_I_INC_1(12)

	From	To	Count	Threshold
Bin	0	1	1206	1
Bin	1	0	1041	1

Signal:

RX_MEM_FREE_I_INC_1(11)

	From	To	Count	Threshold
Bin	0	1	1043	1
Bin	1	0	1208	1

Signal:

RX_MEM_FREE_I_INC_1(10)

	From	To	Count	Threshold
Bin	0	1	1050	1
Bin	1	0	1215	1

Signal:

RX_MEM_FREE_I_INC_1(9)

	From	To	Count	Threshold
Bin	0	1	1064	1
Bin	1	0	1229	1

Signal:

RX_MEM_FREE_I_INC_1(8)

	From	To	Count	Threshold
Bin	0	1	1092	1
Bin	1	0	1257	1

Signal:

RX_MEM_FREE_I_INC_1(7)

	From	To	Count	Threshold
Bin	0	1	4489	1
Bin	1	0	4159	1

Signal:

RX_MEM_FREE_I_INC_1(6)

	From	To	Count	Threshold
Bin	0	1	4116	1
Bin	1	0	4776	1

Signal:

RX_MEM_FREE_I_INC_1(5)

	From	To	Count	Threshold
Bin	0	1	8780	1
Bin	1	0	8502	1

Signal:

RX_MEM_FREE_I_INC_1(4)

	From	To	Count	Threshold
Bin	0	1	8371	1
Bin	1	0	9969	1

Signal:

RX_MEM_FREE_I_INC_1(3)

	From	To	Count	Threshold
Bin	0	1	9840	1
Bin	1	0	11438	1

Signal:

RX_MEM_FREE_I_INC_1(2)

	From	To	Count	Threshold
Bin	0	1	12203	1
Bin	1	0	13801	1

Signal:

RX_MEM_FREE_I_INC_1(1)

	From	To	Count	Threshold
Bin	0	1	13569	1
Bin	1	0	15169	1

Signal:

RX_MEM_FREE_I_INC_1(0)

	From	To	Count	Threshold
Bin	0	1	28814	1
Bin	1	0	27214	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	30868	1
Bin	1	0	32468	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

221: abort_applied <= '1' when (rec_abort_f = '1' or commit_overrun_abort = '1')

	Evaluated to	Count	Threshold
Bin	False	35716	1
Bin	True	30820	1

"=" expression

221: abort_applied <= '1' when (rec_abort_f = '1' or commit_overrun_abort = '1')

	Evaluated to	Count	Threshold
Bin	False	66488	1
Bin	True	48	1

"or" expression

221:    abort_applied <= '1' when (rec_abort_f = '1' or commit_overrun_abort = '1') 
                                   <------LHS------>    <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	35668	1
Bin	False	True	48	1
Bin	True	False	30820	1

"=" expression

231: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052745263	1
Bin	True	2432531	1

"=" expression

234: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	False	526315843	1
Bin	True	51619	1

"=" expression

246: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052745263	1
Bin	True	2432531	1

"=" expression

249: if (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	False	526354152	1
Bin	True	13310	1

"=" expression

262: write_pointer_raw_d <= write_pointer_raw_i + 1 when (write_raw_OK = '1')

	Evaluated to	Count	Threshold
Bin	False	145625	1
Bin	True	305943	1

"=" expression

266: write_pointer_raw_ce <= '1' when (write_raw_OK = '1') else

	Evaluated to	Count	Threshold
Bin	False	179540	1
Bin	True	113014	1

"=" expression

267: '1' when (rec_abort_f = '1') else

	Evaluated to	Count	Threshold
Bin	False	148713	1
Bin	True	30827	1

"=" expression

268: '1' when (commit_overrun_abort = '1') else

	Evaluated to	Count	Threshold
Bin	False	148665	1
Bin	True	48	1

"=" expression

273: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052745263	1
Bin	True	2432531	1

"=" expression

276: if (write_pointer_raw_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526143660	1
Bin	True	223802	1

"=" expression

286: write_pointer_ts_d <= write_pointer_raw_i when (store_ts_wr_ptr = '1')

	Evaluated to	Count	Threshold
Bin	False	225514	1
Bin	True	52702	1

"=" expression

291: write_pointer_ts_ce <= '1' when (store_ts_wr_ptr = '1') else

	Evaluated to	Count	Threshold
Bin	False	55593	1
Bin	True	26351	1

"=" expression

292: '1' when (inc_ts_wr_ptr = '1') else

	Evaluated to	Count	Threshold
Bin	False	42572	1
Bin	True	13021	1

"=" expression

297: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052745263	1
Bin	True	2432531	1

"=" expression

300: if (write_pointer_ts_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526328090	1
Bin	True	39372	1

"=" expression

312: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052745263	1
Bin	True	2432531	1

"=" expression

321: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	False	526315843	1
Bin	True	51619	1

"=" expression

325: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	51599	1
Bin	True	20	1

"=" expression

329: elsif (write_raw_OK = '0') then

	Evaluated to	Count	Threshold
Bin	False	64	1
Bin	True	51535	1

"=" expression

339: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	526284995	1
Bin	True	30848	1

"=" expression

343: elsif (write_raw_OK = '1') then

	Evaluated to	Count	Threshold
Bin	False	526092125	1
Bin	True	192870	1

"=" expression

353: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	False	526315843	1
Bin	True	51619	1

"=" expression

354: if (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	False	51592	1
Bin	True	27	1

"=" expression

360: elsif (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	False	526302560	1
Bin	True	13283	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_POINTERS_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_pointers.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

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Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition: