NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
PRIORITY_DECODER_INST	100.0 % (82/82)	100.0 % (36/36)	100.0 % (194/194)	100.0 % (19/19)	N.A.	N.A.	100.0 % (331/331)
TX_ARBITRATOR_FSM_INST	100.0 % (126/126)	100.0 % (136/136)	100.0 % (54/54)	100.0 % (141/141)	100.0 % (16/16)	N.A.	100.0 % (473/473)
TXTB_PRIORITY_GEN(0)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXTB_PRIORITY_GEN(1)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)
TXTB_PRIORITY_GEN(2)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXTB_PRIORITY_GEN(3)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)
TXTB_PRIORITY_GEN(4)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXTB_PRIORITY_GEN(5)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)
TXTB_PRIORITY_GEN(6)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXTB_PRIORITY_GEN(7)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST	100.0 % (132/132)	100.0 % (102/102)	100.0 % (1420/1420)	98.3 % (119/121)	N.A.	N.A.	99.8 % (1773/1775)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 354 to 360:

354:        if (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or 
355:            ((a(63 downto 32) = b(63 downto 32)) and 
...
359:           return '0'; 
360:        end if;

Count: 785501
Threshold: 1

Sequential statement on line 357:

357: return '1';
Count: 345041
Threshold: 1

Sequential statement on line 359:

359: return '0';
Count: 440460
Threshold: 1

If statement on lines 444 to 446:

444:    timestamp_valid <= less_than(txtb_timestamp, timestamp) when (mr_mode_tttm = TTTM_ENABLED) 
445:                                                            else 
446:                                                        '1';

Count: 545162337
Threshold: 1

Signal assignment statement on line 444:

444: timestamp_valid <= less_than(txtb_timestamp, timestamp) when (mr_mode_tttm = TTTM_ENABLED)
Count: 785501
Threshold: 1

Signal assignment statement on line 446:

446:                                                        '1';

Count: 544376836
Threshold: 1

If statement on lines 454 to 457:

454:    validated_buffer <= '1' when (txtb_available(curr_txtb_index_i) = '1') and 
455:                                 (tran_frame_valid_com = '1') 
456:                            else 
457:                        '0';

Count: 110601
Threshold: 1

Signal assignment statement on line 454:

454: validated_buffer <= '1' when (txtb_available(curr_txtb_index_i) = '1') and
Count: 25944
Threshold: 1

Signal assignment statement on line 457:

457: '0';
Count: 84657
Threshold: 1

If statement on lines 459 to 461:

459:    tran_frame_valid <= '1' when (validated_buffer = '1') or (tx_arb_locked = '1') 
460:                            else 
461:                        '0';

Count: 104768
Threshold: 1

Signal assignment statement on line 459:

459: tran_frame_valid <= '1' when (validated_buffer = '1') or (tx_arb_locked = '1')
Count: 76034
Threshold: 1

Signal assignment statement on line 461:

461: '0';
Count: 28734
Threshold: 1

If statement on lines 467 to 469:

467:    txtb_parity_mismatch_vld <= '1' when (txtb_parity_mismatch(select_buf_index) = '1') 
468:                                    else 
469:                                '0';

Count: 56378
Threshold: 1

Signal assignment statement on line 467:

467: txtb_parity_mismatch_vld <= '1' when (txtb_parity_mismatch(select_buf_index) = '1')
Count: 4180
Threshold: 1

Signal assignment statement on line 469:

469: '0';
Count: 52198
Threshold: 1

If statement on lines 477 to 479:

477:    txtb_parity_mismatch_tx <= '1' when (txtb_parity_mismatch(curr_txtb_index_i) = '1') 
478:                                   else 
479:                               '0';

Count: 23405
Threshold: 1

Signal assignment statement on line 477:

477: txtb_parity_mismatch_tx <= '1' when (txtb_parity_mismatch(curr_txtb_index_i) = '1')
Count: 2881
Threshold: 1

Signal assignment statement on line 479:

479: '0';
Count: 20524
Threshold: 1

If statement on lines 481 to 483:

481:    tran_frame_parity_error <= '1' when (txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1') 
482:                                   else 
483:                               '0';

Count: 169211
Threshold: 1

Signal assignment statement on line 481:

481: tran_frame_parity_error <= '1' when (txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1')
Count: 728
Threshold: 1

Signal assignment statement on line 483:

483: '0';
Count: 168483
Threshold: 1

If statement on lines 489 to 491:

489:    txtb_index_muxed_i <= curr_txtb_index_i when (tx_arb_locked = '1') 
490:                                            else 
491:                          select_buf_index;

Count: 110053
Threshold: 1

Signal assignment statement on line 489:

489: txtb_index_muxed_i <= curr_txtb_index_i when (tx_arb_locked = '1')
Count: 49681
Threshold: 1

Signal assignment statement on line 491:

491: select_buf_index;
Count: 60372
Threshold: 1

If statement on lines 497 to 499:

497:    txtb_parity_check_valid <= txtb_clk_en_q when (tx_arb_locked = '1') 
498:                                             else 
499:                               tx_arb_parity_check_valid;

Count: 422971
Threshold: 1

Signal assignment statement on line 497:

497: txtb_parity_check_valid <= txtb_clk_en_q when (tx_arb_locked = '1')
Count: 178271
Threshold: 1

Signal assignment statement on line 499:

499: tx_arb_parity_check_valid;
Count: 244700
Threshold: 1

Signal assignment statement on line 502:

502: txtb_selected_input <= txtb_port_b_data_out(txtb_index_muxed_i);
Count: 194708
Threshold: 1

Signal assignment statement on line 505:

505: tran_word <= txtb_selected_input;
Count: 159545
Threshold: 1

Signal assignment statement on line 506:

506: txtb_index_muxed <= txtb_index_muxed_i;
Count: 40297
Threshold: 1

Signal assignment statement on line 512:

512: txtb_timestamp <= txtb_selected_input & ts_low_internal;
Count: 161543
Threshold: 1

Signal assignment statement on line 517:

517: tran_dlc <= tran_dlc_com;
Count: 14588
Threshold: 1

Signal assignment statement on line 518:

518: tran_is_rtr <= tran_is_rtr_com;
Count: 5492
Threshold: 1

Signal assignment statement on line 519:

519: tran_ident_type <= tran_ident_type_com;
Count: 8289
Threshold: 1

Signal assignment statement on line 520:

520: tran_frame_type <= tran_frame_type_com;
Count: 8688
Threshold: 1

Signal assignment statement on line 521:

521: tran_brs <= tran_brs_com;
Count: 7168
Threshold: 1

Signal assignment statement on line 522:

522: tran_identifier <= tran_identifier_com;
Count: 17804
Threshold: 1

If statement on lines 529 to 531:

529:    txtb_port_b_address <= std_logic_vector(to_unsigned(txtb_ptr, 5)) when (tx_arb_locked = '1') 
530:                                                                      else 
531:                           std_logic_vector(to_unsigned(txtb_pointer_meta_q, 5));

Count: 265444
Threshold: 1

Signal assignment statement on line 529:

529: txtb_port_b_address <= std_logic_vector(to_unsigned(txtb_ptr, 5)) when (tx_arb_locked = '1')
Count: 105105
Threshold: 1

Signal assignment statement on line 531:

531: std_logic_vector(to_unsigned(txtb_pointer_meta_q, 5));
Count: 160339
Threshold: 1

If statement on lines 533 to 535:

533:    txtb_port_b_clk_en <= txtb_clk_en when (tx_arb_locked = '1') 
534:                                      else 
535:                          txtb_meta_clk_en;

Count: 261067
Threshold: 1

Signal assignment statement on line 533:

533: txtb_port_b_clk_en <= txtb_clk_en when (tx_arb_locked = '1')
Count: 178271
Threshold: 1

Signal assignment statement on line 535:

535: txtb_meta_clk_en;
Count: 82796
Threshold: 1

Signal assignment statement on line 539:

539: txtb_hw_cmd_cs <= (others => '0');
Count: 13983
Threshold: 1

Signal assignment statement on line 540:

540: txtb_hw_cmd_cs(curr_txtb_index_i) <= '1';
Count: 13983
Threshold: 1

If statement on lines 548 to 552:

548:        if (res_n = '0') then 
549:            txtb_clk_en_q <= '0'; 
550:        elsif (rising_edge(clk_sys)) then 
551:            txtb_clk_en_q <= txtb_clk_en; 
552:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 549:

549: txtb_clk_en_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 551:

551: txtb_clk_en_q <= txtb_clk_en;
Count: 543791678
Threshold: 1

If statement on lines 561 to 567:

561:        if (res_n = '0') then 
562:            ts_low_internal <= (others => '0'); 
...
566:            end if; 
567:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 562:

562: ts_low_internal <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 564 to 566:

564:            if (store_ts_l_w = '1') then 
565:                ts_low_internal <= txtb_selected_input; 
566:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 565:

565: ts_low_internal <= txtb_selected_input;
Count: 26263
Threshold: 1

If statement on lines 575 to 589:

575:        if (res_n = '0') then 
576:            tran_dlc_dbl_buf           <= (others => '0'); 
...
588:            end if; 
589:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 576:

576: tran_dlc_dbl_buf <= (others => '0');
Count: 2424883
Threshold: 1

Signal assignment statement on line 577:

577: tran_is_rtr_dbl_buf <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 578:

578: tran_ident_type_dbl_buf <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 579:

579: tran_frame_type_dbl_buf <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 580:

580: tran_brs_dbl_buf <= '0';
Count: 2424883
Threshold: 1

If statement on lines 582 to 588:

582:            if (buffer_md_w = '1') then 
583:                tran_dlc_dbl_buf           <= txtb_selected_input(DLC_H downto DLC_L); 
...
587:                tran_brs_dbl_buf           <= txtb_selected_input(BRS_IND); 
588:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 583:

583:                tran_dlc_dbl_buf           <= txtb_selected_input(DLC_H downto DLC_L);

Count: 25787
Threshold: 1

Signal assignment statement on line 584:

584: tran_is_rtr_dbl_buf <= txtb_selected_input(RTR_IND);
Count: 25787
Threshold: 1

Signal assignment statement on line 585:

585: tran_ident_type_dbl_buf <= txtb_selected_input(IDE_IND);
Count: 25787
Threshold: 1

Signal assignment statement on line 586:

586: tran_frame_type_dbl_buf <= txtb_selected_input(FDF_IND);
Count: 25787
Threshold: 1

Signal assignment statement on line 587:

587: tran_brs_dbl_buf <= txtb_selected_input(BRS_IND);
Count: 25787
Threshold: 1

If statement on lines 597 to 609:

597:        if (res_n = '0') then 
598:            tran_frame_test_dbl_buf.fstc <= '0'; 
...
608:            end if; 
609:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 598:

598: tran_frame_test_dbl_buf.fstc <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 599:

599: tran_frame_test_dbl_buf.fcrc <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 600:

600: tran_frame_test_dbl_buf.sdlc <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 601:

601: tran_frame_test_dbl_buf.tprm <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 603 to 608:

603:            if (buffer_frame_test_w = '1') then 
604:                tran_frame_test_dbl_buf.fstc <= txtb_selected_input(FSTC_IND); 
605:                tran_frame_test_dbl_buf.fcrc <= txtb_selected_input(FCRC_IND); 
606:                tran_frame_test_dbl_buf.sdlc <= txtb_selected_input(SDLC_IND); 
607:                tran_frame_test_dbl_buf.tprm <= txtb_selected_input(TPRM_H downto TPRM_L); 
608:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 604:

604: tran_frame_test_dbl_buf.fstc <= txtb_selected_input(FSTC_IND);
Count: 25904
Threshold: 1

Signal assignment statement on line 605:

605: tran_frame_test_dbl_buf.fcrc <= txtb_selected_input(FCRC_IND);
Count: 25904
Threshold: 1

Signal assignment statement on line 606:

606: tran_frame_test_dbl_buf.sdlc <= txtb_selected_input(SDLC_IND);
Count: 25904
Threshold: 1

Signal assignment statement on line 607:

607: tran_frame_test_dbl_buf.tprm <= txtb_selected_input(TPRM_H downto TPRM_L);
Count: 25904
Threshold: 1

If statement on lines 619 to 633:

619:        if (res_n = '0') then 
620:            tran_dlc_com         <= (others => '0'); 
...
632:            end if; 
633:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 620:

620: tran_dlc_com <= (others => '0');
Count: 2424883
Threshold: 1

Signal assignment statement on line 621:

621: tran_is_rtr_com <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 622:

622: tran_ident_type_com <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 623:

623: tran_frame_type_com <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 624:

624: tran_brs_com <= '0';
Count: 2424883
Threshold: 1

If statement on lines 626 to 632:

626:            if (commit_dbl_bufs = '1') then 
627:                tran_frame_type_com  <= tran_frame_type_dbl_buf; 
...
631:                tran_brs_com         <= tran_brs_dbl_buf; 
632:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 627:

627: tran_frame_type_com <= tran_frame_type_dbl_buf;
Count: 25568
Threshold: 1

Signal assignment statement on line 628:

628: tran_ident_type_com <= tran_ident_type_dbl_buf;
Count: 25568
Threshold: 1

Signal assignment statement on line 629:

629: tran_dlc_com <= tran_dlc_dbl_buf;
Count: 25568
Threshold: 1

Signal assignment statement on line 630:

630: tran_is_rtr_com <= tran_is_rtr_dbl_buf;
Count: 25568
Threshold: 1

Signal assignment statement on line 631:

631: tran_brs_com <= tran_brs_dbl_buf;
Count: 25568
Threshold: 1

If statement on lines 641 to 647:

641:        if (res_n = '0') then 
642:            tran_identifier_com <= (others => '0'); 
...
646:            end if; 
647:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 642:

642: tran_identifier_com <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 644 to 646:

644:            if (commit_dbl_bufs = '1') then 
645:                tran_identifier_com <= txtb_selected_input(28 downto 0); 
646:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 645:

645: tran_identifier_com <= txtb_selected_input(28 downto 0);
Count: 25568
Threshold: 1

If statement on lines 655 to 664:

655:        if (res_n = '0') then 
656:            tran_frame_test.fstc <= '0'; 
...
663:            end if; 
664:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 656:

656: tran_frame_test.fstc <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 657:

657: tran_frame_test.fcrc <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 658:

658: tran_frame_test.sdlc <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 659:

659: tran_frame_test.tprm <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 661 to 663:

661:            if (commit_dbl_bufs = '1') then 
662:                tran_frame_test <= tran_frame_test_dbl_buf; 
663:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 662:

662: tran_frame_test <= tran_frame_test_dbl_buf;
Count: 25568
Threshold: 1

If statement on lines 672 to 680:

672:        if (res_n = '0') then 
673:            tran_frame_valid_com        <= '0'; 
...
679:            end if; 
680:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 673:

673: tran_frame_valid_com <= '0';
Count: 2424883
Threshold: 1

If statement on lines 675 to 679:

675:            if (frame_valid_com_set = '1') then 
676:                tran_frame_valid_com    <= '1'; 
677:            elsif (frame_valid_com_clear = '1') then 
678:                tran_frame_valid_com    <= '0'; 
679:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 676:

676: tran_frame_valid_com <= '1';
Count: 25568
Threshold: 1

Signal assignment statement on line 678:

678: tran_frame_valid_com <= '0';
Count: 26018
Threshold: 1

If statement on lines 691 to 706:

691:        if (res_n = '0') then 
692:            last_txtb_index             <= 0; 
...
705: 
706:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 692:

692: last_txtb_index <= 0;
Count: 2424883
Threshold: 1

Signal assignment statement on line 693:

693: curr_txtb_index_i <= 0;
Count: 2424883
Threshold: 1

If statement on lines 697 to 699:

697:            if (store_last_txtb_index = '1') then 
698:                last_txtb_index         <= curr_txtb_index_i; 
699:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 698:

698: last_txtb_index <= curr_txtb_index_i;
Count: 25275
Threshold: 1

If statement on lines 702 to 704:

702:            if (commit_dbl_bufs = '1') then 
703:                curr_txtb_index_i       <= select_buf_index; 
704:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 703:

703: curr_txtb_index_i <= select_buf_index;
Count: 25568
Threshold: 1

If statement on lines 709 to 711:

709:    txtb_changed  <= '1' when (last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1') 
710:                         else 
711:                     '0';

Count: 76154
Threshold: 1

Signal assignment statement on line 709:

709:    txtb_changed  <= '1' when (last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1')

Count: 10020
Threshold: 1

Signal assignment statement on line 711:

711: '0';
Count: 66134
Threshold: 1

Signal assignment statement on line 713:

713: curr_txtb_index <= std_logic_vector(to_unsigned(curr_txtb_index_i, 3));
Count: 13983
Threshold: 1

If statement on lines 721 to 725:

721:        if (res_n = '0') then 
722:            select_buf_index_reg  <= 0; 
723:        elsif (rising_edge(clk_sys)) then 
724:            select_buf_index_reg <= select_buf_index; 
725:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 722:

722: select_buf_index_reg <= 0;
Count: 2424883
Threshold: 1

Signal assignment statement on line 724:

724: select_buf_index_reg <= select_buf_index;
Count: 543791678
Threshold: 1

If statement on lines 728 to 730:

728:    select_index_changed <= '0' when (select_buf_index = select_buf_index_reg) 
729:                                else 
730:                            '1';

Count: 99614
Threshold: 1

Signal assignment statement on line 728:

728: select_index_changed <= '0' when (select_buf_index = select_buf_index_reg)
Count: 46084
Threshold: 1

Signal assignment statement on line 730:

730: '1';
Count: 53530
Threshold: 1

If statement on lines 736 to 742:

736:    txtb_pointer_meta_d <= 
737:        to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))) when (load_ts_lw_addr = '1') else 
...
741:        to_integer(unsigned(FRAME_TEST_W_ADR(11 downto 2))) when (load_frame_test_w_addr = '1') else 
742:        txtb_pointer_meta_q;

Count: 400966
Threshold: 1

Signal assignment statement on line 737:

737: to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))) when (load_ts_lw_addr = '1') else
Count: 50412
Threshold: 1

Signal assignment statement on line 738:

738: to_integer(unsigned(TIMESTAMP_U_W_ADR(11 downto 2))) when (load_ts_uw_addr = '1') else
Count: 52613
Threshold: 1

Signal assignment statement on line 739:

739: to_integer(unsigned(FRAME_FORMAT_W_ADR(11 downto 2))) when (load_ffmt_w_addr = '1') else
Count: 51864
Threshold: 1

Signal assignment statement on line 740:

740: to_integer(unsigned(IDENTIFIER_W_ADR(11 downto 2))) when (load_ident_w_addr = '1') else
Count: 51634
Threshold: 1

Signal assignment statement on line 741:

741:        to_integer(unsigned(FRAME_TEST_W_ADR(11 downto 2))) when (load_frame_test_w_addr = '1') else

Count: 52232
Threshold: 1

Signal assignment statement on line 742:

742: txtb_pointer_meta_q;
Count: 142211
Threshold: 1

If statement on lines 746 to 750:

746:        if (res_n = '0') then 
747:            txtb_pointer_meta_q <= to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))); 
748:        elsif (rising_edge(clk_sys)) then 
749:            txtb_pointer_meta_q <= txtb_pointer_meta_d; 
750:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 747:

747: txtb_pointer_meta_q <= to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2)));
Count: 2424883
Threshold: 1

Signal assignment statement on line 749:

749: txtb_pointer_meta_q <= txtb_pointer_meta_d;
Count: 543791678
Threshold: 1

If statement on lines 756 to 759:

756:    txtb_hw_cmd_unlock <= '1' when (txtb_hw_cmd.valid  = '1' or txtb_hw_cmd.err    = '1' or 
757:                                    txtb_hw_cmd.arbl   = '1' or txtb_hw_cmd.failed = '1') 
758:                              else 
759:                          '0';

Count: 53732
Threshold: 1

Signal assignment statement on line 756:

756: txtb_hw_cmd_unlock <= '1' when (txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' or
Count: 25265
Threshold: 1

Signal assignment statement on line 759:

759: '0';
Count: 28467
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 354 to 356:

354:        if (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or 
355:            ((a(63 downto 32) = b(63 downto 32)) and 
356:            (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))))then

	Evaluated to	Count	Threshold
Bin	True	345041	1
Bin	False	440460	1

"if" / "when" / "else" condition on line 444:

444: timestamp_valid <= less_than(txtb_timestamp, timestamp) when (mr_mode_tttm = TTTM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	785501	1
Bin	False	544376836	1

"if" / "when" / "else" condition on lines 454 to 455:

454:    validated_buffer <= '1' when (txtb_available(curr_txtb_index_i) = '1') and 
455:                                 (tran_frame_valid_com = '1')

	Evaluated to	Count	Threshold
Bin	True	25944	1
Bin	False	84657	1

"if" / "when" / "else" condition on line 459:

459: tran_frame_valid <= '1' when (validated_buffer = '1') or (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	76034	1
Bin	False	28734	1

"if" / "when" / "else" condition on line 467:

467: txtb_parity_mismatch_vld <= '1' when (txtb_parity_mismatch(select_buf_index) = '1')

	Evaluated to	Count	Threshold
Bin	True	4180	1
Bin	False	52198	1

"if" / "when" / "else" condition on line 477:

477: txtb_parity_mismatch_tx <= '1' when (txtb_parity_mismatch(curr_txtb_index_i) = '1')

	Evaluated to	Count	Threshold
Bin	True	2881	1
Bin	False	20524	1

"if" / "when" / "else" condition on line 481:

481: tran_frame_parity_error <= '1' when (txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1')

	Evaluated to	Count	Threshold
Bin	True	728	1
Bin	False	168483	1

"if" / "when" / "else" condition on line 489:

489: txtb_index_muxed_i <= curr_txtb_index_i when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	49681	1
Bin	False	60372	1

"if" / "when" / "else" condition on line 497:

497: txtb_parity_check_valid <= txtb_clk_en_q when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	178271	1
Bin	False	244700	1

"if" / "when" / "else" condition on line 529:

529: txtb_port_b_address <= std_logic_vector(to_unsigned(txtb_ptr, 5)) when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	105105	1
Bin	False	160339	1

"if" / "when" / "else" condition on line 533:

533: txtb_port_b_clk_en <= txtb_clk_en when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	178271	1
Bin	False	82796	1

"if" / "when" / "else" condition on line 548:

548: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 550:

550: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 561:

561: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 563:

563: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 564:

564: if (store_ts_l_w = '1') then

	Evaluated to	Count	Threshold
Bin	True	26263	1
Bin	False	543765415	1

"if" / "when" / "else" condition on line 575:

575: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 581:

581: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 582:

582: if (buffer_md_w = '1') then

	Evaluated to	Count	Threshold
Bin	True	25787	1
Bin	False	543765891	1

"if" / "when" / "else" condition on line 597:

597: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 602:

602: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 603:

603: if (buffer_frame_test_w = '1') then

	Evaluated to	Count	Threshold
Bin	True	25904	1
Bin	False	543765774	1

"if" / "when" / "else" condition on line 619:

619: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 625:

625: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 626:

626: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25568	1
Bin	False	543766110	1

"if" / "when" / "else" condition on line 641:

641: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 643:

643: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 644:

644: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25568	1
Bin	False	543766110	1

"if" / "when" / "else" condition on line 655:

655: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 660:

660: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 661:

661: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25568	1
Bin	False	543766110	1

"if" / "when" / "else" condition on line 672:

672: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 674:

674: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 675:

675: if (frame_valid_com_set = '1') then

	Evaluated to	Count	Threshold
Bin	True	25568	1
Bin	False	543766110	1

"if" / "when" / "else" condition on line 677:

677: elsif (frame_valid_com_clear = '1') then

	Evaluated to	Count	Threshold
Bin	True	26018	1
Bin	False	543740092	1

"if" / "when" / "else" condition on line 691:

691: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 695:

695: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 697:

697: if (store_last_txtb_index = '1') then

	Evaluated to	Count	Threshold
Bin	True	25275	1
Bin	False	543766403	1

"if" / "when" / "else" condition on line 702:

702: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25568	1
Bin	False	543766110	1

"if" / "when" / "else" condition on line 709:

709:    txtb_changed  <= '1' when (last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1')

	Evaluated to	Count	Threshold
Bin	True	10020	1
Bin	False	66134	1

"if" / "when" / "else" condition on line 721:

721: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 723:

723: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 728:

728: select_index_changed <= '0' when (select_buf_index = select_buf_index_reg)

	Evaluated to	Count	Threshold
Bin	True	46084	1
Bin	False	53530	1

"if" / "when" / "else" condition on line 737:

737: to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))) when (load_ts_lw_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	50412	1
Bin	False	350554	1

"if" / "when" / "else" condition on line 738:

738: to_integer(unsigned(TIMESTAMP_U_W_ADR(11 downto 2))) when (load_ts_uw_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	52613	1
Bin	False	297941	1

"if" / "when" / "else" condition on line 739:

739: to_integer(unsigned(FRAME_FORMAT_W_ADR(11 downto 2))) when (load_ffmt_w_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	51864	1
Bin	False	246077	1

"if" / "when" / "else" condition on line 740:

740: to_integer(unsigned(IDENTIFIER_W_ADR(11 downto 2))) when (load_ident_w_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	51634	1
Bin	False	194443	1

"if" / "when" / "else" condition on line 741:

741:        to_integer(unsigned(FRAME_TEST_W_ADR(11 downto 2))) when (load_frame_test_w_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	52232	1
Bin	False	142211	1

"if" / "when" / "else" condition on line 746:

746: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 748:

748: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on lines 756 to 757:

756:    txtb_hw_cmd_unlock <= '1' when (txtb_hw_cmd.valid  = '1' or txtb_hw_cmd.err    = '1' or 
757:                                    txtb_hw_cmd.arbl   = '1' or txtb_hw_cmd.failed = '1')

	Evaluated to	Count	Threshold
Bin	True	25265	1
Bin	False	28467	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Threshold	Excluded due to
Bin	(7)(31)	0	1	1	Exclude file
Bin	(7)(31)	1	0	1	Exclude file
Bin	(7)(30)	0	1	1	Exclude file
Bin	(7)(30)	1	0	1	Exclude file
Bin	(7)(29)	0	1	1	Exclude file
Bin	(7)(29)	1	0	1	Exclude file
Bin	(7)(28)	0	1	1	Exclude file
Bin	(7)(28)	1	0	1	Exclude file
Bin	(7)(27)	0	1	1	Exclude file
Bin	(7)(27)	1	0	1	Exclude file
Bin	(7)(26)	0	1	1	Exclude file
Bin	(7)(26)	1	0	1	Exclude file
Bin	(7)(25)	0	1	1	Exclude file
Bin	(7)(25)	1	0	1	Exclude file
Bin	(7)(24)	0	1	1	Exclude file
Bin	(7)(24)	1	0	1	Exclude file
Bin	(7)(23)	0	1	1	Exclude file
Bin	(7)(23)	1	0	1	Exclude file
Bin	(7)(22)	0	1	1	Exclude file
Bin	(7)(22)	1	0	1	Exclude file
Bin	(7)(21)	0	1	1	Exclude file
Bin	(7)(21)	1	0	1	Exclude file
Bin	(7)(20)	0	1	1	Exclude file
Bin	(7)(20)	1	0	1	Exclude file
Bin	(7)(19)	0	1	1	Exclude file
Bin	(7)(19)	1	0	1	Exclude file
Bin	(7)(18)	0	1	1	Exclude file
Bin	(7)(18)	1	0	1	Exclude file
Bin	(7)(17)	0	1	1	Exclude file
Bin	(7)(17)	1	0	1	Exclude file
Bin	(7)(16)	0	1	1	Exclude file
Bin	(7)(16)	1	0	1	Exclude file
Bin	(7)(15)	0	1	1	Exclude file
Bin	(7)(15)	1	0	1	Exclude file
Bin	(7)(14)	0	1	1	Exclude file
Bin	(7)(14)	1	0	1	Exclude file
Bin	(7)(13)	0	1	1	Exclude file
Bin	(7)(13)	1	0	1	Exclude file
Bin	(7)(12)	0	1	1	Exclude file
Bin	(7)(12)	1	0	1	Exclude file
Bin	(7)(11)	0	1	1	Exclude file
Bin	(7)(11)	1	0	1	Exclude file
Bin	(7)(10)	0	1	1	Exclude file
Bin	(7)(10)	1	0	1	Exclude file
Bin	(7)(9)	0	1	1	Exclude file
Bin	(7)(9)	1	0	1	Exclude file
Bin	(7)(8)	0	1	1	Exclude file
Bin	(7)(8)	1	0	1	Exclude file
Bin	(7)(7)	0	1	1	Exclude file
Bin	(7)(7)	1	0	1	Exclude file
Bin	(7)(6)	0	1	1	Exclude file
Bin	(7)(6)	1	0	1	Exclude file
Bin	(7)(5)	0	1	1	Exclude file
Bin	(7)(5)	1	0	1	Exclude file
Bin	(7)(4)	0	1	1	Exclude file
Bin	(7)(4)	1	0	1	Exclude file
Bin	(7)(3)	0	1	1	Exclude file
Bin	(7)(3)	1	0	1	Exclude file
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(31)	0	1	1	Exclude file
Bin	(6)(31)	1	0	1	Exclude file
Bin	(6)(30)	0	1	1	Exclude file
Bin	(6)(30)	1	0	1	Exclude file
Bin	(6)(29)	0	1	1	Exclude file
Bin	(6)(29)	1	0	1	Exclude file
Bin	(6)(28)	0	1	1	Exclude file
Bin	(6)(28)	1	0	1	Exclude file
Bin	(6)(27)	0	1	1	Exclude file
Bin	(6)(27)	1	0	1	Exclude file
Bin	(6)(26)	0	1	1	Exclude file
Bin	(6)(26)	1	0	1	Exclude file
Bin	(6)(25)	0	1	1	Exclude file
Bin	(6)(25)	1	0	1	Exclude file
Bin	(6)(24)	0	1	1	Exclude file
Bin	(6)(24)	1	0	1	Exclude file
Bin	(6)(23)	0	1	1	Exclude file
Bin	(6)(23)	1	0	1	Exclude file
Bin	(6)(22)	0	1	1	Exclude file
Bin	(6)(22)	1	0	1	Exclude file
Bin	(6)(21)	0	1	1	Exclude file
Bin	(6)(21)	1	0	1	Exclude file
Bin	(6)(20)	0	1	1	Exclude file
Bin	(6)(20)	1	0	1	Exclude file
Bin	(6)(19)	0	1	1	Exclude file
Bin	(6)(19)	1	0	1	Exclude file
Bin	(6)(18)	0	1	1	Exclude file
Bin	(6)(18)	1	0	1	Exclude file
Bin	(6)(17)	0	1	1	Exclude file
Bin	(6)(17)	1	0	1	Exclude file
Bin	(6)(16)	0	1	1	Exclude file
Bin	(6)(16)	1	0	1	Exclude file
Bin	(6)(15)	0	1	1	Exclude file
Bin	(6)(15)	1	0	1	Exclude file
Bin	(6)(14)	0	1	1	Exclude file
Bin	(6)(14)	1	0	1	Exclude file
Bin	(6)(13)	0	1	1	Exclude file
Bin	(6)(13)	1	0	1	Exclude file
Bin	(6)(12)	0	1	1	Exclude file
Bin	(6)(12)	1	0	1	Exclude file
Bin	(6)(11)	0	1	1	Exclude file
Bin	(6)(11)	1	0	1	Exclude file
Bin	(6)(10)	0	1	1	Exclude file
Bin	(6)(10)	1	0	1	Exclude file
Bin	(6)(9)	0	1	1	Exclude file
Bin	(6)(9)	1	0	1	Exclude file
Bin	(6)(8)	0	1	1	Exclude file
Bin	(6)(8)	1	0	1	Exclude file
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Bin	(6)(6)	0	1	1	Exclude file
Bin	(6)(6)	1	0	1	Exclude file
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Bin	(6)(5)	1	0	1	Exclude file
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Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
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Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
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Bin	(5)(31)	1	0	1	Exclude file
Bin	(5)(30)	0	1	1	Exclude file
Bin	(5)(30)	1	0	1	Exclude file
Bin	(5)(29)	0	1	1	Exclude file
Bin	(5)(29)	1	0	1	Exclude file
Bin	(5)(28)	0	1	1	Exclude file
Bin	(5)(28)	1	0	1	Exclude file
Bin	(5)(27)	0	1	1	Exclude file
Bin	(5)(27)	1	0	1	Exclude file
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Bin	(5)(23)	1	0	1	Exclude file
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Bin	(5)(21)	0	1	1	Exclude file
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Bin	(5)(20)	1	0	1	Exclude file
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Bin	(5)(17)	1	0	1	Exclude file
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Bin	(5)(16)	1	0	1	Exclude file
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Bin	(5)(9)	1	0	1	Exclude file
Bin	(5)(8)	0	1	1	Exclude file
Bin	(5)(8)	1	0	1	Exclude file
Bin	(5)(7)	0	1	1	Exclude file
Bin	(5)(7)	1	0	1	Exclude file
Bin	(5)(6)	0	1	1	Exclude file
Bin	(5)(6)	1	0	1	Exclude file
Bin	(5)(5)	0	1	1	Exclude file
Bin	(5)(5)	1	0	1	Exclude file
Bin	(5)(4)	0	1	1	Exclude file
Bin	(5)(4)	1	0	1	Exclude file
Bin	(5)(3)	0	1	1	Exclude file
Bin	(5)(3)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(31)	0	1	1	Exclude file
Bin	(4)(31)	1	0	1	Exclude file
Bin	(4)(30)	0	1	1	Exclude file
Bin	(4)(30)	1	0	1	Exclude file
Bin	(4)(29)	0	1	1	Exclude file
Bin	(4)(29)	1	0	1	Exclude file
Bin	(4)(28)	0	1	1	Exclude file
Bin	(4)(28)	1	0	1	Exclude file
Bin	(4)(27)	0	1	1	Exclude file
Bin	(4)(27)	1	0	1	Exclude file
Bin	(4)(26)	0	1	1	Exclude file
Bin	(4)(26)	1	0	1	Exclude file
Bin	(4)(25)	0	1	1	Exclude file
Bin	(4)(25)	1	0	1	Exclude file
Bin	(4)(24)	0	1	1	Exclude file
Bin	(4)(24)	1	0	1	Exclude file
Bin	(4)(23)	0	1	1	Exclude file
Bin	(4)(23)	1	0	1	Exclude file
Bin	(4)(22)	0	1	1	Exclude file
Bin	(4)(22)	1	0	1	Exclude file
Bin	(4)(21)	0	1	1	Exclude file
Bin	(4)(21)	1	0	1	Exclude file
Bin	(4)(20)	0	1	1	Exclude file
Bin	(4)(20)	1	0	1	Exclude file
Bin	(4)(19)	0	1	1	Exclude file
Bin	(4)(19)	1	0	1	Exclude file
Bin	(4)(18)	0	1	1	Exclude file
Bin	(4)(18)	1	0	1	Exclude file
Bin	(4)(17)	0	1	1	Exclude file
Bin	(4)(17)	1	0	1	Exclude file
Bin	(4)(16)	0	1	1	Exclude file
Bin	(4)(16)	1	0	1	Exclude file
Bin	(4)(15)	0	1	1	Exclude file
Bin	(4)(15)	1	0	1	Exclude file
Bin	(4)(14)	0	1	1	Exclude file
Bin	(4)(14)	1	0	1	Exclude file
Bin	(4)(13)	0	1	1	Exclude file
Bin	(4)(13)	1	0	1	Exclude file
Bin	(4)(12)	0	1	1	Exclude file
Bin	(4)(12)	1	0	1	Exclude file
Bin	(4)(11)	0	1	1	Exclude file
Bin	(4)(11)	1	0	1	Exclude file
Bin	(4)(10)	0	1	1	Exclude file
Bin	(4)(10)	1	0	1	Exclude file
Bin	(4)(9)	0	1	1	Exclude file
Bin	(4)(9)	1	0	1	Exclude file
Bin	(4)(8)	0	1	1	Exclude file
Bin	(4)(8)	1	0	1	Exclude file
Bin	(4)(7)	0	1	1	Exclude file
Bin	(4)(7)	1	0	1	Exclude file
Bin	(4)(6)	0	1	1	Exclude file
Bin	(4)(6)	1	0	1	Exclude file
Bin	(4)(5)	0	1	1	Exclude file
Bin	(4)(5)	1	0	1	Exclude file
Bin	(4)(4)	0	1	1	Exclude file
Bin	(4)(4)	1	0	1	Exclude file
Bin	(4)(3)	0	1	1	Exclude file
Bin	(4)(3)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(31)	0	1	1	Exclude file
Bin	(3)(31)	1	0	1	Exclude file
Bin	(3)(30)	0	1	1	Exclude file
Bin	(3)(30)	1	0	1	Exclude file
Bin	(3)(29)	0	1	1	Exclude file
Bin	(3)(29)	1	0	1	Exclude file
Bin	(3)(28)	0	1	1	Exclude file
Bin	(3)(28)	1	0	1	Exclude file
Bin	(3)(27)	0	1	1	Exclude file
Bin	(3)(27)	1	0	1	Exclude file
Bin	(3)(26)	0	1	1	Exclude file
Bin	(3)(26)	1	0	1	Exclude file
Bin	(3)(25)	0	1	1	Exclude file
Bin	(3)(25)	1	0	1	Exclude file
Bin	(3)(24)	0	1	1	Exclude file
Bin	(3)(24)	1	0	1	Exclude file
Bin	(3)(23)	0	1	1	Exclude file
Bin	(3)(23)	1	0	1	Exclude file
Bin	(3)(22)	0	1	1	Exclude file
Bin	(3)(22)	1	0	1	Exclude file
Bin	(3)(21)	0	1	1	Exclude file
Bin	(3)(21)	1	0	1	Exclude file
Bin	(3)(20)	0	1	1	Exclude file
Bin	(3)(20)	1	0	1	Exclude file
Bin	(3)(19)	0	1	1	Exclude file
Bin	(3)(19)	1	0	1	Exclude file
Bin	(3)(18)	0	1	1	Exclude file
Bin	(3)(18)	1	0	1	Exclude file
Bin	(3)(17)	0	1	1	Exclude file
Bin	(3)(17)	1	0	1	Exclude file
Bin	(3)(16)	0	1	1	Exclude file
Bin	(3)(16)	1	0	1	Exclude file
Bin	(3)(15)	0	1	1	Exclude file
Bin	(3)(15)	1	0	1	Exclude file
Bin	(3)(14)	0	1	1	Exclude file
Bin	(3)(14)	1	0	1	Exclude file
Bin	(3)(13)	0	1	1	Exclude file
Bin	(3)(13)	1	0	1	Exclude file
Bin	(3)(12)	0	1	1	Exclude file
Bin	(3)(12)	1	0	1	Exclude file
Bin	(3)(11)	0	1	1	Exclude file
Bin	(3)(11)	1	0	1	Exclude file
Bin	(3)(10)	0	1	1	Exclude file
Bin	(3)(10)	1	0	1	Exclude file
Bin	(3)(9)	0	1	1	Exclude file
Bin	(3)(9)	1	0	1	Exclude file
Bin	(3)(8)	0	1	1	Exclude file
Bin	(3)(8)	1	0	1	Exclude file
Bin	(3)(7)	0	1	1	Exclude file
Bin	(3)(7)	1	0	1	Exclude file
Bin	(3)(6)	0	1	1	Exclude file
Bin	(3)(6)	1	0	1	Exclude file
Bin	(3)(5)	0	1	1	Exclude file
Bin	(3)(5)	1	0	1	Exclude file
Bin	(3)(4)	0	1	1	Exclude file
Bin	(3)(4)	1	0	1	Exclude file
Bin	(3)(3)	0	1	1	Exclude file
Bin	(3)(3)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(31)	0	1	1	Exclude file
Bin	(2)(31)	1	0	1	Exclude file
Bin	(2)(30)	0	1	1	Exclude file
Bin	(2)(30)	1	0	1	Exclude file
Bin	(2)(29)	0	1	1	Exclude file
Bin	(2)(29)	1	0	1	Exclude file
Bin	(2)(28)	0	1	1	Exclude file
Bin	(2)(28)	1	0	1	Exclude file
Bin	(2)(27)	0	1	1	Exclude file
Bin	(2)(27)	1	0	1	Exclude file
Bin	(2)(26)	0	1	1	Exclude file
Bin	(2)(26)	1	0	1	Exclude file
Bin	(2)(25)	0	1	1	Exclude file
Bin	(2)(25)	1	0	1	Exclude file
Bin	(2)(24)	0	1	1	Exclude file
Bin	(2)(24)	1	0	1	Exclude file
Bin	(2)(23)	0	1	1	Exclude file
Bin	(2)(23)	1	0	1	Exclude file
Bin	(2)(22)	0	1	1	Exclude file
Bin	(2)(22)	1	0	1	Exclude file
Bin	(2)(21)	0	1	1	Exclude file
Bin	(2)(21)	1	0	1	Exclude file
Bin	(2)(20)	0	1	1	Exclude file
Bin	(2)(20)	1	0	1	Exclude file
Bin	(2)(19)	0	1	1	Exclude file
Bin	(2)(19)	1	0	1	Exclude file
Bin	(2)(18)	0	1	1	Exclude file
Bin	(2)(18)	1	0	1	Exclude file
Bin	(2)(17)	0	1	1	Exclude file
Bin	(2)(17)	1	0	1	Exclude file
Bin	(2)(16)	0	1	1	Exclude file
Bin	(2)(16)	1	0	1	Exclude file
Bin	(2)(15)	0	1	1	Exclude file
Bin	(2)(15)	1	0	1	Exclude file
Bin	(2)(14)	0	1	1	Exclude file
Bin	(2)(14)	1	0	1	Exclude file
Bin	(2)(13)	0	1	1	Exclude file
Bin	(2)(13)	1	0	1	Exclude file
Bin	(2)(12)	0	1	1	Exclude file
Bin	(2)(12)	1	0	1	Exclude file
Bin	(2)(11)	0	1	1	Exclude file
Bin	(2)(11)	1	0	1	Exclude file
Bin	(2)(10)	0	1	1	Exclude file
Bin	(2)(10)	1	0	1	Exclude file
Bin	(2)(9)	0	1	1	Exclude file
Bin	(2)(9)	1	0	1	Exclude file
Bin	(2)(8)	0	1	1	Exclude file
Bin	(2)(8)	1	0	1	Exclude file
Bin	(2)(7)	0	1	1	Exclude file
Bin	(2)(7)	1	0	1	Exclude file
Bin	(2)(6)	0	1	1	Exclude file
Bin	(2)(6)	1	0	1	Exclude file
Bin	(2)(5)	0	1	1	Exclude file
Bin	(2)(5)	1	0	1	Exclude file
Bin	(2)(4)	0	1	1	Exclude file
Bin	(2)(4)	1	0	1	Exclude file
Bin	(2)(3)	0	1	1	Exclude file
Bin	(2)(3)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(31)	0	1	1	Exclude file
Bin	(1)(31)	1	0	1	Exclude file
Bin	(1)(30)	0	1	1	Exclude file
Bin	(1)(30)	1	0	1	Exclude file
Bin	(1)(29)	0	1	1	Exclude file
Bin	(1)(29)	1	0	1	Exclude file
Bin	(1)(28)	0	1	1	Exclude file
Bin	(1)(28)	1	0	1	Exclude file
Bin	(1)(27)	0	1	1	Exclude file
Bin	(1)(27)	1	0	1	Exclude file
Bin	(1)(26)	0	1	1	Exclude file
Bin	(1)(26)	1	0	1	Exclude file
Bin	(1)(25)	0	1	1	Exclude file
Bin	(1)(25)	1	0	1	Exclude file
Bin	(1)(24)	0	1	1	Exclude file
Bin	(1)(24)	1	0	1	Exclude file
Bin	(1)(23)	0	1	1	Exclude file
Bin	(1)(23)	1	0	1	Exclude file
Bin	(1)(22)	0	1	1	Exclude file
Bin	(1)(22)	1	0	1	Exclude file
Bin	(1)(21)	0	1	1	Exclude file
Bin	(1)(21)	1	0	1	Exclude file
Bin	(1)(20)	0	1	1	Exclude file
Bin	(1)(20)	1	0	1	Exclude file
Bin	(1)(19)	0	1	1	Exclude file
Bin	(1)(19)	1	0	1	Exclude file
Bin	(1)(18)	0	1	1	Exclude file
Bin	(1)(18)	1	0	1	Exclude file
Bin	(1)(17)	0	1	1	Exclude file
Bin	(1)(17)	1	0	1	Exclude file
Bin	(1)(16)	0	1	1	Exclude file
Bin	(1)(16)	1	0	1	Exclude file
Bin	(1)(15)	0	1	1	Exclude file
Bin	(1)(15)	1	0	1	Exclude file
Bin	(1)(14)	0	1	1	Exclude file
Bin	(1)(14)	1	0	1	Exclude file
Bin	(1)(13)	0	1	1	Exclude file
Bin	(1)(13)	1	0	1	Exclude file
Bin	(1)(12)	0	1	1	Exclude file
Bin	(1)(12)	1	0	1	Exclude file
Bin	(1)(11)	0	1	1	Exclude file
Bin	(1)(11)	1	0	1	Exclude file
Bin	(1)(10)	0	1	1	Exclude file
Bin	(1)(10)	1	0	1	Exclude file
Bin	(1)(9)	0	1	1	Exclude file
Bin	(1)(9)	1	0	1	Exclude file
Bin	(1)(8)	0	1	1	Exclude file
Bin	(1)(8)	1	0	1	Exclude file
Bin	(1)(7)	0	1	1	Exclude file
Bin	(1)(7)	1	0	1	Exclude file
Bin	(1)(6)	0	1	1	Exclude file
Bin	(1)(6)	1	0	1	Exclude file
Bin	(1)(5)	0	1	1	Exclude file
Bin	(1)(5)	1	0	1	Exclude file
Bin	(1)(4)	0	1	1	Exclude file
Bin	(1)(4)	1	0	1	Exclude file
Bin	(1)(3)	0	1	1	Exclude file
Bin	(1)(3)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(31)	0	1	1	Exclude file
Bin	(0)(31)	1	0	1	Exclude file
Bin	(0)(30)	0	1	1	Exclude file
Bin	(0)(30)	1	0	1	Exclude file
Bin	(0)(29)	0	1	1	Exclude file
Bin	(0)(29)	1	0	1	Exclude file
Bin	(0)(28)	0	1	1	Exclude file
Bin	(0)(28)	1	0	1	Exclude file
Bin	(0)(27)	0	1	1	Exclude file
Bin	(0)(27)	1	0	1	Exclude file
Bin	(0)(26)	0	1	1	Exclude file
Bin	(0)(26)	1	0	1	Exclude file
Bin	(0)(25)	0	1	1	Exclude file
Bin	(0)(25)	1	0	1	Exclude file
Bin	(0)(24)	0	1	1	Exclude file
Bin	(0)(24)	1	0	1	Exclude file
Bin	(0)(23)	0	1	1	Exclude file
Bin	(0)(23)	1	0	1	Exclude file
Bin	(0)(22)	0	1	1	Exclude file
Bin	(0)(22)	1	0	1	Exclude file
Bin	(0)(21)	0	1	1	Exclude file
Bin	(0)(21)	1	0	1	Exclude file
Bin	(0)(20)	0	1	1	Exclude file
Bin	(0)(20)	1	0	1	Exclude file
Bin	(0)(19)	0	1	1	Exclude file
Bin	(0)(19)	1	0	1	Exclude file
Bin	(0)(18)	0	1	1	Exclude file
Bin	(0)(18)	1	0	1	Exclude file
Bin	(0)(17)	0	1	1	Exclude file
Bin	(0)(17)	1	0	1	Exclude file
Bin	(0)(16)	0	1	1	Exclude file
Bin	(0)(16)	1	0	1	Exclude file
Bin	(0)(15)	0	1	1	Exclude file
Bin	(0)(15)	1	0	1	Exclude file
Bin	(0)(14)	0	1	1	Exclude file
Bin	(0)(14)	1	0	1	Exclude file
Bin	(0)(13)	0	1	1	Exclude file
Bin	(0)(13)	1	0	1	Exclude file
Bin	(0)(12)	0	1	1	Exclude file
Bin	(0)(12)	1	0	1	Exclude file
Bin	(0)(11)	0	1	1	Exclude file
Bin	(0)(11)	1	0	1	Exclude file
Bin	(0)(10)	0	1	1	Exclude file
Bin	(0)(10)	1	0	1	Exclude file
Bin	(0)(9)	0	1	1	Exclude file
Bin	(0)(9)	1	0	1	Exclude file
Bin	(0)(8)	0	1	1	Exclude file
Bin	(0)(8)	1	0	1	Exclude file
Bin	(0)(7)	0	1	1	Exclude file
Bin	(0)(7)	1	0	1	Exclude file
Bin	(0)(6)	0	1	1	Exclude file
Bin	(0)(6)	1	0	1	Exclude file
Bin	(0)(5)	0	1	1	Exclude file
Bin	(0)(5)	1	0	1	Exclude file
Bin	(0)(4)	0	1	1	Exclude file
Bin	(0)(4)	1	0	1	Exclude file
Bin	(0)(3)	0	1	1	Exclude file
Bin	(0)(3)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

TXTB_AVAILABLE

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_ALLOW_BB

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PARITY_MISMATCH

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TTTM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_PRIORITY

	Element	From	To	Threshold	Excluded due to
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(2)	0	1	1	Exclude file
Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
Bin	(6)(1)	1	0	1	Exclude file
Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

TIMESTAMP

	Element	From	To	Threshold	Excluded due to
Bin	(63)	0	1	1	Exclude file
Bin	(63)	1	0	1	Exclude file
Bin	(62)	0	1	1	Exclude file
Bin	(62)	1	0	1	Exclude file
Bin	(61)	0	1	1	Exclude file
Bin	(61)	1	0	1	Exclude file
Bin	(60)	0	1	1	Exclude file
Bin	(60)	1	0	1	Exclude file
Bin	(59)	0	1	1	Exclude file
Bin	(59)	1	0	1	Exclude file
Bin	(58)	0	1	1	Exclude file
Bin	(58)	1	0	1	Exclude file
Bin	(57)	0	1	1	Exclude file
Bin	(57)	1	0	1	Exclude file
Bin	(56)	0	1	1	Exclude file
Bin	(56)	1	0	1	Exclude file
Bin	(55)	0	1	1	Exclude file
Bin	(55)	1	0	1	Exclude file
Bin	(54)	0	1	1	Exclude file
Bin	(54)	1	0	1	Exclude file
Bin	(53)	0	1	1	Exclude file
Bin	(53)	1	0	1	Exclude file
Bin	(52)	0	1	1	Exclude file
Bin	(52)	1	0	1	Exclude file
Bin	(51)	0	1	1	Exclude file
Bin	(51)	1	0	1	Exclude file
Bin	(50)	0	1	1	Exclude file
Bin	(50)	1	0	1	Exclude file
Bin	(49)	0	1	1	Exclude file
Bin	(49)	1	0	1	Exclude file
Bin	(48)	0	1	1	Exclude file
Bin	(48)	1	0	1	Exclude file
Bin	(47)	0	1	1	Exclude file
Bin	(47)	1	0	1	Exclude file
Bin	(46)	0	1	1	Exclude file
Bin	(46)	1	0	1	Exclude file
Bin	(45)	0	1	1	Exclude file
Bin	(45)	1	0	1	Exclude file
Bin	(44)	0	1	1	Exclude file
Bin	(44)	1	0	1	Exclude file
Bin	(43)	0	1	1	Exclude file
Bin	(43)	1	0	1	Exclude file
Bin	(42)	0	1	1	Exclude file
Bin	(42)	1	0	1	Exclude file
Bin	(41)	0	1	1	Exclude file
Bin	(41)	1	0	1	Exclude file
Bin	(40)	0	1	1	Exclude file
Bin	(40)	1	0	1	Exclude file
Bin	(39)	0	1	1	Exclude file
Bin	(39)	1	0	1	Exclude file
Bin	(38)	0	1	1	Exclude file
Bin	(38)	1	0	1	Exclude file
Bin	(37)	0	1	1	Exclude file
Bin	(37)	1	0	1	Exclude file
Bin	(36)	0	1	1	Exclude file
Bin	(36)	1	0	1	Exclude file
Bin	(35)	0	1	1	Exclude file
Bin	(35)	1	0	1	Exclude file
Bin	(34)	0	1	1	Exclude file
Bin	(34)	1	0	1	Exclude file
Bin	(33)	0	1	1	Exclude file
Bin	(33)	1	0	1	Exclude file
Bin	(32)	0	1	1	Exclude file
Bin	(32)	1	0	1	Exclude file
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold
Bin	(4)	0	1	27262	1
Bin	(4)	1	0	28863	1
Bin	(3)	0	1	3825	1
Bin	(3)	1	0	5426	1
Bin	(2)	0	1	46672	1
Bin	(2)	1	0	48273	1
Bin	(1)	0	1	38173	1
Bin	(1)	1	0	38177	1
Bin	(0)	0	1	102582	1
Bin	(0)	1	0	104179	1

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold
Bin	0	1	106192	1
Bin	1	0	107793	1

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold
Bin	0	1	183809	1
Bin	1	0	185410	1

Port:

TXTB_IS_BB

	Element	From	To	Count	Threshold
Bin	(3)	0	1	7	1
Bin	(3)	1	0	234	1
Bin	(2)	0	1	6	1
Bin	(2)	1	0	235	1
Bin	(1)	0	1	39	1
Bin	(1)	1	0	875	1
Bin	(0)	0	1	87	1
Bin	(0)	1	0	1792	1

Port:

TRAN_WORD

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8376	1
Bin	(31)	1	0	9977	1
Bin	(30)	0	1	8561	1
Bin	(30)	1	0	10162	1
Bin	(29)	0	1	8142	1
Bin	(29)	1	0	9743	1
Bin	(28)	0	1	26007	1
Bin	(28)	1	0	27608	1
Bin	(27)	0	1	21693	1
Bin	(27)	1	0	23294	1
Bin	(26)	0	1	25772	1
Bin	(26)	1	0	27373	1
Bin	(25)	0	1	21893	1
Bin	(25)	1	0	23494	1
Bin	(24)	0	1	26638	1
Bin	(24)	1	0	28239	1
Bin	(23)	0	1	22559	1
Bin	(23)	1	0	24160	1
Bin	(22)	0	1	26443	1
Bin	(22)	1	0	28044	1
Bin	(21)	0	1	22115	1
Bin	(21)	1	0	23716	1
Bin	(20)	0	1	26193	1
Bin	(20)	1	0	27794	1
Bin	(19)	0	1	23117	1
Bin	(19)	1	0	24718	1
Bin	(18)	0	1	26236	1
Bin	(18)	1	0	27837	1
Bin	(17)	0	1	15043	1
Bin	(17)	1	0	16644	1
Bin	(16)	0	1	15226	1
Bin	(16)	1	0	16827	1
Bin	(15)	0	1	15010	1
Bin	(15)	1	0	16611	1
Bin	(14)	0	1	15577	1
Bin	(14)	1	0	17178	1
Bin	(13)	0	1	15548	1
Bin	(13)	1	0	17149	1
Bin	(12)	0	1	15770	1
Bin	(12)	1	0	17371	1
Bin	(11)	0	1	16048	1
Bin	(11)	1	0	17649	1
Bin	(10)	0	1	17948	1
Bin	(10)	1	0	19549	1
Bin	(9)	0	1	25142	1
Bin	(9)	1	0	26743	1
Bin	(8)	0	1	16245	1
Bin	(8)	1	0	17846	1
Bin	(7)	0	1	35636	1
Bin	(7)	1	0	37237	1
Bin	(6)	0	1	26492	1
Bin	(6)	1	0	28093	1
Bin	(5)	0	1	19634	1
Bin	(5)	1	0	21235	1
Bin	(4)	0	1	18379	1
Bin	(4)	1	0	19980	1
Bin	(3)	0	1	26281	1
Bin	(3)	1	0	27882	1
Bin	(2)	0	1	27751	1
Bin	(2)	1	0	29352	1
Bin	(1)	0	1	29032	1
Bin	(1)	1	0	30633	1
Bin	(0)	0	1	36401	1
Bin	(0)	1	0	38002	1

Port:

TRAN_DLC

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1588	1
Bin	(3)	1	0	3188	1
Bin	(2)	0	1	2002	1
Bin	(2)	1	0	3601	1
Bin	(1)	0	1	1972	1
Bin	(1)	1	0	3571	1
Bin	(0)	0	1	3613	1
Bin	(0)	1	0	5214	1

Port:

TRAN_IS_RTR

	From	To	Count	Threshold
Bin	0	1	1146	1
Bin	1	0	2745	1

Port:

TRAN_IDENT_TYPE

	From	To	Count	Threshold
Bin	0	1	2544	1
Bin	1	0	4144	1

Port:

TRAN_FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	2743	1
Bin	1	0	4344	1

Port:

TRAN_BRS

	From	To	Count	Threshold
Bin	0	1	1983	1
Bin	1	0	3584	1

Port:

TRAN_IDENTIFIER

	Element	From	To	Count	Threshold
Bin	(28)	0	1	3910	1
Bin	(28)	1	0	5449	1
Bin	(27)	0	1	3888	1
Bin	(27)	1	0	5508	1
Bin	(26)	0	1	3909	1
Bin	(26)	1	0	5442	1
Bin	(25)	0	1	4137	1
Bin	(25)	1	0	5757	1
Bin	(24)	0	1	3899	1
Bin	(24)	1	0	5435	1
Bin	(23)	0	1	4144	1
Bin	(23)	1	0	5757	1
Bin	(22)	0	1	3834	1
Bin	(22)	1	0	5450	1
Bin	(21)	0	1	4219	1
Bin	(21)	1	0	5769	1
Bin	(20)	0	1	3872	1
Bin	(20)	1	0	5494	1
Bin	(19)	0	1	4249	1
Bin	(19)	1	0	5796	1
Bin	(18)	0	1	3780	1
Bin	(18)	1	0	5402	1
Bin	(17)	0	1	1690	1
Bin	(17)	1	0	9492	1
Bin	(16)	0	1	1685	1
Bin	(16)	1	0	9549	1
Bin	(15)	0	1	1736	1
Bin	(15)	1	0	9638	1
Bin	(14)	0	1	1640	1
Bin	(14)	1	0	9457	1
Bin	(13)	0	1	1691	1
Bin	(13)	1	0	9563	1
Bin	(12)	0	1	1656	1
Bin	(12)	1	0	9537	1
Bin	(11)	0	1	1722	1
Bin	(11)	1	0	9686	1
Bin	(10)	0	1	1652	1
Bin	(10)	1	0	9432	1
Bin	(9)	0	1	1690	1
Bin	(9)	1	0	9552	1
Bin	(8)	0	1	1672	1
Bin	(8)	1	0	9517	1
Bin	(7)	0	1	1722	1
Bin	(7)	1	0	9503	1
Bin	(6)	0	1	1638	1
Bin	(6)	1	0	9444	1
Bin	(5)	0	1	1684	1
Bin	(5)	1	0	9459	1
Bin	(4)	0	1	1710	1
Bin	(4)	1	0	9634	1
Bin	(3)	0	1	1706	1
Bin	(3)	1	0	9610	1
Bin	(2)	0	1	1690	1
Bin	(2)	1	0	9572	1
Bin	(1)	0	1	1707	1
Bin	(1)	1	0	9621	1
Bin	(0)	0	1	1658	1
Bin	(0)	1	0	9460	1

Port:

TRAN_FRAME_TEST

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	74	1
Bin	TPRM(4)	1	0	3283	1
Bin	TPRM(3)	0	1	169	1
Bin	TPRM(3)	1	0	1814	1
Bin	TPRM(2)	0	1	246	1
Bin	TPRM(2)	1	0	1891	1
Bin	TPRM(1)	0	1	458	1
Bin	TPRM(1)	1	0	2103	1
Bin	TPRM(0)	0	1	645	1
Bin	TPRM(0)	1	0	2290	1

Port:

TRAN_FRAME_VALID

	From	To	Count	Threshold
Bin	0	1	25532	1
Bin	1	0	27133	1

Port:

TRAN_FRAME_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	728	1
Bin	1	0	2329	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25275	1
Bin	LOCK	1	0	26876	1
Bin	VALID	0	1	11112	1
Bin	VALID	1	0	12713	1
Bin	ERR	0	1	4262	1
Bin	ERR	1	0	5863	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9436	1
Bin	FAILED	1	0	11037	1

Port:

TXTB_CHANGED

	From	To	Count	Threshold
Bin	0	1	10020	1
Bin	1	0	11621	1

Port:

TXTB_HW_CMD_CS

	Element	From	To	Count	Threshold
Bin	(7)	0	1	72	1
Bin	(7)	1	0	867	1
Bin	(6)	0	1	74	1
Bin	(6)	1	0	865	1
Bin	(5)	0	1	72	1
Bin	(5)	1	0	867	1
Bin	(4)	0	1	77	1
Bin	(4)	1	0	862	1
Bin	(3)	0	1	363	1
Bin	(3)	1	0	2729	1
Bin	(2)	0	1	306	1
Bin	(2)	1	0	2786	1
Bin	(1)	0	1	5601	1
Bin	(1)	1	0	8382	1
Bin	(0)	0	1	7418	1
Bin	(0)	1	0	6565	1

Port:

CURR_TXTB_INDEX

	Element	From	To	Count	Threshold
Bin	(2)	0	1	124	1
Bin	(2)	1	0	1725	1
Bin	(1)	0	1	521	1
Bin	(1)	1	0	2122	1
Bin	(0)	0	1	6025	1
Bin	(0)	1	0	7626	1

Signal:

SELECT_BUF_AVAIL

	From	To	Count	Threshold
Bin	0	1	26988	1
Bin	1	0	28589	1

Signal:

TXTB_SELECTED_INPUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8376	1
Bin	(31)	1	0	9977	1
Bin	(30)	0	1	8561	1
Bin	(30)	1	0	10162	1
Bin	(29)	0	1	8142	1
Bin	(29)	1	0	9743	1
Bin	(28)	0	1	26007	1
Bin	(28)	1	0	27608	1
Bin	(27)	0	1	21693	1
Bin	(27)	1	0	23294	1
Bin	(26)	0	1	25772	1
Bin	(26)	1	0	27373	1
Bin	(25)	0	1	21893	1
Bin	(25)	1	0	23494	1
Bin	(24)	0	1	26638	1
Bin	(24)	1	0	28239	1
Bin	(23)	0	1	22559	1
Bin	(23)	1	0	24160	1
Bin	(22)	0	1	26443	1
Bin	(22)	1	0	28044	1
Bin	(21)	0	1	22115	1
Bin	(21)	1	0	23716	1
Bin	(20)	0	1	26193	1
Bin	(20)	1	0	27794	1
Bin	(19)	0	1	23117	1
Bin	(19)	1	0	24718	1
Bin	(18)	0	1	26236	1
Bin	(18)	1	0	27837	1
Bin	(17)	0	1	15043	1
Bin	(17)	1	0	16644	1
Bin	(16)	0	1	15226	1
Bin	(16)	1	0	16827	1
Bin	(15)	0	1	15010	1
Bin	(15)	1	0	16611	1
Bin	(14)	0	1	15577	1
Bin	(14)	1	0	17178	1
Bin	(13)	0	1	15548	1
Bin	(13)	1	0	17149	1
Bin	(12)	0	1	15770	1
Bin	(12)	1	0	17371	1
Bin	(11)	0	1	16048	1
Bin	(11)	1	0	17649	1
Bin	(10)	0	1	17948	1
Bin	(10)	1	0	19549	1
Bin	(9)	0	1	25142	1
Bin	(9)	1	0	26743	1
Bin	(8)	0	1	16245	1
Bin	(8)	1	0	17846	1
Bin	(7)	0	1	35636	1
Bin	(7)	1	0	37237	1
Bin	(6)	0	1	26492	1
Bin	(6)	1	0	28093	1
Bin	(5)	0	1	19634	1
Bin	(5)	1	0	21235	1
Bin	(4)	0	1	18379	1
Bin	(4)	1	0	19980	1
Bin	(3)	0	1	26281	1
Bin	(3)	1	0	27882	1
Bin	(2)	0	1	27751	1
Bin	(2)	1	0	29352	1
Bin	(1)	0	1	29032	1
Bin	(1)	1	0	30633	1
Bin	(0)	0	1	36401	1
Bin	(0)	1	0	38002	1

Signal:

TXTB_TIMESTAMP

	Element	From	To	Count	Threshold
Bin	(63)	0	1	8376	1
Bin	(63)	1	0	9977	1
Bin	(62)	0	1	8561	1
Bin	(62)	1	0	10162	1
Bin	(61)	0	1	8142	1
Bin	(61)	1	0	9743	1
Bin	(60)	0	1	26007	1
Bin	(60)	1	0	27608	1
Bin	(59)	0	1	21693	1
Bin	(59)	1	0	23294	1
Bin	(58)	0	1	25772	1
Bin	(58)	1	0	27373	1
Bin	(57)	0	1	21893	1
Bin	(57)	1	0	23494	1
Bin	(56)	0	1	26638	1
Bin	(56)	1	0	28239	1
Bin	(55)	0	1	22559	1
Bin	(55)	1	0	24160	1
Bin	(54)	0	1	26443	1
Bin	(54)	1	0	28044	1
Bin	(53)	0	1	22115	1
Bin	(53)	1	0	23716	1
Bin	(52)	0	1	26193	1
Bin	(52)	1	0	27794	1
Bin	(51)	0	1	23117	1
Bin	(51)	1	0	24718	1
Bin	(50)	0	1	26236	1
Bin	(50)	1	0	27837	1
Bin	(49)	0	1	15043	1
Bin	(49)	1	0	16644	1
Bin	(48)	0	1	15226	1
Bin	(48)	1	0	16827	1
Bin	(47)	0	1	15010	1
Bin	(47)	1	0	16611	1
Bin	(46)	0	1	15577	1
Bin	(46)	1	0	17178	1
Bin	(45)	0	1	15548	1
Bin	(45)	1	0	17149	1
Bin	(44)	0	1	15770	1
Bin	(44)	1	0	17371	1
Bin	(43)	0	1	16048	1
Bin	(43)	1	0	17649	1
Bin	(42)	0	1	17948	1
Bin	(42)	1	0	19549	1
Bin	(41)	0	1	25142	1
Bin	(41)	1	0	26743	1
Bin	(40)	0	1	16245	1
Bin	(40)	1	0	17846	1
Bin	(39)	0	1	35636	1
Bin	(39)	1	0	37237	1
Bin	(38)	0	1	26492	1
Bin	(38)	1	0	28093	1
Bin	(37)	0	1	19634	1
Bin	(37)	1	0	21235	1
Bin	(36)	0	1	18379	1
Bin	(36)	1	0	19980	1
Bin	(35)	0	1	26281	1
Bin	(35)	1	0	27882	1
Bin	(34)	0	1	27751	1
Bin	(34)	1	0	29352	1
Bin	(33)	0	1	29032	1
Bin	(33)	1	0	30633	1
Bin	(32)	0	1	36401	1
Bin	(32)	1	0	38002	1
Bin	(31)	0	1	15	1
Bin	(31)	1	0	1616	1
Bin	(30)	0	1	15	1
Bin	(30)	1	0	1616	1
Bin	(29)	0	1	21	1
Bin	(29)	1	0	1622	1
Bin	(28)	0	1	14	1
Bin	(28)	1	0	1615	1
Bin	(27)	0	1	18	1
Bin	(27)	1	0	1619	1
Bin	(26)	0	1	17	1
Bin	(26)	1	0	1618	1
Bin	(25)	0	1	23	1
Bin	(25)	1	0	1624	1
Bin	(24)	0	1	17	1
Bin	(24)	1	0	1618	1
Bin	(23)	0	1	16	1
Bin	(23)	1	0	1617	1
Bin	(22)	0	1	19	1
Bin	(22)	1	0	1620	1
Bin	(21)	0	1	12	1
Bin	(21)	1	0	1613	1
Bin	(20)	0	1	12	1
Bin	(20)	1	0	1613	1
Bin	(19)	0	1	10	1
Bin	(19)	1	0	1611	1
Bin	(18)	0	1	21	1
Bin	(18)	1	0	1622	1
Bin	(17)	0	1	22	1
Bin	(17)	1	0	1623	1
Bin	(16)	0	1	27	1
Bin	(16)	1	0	1628	1
Bin	(15)	0	1	25	1
Bin	(15)	1	0	1626	1
Bin	(14)	0	1	31	1
Bin	(14)	1	0	1632	1
Bin	(13)	0	1	52	1
Bin	(13)	1	0	1653	1
Bin	(12)	0	1	70	1
Bin	(12)	1	0	1671	1
Bin	(11)	0	1	53	1
Bin	(11)	1	0	1654	1
Bin	(10)	0	1	71	1
Bin	(10)	1	0	1672	1
Bin	(9)	0	1	63	1
Bin	(9)	1	0	1664	1
Bin	(8)	0	1	58	1
Bin	(8)	1	0	1659	1
Bin	(7)	0	1	70	1
Bin	(7)	1	0	1671	1
Bin	(6)	0	1	78	1
Bin	(6)	1	0	1679	1
Bin	(5)	0	1	64	1
Bin	(5)	1	0	1665	1
Bin	(4)	0	1	71	1
Bin	(4)	1	0	1672	1
Bin	(3)	0	1	73	1
Bin	(3)	1	0	1674	1
Bin	(2)	0	1	56	1
Bin	(2)	1	0	1657	1
Bin	(1)	0	1	57	1
Bin	(1)	1	0	1658	1
Bin	(0)	0	1	53	1
Bin	(0)	1	0	1654	1

Signal:

TIMESTAMP_VALID

	From	To	Count	Threshold
Bin	0	1	1815	1
Bin	1	0	214	1

Signal:

SELECT_INDEX_CHANGED

	From	To	Count	Threshold
Bin	0	1	46073	1
Bin	1	0	46084	1

Signal:

VALIDATED_BUFFER

	From	To	Count	Threshold
Bin	0	1	25508	1
Bin	1	0	27109	1

Signal:

TXTB_CLK_EN_Q

	From	To	Count	Threshold
Bin	0	1	79820	1
Bin	1	0	81421	1

Signal:

TX_ARB_PARITY_CHECK_VALID

	From	To	Count	Threshold
Bin	0	1	103989	1
Bin	1	0	105590	1

Signal:

TS_LOW_INTERNAL

	Element	From	To	Count	Threshold
Bin	(31)	0	1	15	1
Bin	(31)	1	0	1616	1
Bin	(30)	0	1	15	1
Bin	(30)	1	0	1616	1
Bin	(29)	0	1	21	1
Bin	(29)	1	0	1622	1
Bin	(28)	0	1	14	1
Bin	(28)	1	0	1615	1
Bin	(27)	0	1	18	1
Bin	(27)	1	0	1619	1
Bin	(26)	0	1	17	1
Bin	(26)	1	0	1618	1
Bin	(25)	0	1	23	1
Bin	(25)	1	0	1624	1
Bin	(24)	0	1	17	1
Bin	(24)	1	0	1618	1
Bin	(23)	0	1	16	1
Bin	(23)	1	0	1617	1
Bin	(22)	0	1	19	1
Bin	(22)	1	0	1620	1
Bin	(21)	0	1	12	1
Bin	(21)	1	0	1613	1
Bin	(20)	0	1	12	1
Bin	(20)	1	0	1613	1
Bin	(19)	0	1	10	1
Bin	(19)	1	0	1611	1
Bin	(18)	0	1	21	1
Bin	(18)	1	0	1622	1
Bin	(17)	0	1	22	1
Bin	(17)	1	0	1623	1
Bin	(16)	0	1	27	1
Bin	(16)	1	0	1628	1
Bin	(15)	0	1	25	1
Bin	(15)	1	0	1626	1
Bin	(14)	0	1	31	1
Bin	(14)	1	0	1632	1
Bin	(13)	0	1	52	1
Bin	(13)	1	0	1653	1
Bin	(12)	0	1	70	1
Bin	(12)	1	0	1671	1
Bin	(11)	0	1	53	1
Bin	(11)	1	0	1654	1
Bin	(10)	0	1	71	1
Bin	(10)	1	0	1672	1
Bin	(9)	0	1	63	1
Bin	(9)	1	0	1664	1
Bin	(8)	0	1	58	1
Bin	(8)	1	0	1659	1
Bin	(7)	0	1	70	1
Bin	(7)	1	0	1671	1
Bin	(6)	0	1	78	1
Bin	(6)	1	0	1679	1
Bin	(5)	0	1	64	1
Bin	(5)	1	0	1665	1
Bin	(4)	0	1	71	1
Bin	(4)	1	0	1672	1
Bin	(3)	0	1	73	1
Bin	(3)	1	0	1674	1
Bin	(2)	0	1	56	1
Bin	(2)	1	0	1657	1
Bin	(1)	0	1	57	1
Bin	(1)	1	0	1658	1
Bin	(0)	0	1	53	1
Bin	(0)	1	0	1654	1

Signal:

TRAN_DLC_DBL_BUF

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1601	1
Bin	(3)	1	0	3201	1
Bin	(2)	0	1	2020	1
Bin	(2)	1	0	3619	1
Bin	(1)	0	1	1986	1
Bin	(1)	1	0	3585	1
Bin	(0)	0	1	3630	1
Bin	(0)	1	0	5231	1

Signal:

TRAN_IS_RTR_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	1166	1
Bin	1	0	2765	1

Signal:

TRAN_IDENT_TYPE_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	2570	1
Bin	1	0	4170	1

Signal:

TRAN_FRAME_TYPE_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	2770	1
Bin	1	0	4371	1

Signal:

TRAN_BRS_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	2007	1
Bin	1	0	3608	1

Signal:

TRAN_FRAME_TEST_DBL_BUF

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	50	1
Bin	TPRM(4)	1	0	1651	1
Bin	TPRM(3)	0	1	169	1
Bin	TPRM(3)	1	0	1770	1
Bin	TPRM(2)	0	1	246	1
Bin	TPRM(2)	1	0	1847	1
Bin	TPRM(1)	0	1	458	1
Bin	TPRM(1)	1	0	2059	1
Bin	TPRM(0)	0	1	645	1
Bin	TPRM(0)	1	0	2246	1

Signal:

TRAN_DLC_COM

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1588	1
Bin	(3)	1	0	3188	1
Bin	(2)	0	1	2002	1
Bin	(2)	1	0	3601	1
Bin	(1)	0	1	1972	1
Bin	(1)	1	0	3571	1
Bin	(0)	0	1	3613	1
Bin	(0)	1	0	5214	1

Signal:

TRAN_IS_RTR_COM

	From	To	Count	Threshold
Bin	0	1	1146	1
Bin	1	0	2745	1

Signal:

TRAN_IDENT_TYPE_COM

	From	To	Count	Threshold
Bin	0	1	2544	1
Bin	1	0	4144	1

Signal:

TRAN_FRAME_TYPE_COM

	From	To	Count	Threshold
Bin	0	1	2743	1
Bin	1	0	4344	1

Signal:

TRAN_BRS_COM

	From	To	Count	Threshold
Bin	0	1	1983	1
Bin	1	0	3584	1

Signal:

TRAN_FRAME_VALID_COM

	From	To	Count	Threshold
Bin	0	1	25503	1
Bin	1	0	27104	1

Signal:

TRAN_IDENTIFIER_COM

	Element	From	To	Count	Threshold
Bin	(28)	0	1	3820	1
Bin	(28)	1	0	5419	1
Bin	(27)	0	1	3883	1
Bin	(27)	1	0	5483	1
Bin	(26)	0	1	3817	1
Bin	(26)	1	0	5415	1
Bin	(25)	0	1	4129	1
Bin	(25)	1	0	5729	1
Bin	(24)	0	1	3806	1
Bin	(24)	1	0	5406	1
Bin	(23)	0	1	4134	1
Bin	(23)	1	0	5734	1
Bin	(22)	0	1	3824	1
Bin	(22)	1	0	5423	1
Bin	(21)	0	1	4128	1
Bin	(21)	1	0	5728	1
Bin	(20)	0	1	3868	1
Bin	(20)	1	0	5469	1
Bin	(19)	0	1	4160	1
Bin	(19)	1	0	5758	1
Bin	(18)	0	1	3777	1
Bin	(18)	1	0	5375	1
Bin	(17)	0	1	1685	1
Bin	(17)	1	0	3286	1
Bin	(16)	0	1	1680	1
Bin	(16)	1	0	3281	1
Bin	(15)	0	1	1732	1
Bin	(15)	1	0	3333	1
Bin	(14)	0	1	1640	1
Bin	(14)	1	0	3241	1
Bin	(13)	0	1	1691	1
Bin	(13)	1	0	3291	1
Bin	(12)	0	1	1656	1
Bin	(12)	1	0	3257	1
Bin	(11)	0	1	1721	1
Bin	(11)	1	0	3321	1
Bin	(10)	0	1	1648	1
Bin	(10)	1	0	3248	1
Bin	(9)	0	1	1686	1
Bin	(9)	1	0	3287	1
Bin	(8)	0	1	1667	1
Bin	(8)	1	0	3268	1
Bin	(7)	0	1	1718	1
Bin	(7)	1	0	3319	1
Bin	(6)	0	1	1637	1
Bin	(6)	1	0	3238	1
Bin	(5)	0	1	1683	1
Bin	(5)	1	0	3283	1
Bin	(4)	0	1	1710	1
Bin	(4)	1	0	3310	1
Bin	(3)	0	1	1706	1
Bin	(3)	1	0	3307	1
Bin	(2)	0	1	1686	1
Bin	(2)	1	0	3286	1
Bin	(1)	0	1	1703	1
Bin	(1)	1	0	3304	1
Bin	(0)	0	1	1654	1
Bin	(0)	1	0	3254	1

Signal:

LOAD_TS_LW_ADDR

	From	To	Count	Threshold
Bin	0	1	28775	1
Bin	1	0	30376	1

Signal:

LOAD_TS_UW_ADDR

	From	To	Count	Threshold
Bin	0	1	26350	1
Bin	1	0	27951	1

Signal:

LOAD_FFMT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25960	1
Bin	1	0	27561	1

Signal:

LOAD_IDENT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25847	1
Bin	1	0	27448	1

Signal:

LOAD_FRAME_TEST_W_ADDR

	From	To	Count	Threshold
Bin	0	1	26174	1
Bin	1	0	27775	1

Signal:

STORE_TS_L_W

	From	To	Count	Threshold
Bin	0	1	26350	1
Bin	1	0	27951	1

Signal:

COMMIT_DBL_BUFS

	From	To	Count	Threshold
Bin	0	1	25922	1
Bin	1	0	27523	1

Signal:

BUFFER_MD_W

	From	To	Count	Threshold
Bin	0	1	25847	1
Bin	1	0	27448	1

Signal:

BUFFER_FRAME_TEST_W

	From	To	Count	Threshold
Bin	0	1	25960	1
Bin	1	0	27561	1

Signal:

STORE_LAST_TXTB_INDEX

	From	To	Count	Threshold
Bin	0	1	25275	1
Bin	1	0	26876	1

Signal:

FRAME_VALID_COM_SET

	From	To	Count	Threshold
Bin	0	1	25922	1
Bin	1	0	27523	1

Signal:

FRAME_VALID_COM_CLEAR

	From	To	Count	Threshold
Bin	0	1	26018	1
Bin	1	0	27619	1

Signal:

TX_ARB_LOCKED

	From	To	Count	Threshold
Bin	0	1	25275	1
Bin	1	0	26876	1

Signal:

TXTB_META_CLK_EN

	From	To	Count	Threshold
Bin	0	1	26372	1
Bin	1	0	27973	1

Signal:

MR_TX_PRIORITY_TXBBM

	Element	From	To	Count	Threshold
Bin	(7)(2)	0	1	65	1
Bin	(7)(2)	1	0	303	1
Bin	(7)(1)	0	1	71	1
Bin	(7)(1)	1	0	365	1
Bin	(7)(0)	0	1	73	1
Bin	(7)(0)	1	0	360	1
Bin	(6)(2)	0	1	65	1
Bin	(6)(2)	1	0	306	1
Bin	(6)(1)	0	1	78	1
Bin	(6)(1)	1	0	307	1
Bin	(6)(0)	0	1	83	1
Bin	(6)(0)	1	0	325	1
Bin	(5)(2)	0	1	93	1
Bin	(5)(2)	1	0	346	1
Bin	(5)(1)	0	1	73	1
Bin	(5)(1)	1	0	333	1
Bin	(5)(0)	0	1	99	1
Bin	(5)(0)	1	0	342	1
Bin	(4)(2)	0	1	67	1
Bin	(4)(2)	1	0	268	1
Bin	(4)(1)	0	1	99	1
Bin	(4)(1)	1	0	311	1
Bin	(4)(0)	0	1	100	1
Bin	(4)(0)	1	0	283	1
Bin	(3)(2)	0	1	151	1
Bin	(3)(2)	1	0	985	1
Bin	(3)(1)	0	1	163	1
Bin	(3)(1)	1	0	1053	1
Bin	(3)(0)	0	1	227	1
Bin	(3)(0)	1	0	1063	1
Bin	(2)(2)	0	1	171	1
Bin	(2)(2)	1	0	945	1
Bin	(2)(1)	0	1	242	1
Bin	(2)(1)	1	0	1064	1
Bin	(2)(0)	0	1	275	1
Bin	(2)(0)	1	0	982	1
Bin	(1)(2)	0	1	255	1
Bin	(1)(2)	1	0	1824	1
Bin	(1)(1)	0	1	315	1
Bin	(1)(1)	1	0	1932	1
Bin	(1)(0)	0	1	337	1
Bin	(1)(0)	1	0	1900	1
Bin	(0)(2)	0	1	323	1
Bin	(0)(2)	1	0	1867	1
Bin	(0)(1)	0	1	302	1
Bin	(0)(1)	1	0	1975	1
Bin	(0)(0)	0	1	1998	1
Bin	(0)(0)	1	0	350	1

Signal:

TXTB_PARITY_MISMATCH_VLD

	From	To	Count	Threshold
Bin	0	1	2261	1
Bin	1	0	3862	1

Signal:

TXTB_PARITY_MISMATCH_TX

	From	To	Count	Threshold
Bin	0	1	2384	1
Bin	1	0	3985	1

Signal:

TXTB_HW_CMD_UNLOCK

	From	To	Count	Threshold
Bin	0	1	25265	1
Bin	1	0	26866	1

Uncovered expressions:

"or" expression on lines 354 to 356:

 (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or ((a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0)))) 
  <------------------------LHS------------------------>      <--------------------------------------------RHS-------------------------------------------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	True	False	0	1

"and" expression on lines 355 to 356:

 (a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))) 
  <--------------LHS-------------->       <-----------------------RHS----------------------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1

Excluded expressions:

"or" expression on lines 354 to 356:

 (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or ((a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0)))) 
  <------------------------LHS------------------------>      <--------------------------------------------RHS-------------------------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression on lines 355 to 356:

 (a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))) 
  <--------------LHS-------------->       <-----------------------RHS----------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"or" expression on lines 354 to 356:

 (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or ((a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0)))) 
  <------------------------LHS------------------------>      <--------------------------------------------RHS-------------------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	440460	1
Bin	False	True	753	1

"and" expression on lines 355 to 356:

 (a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))) 
  <--------------LHS-------------->       <-----------------------RHS----------------------->

	LHS	RHS	Count	Threshold
Bin	True	False	392015	1
Bin	True	True	753	1

"=" expression on line 444:

mr_mode_tttm = TTTM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	544376836	1
Bin	True	785501	1

"and" expression on lines 454 to 455:

 (txtb_available(curr_txtb_index_i) = '1') and (tran_frame_valid_com = '1') 
  <-----------------LHS----------------->       <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	25616	1
Bin	True	False	16396	1
Bin	True	True	25944	1

"=" expression on line 454:

txtb_available(curr_txtb_index_i) = '1'

	Evaluated to	Count	Threshold
Bin	False	68261	1
Bin	True	42340	1

"=" expression on line 455:

tran_frame_valid_com = '1'

	Evaluated to	Count	Threshold
Bin	False	59041	1
Bin	True	51560	1

"or" expression on line 459:

 (validated_buffer = '1') or (tx_arb_locked = '1') 
  <--------LHS--------->      <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	28734	1
Bin	False	True	25275	1
Bin	True	False	25508	1

"=" expression on line 459:

validated_buffer = '1'

	Evaluated to	Count	Threshold
Bin	False	54009	1
Bin	True	50759	1

"=" expression on line 459:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	54242	1
Bin	True	50526	1

"=" expression on line 467:

txtb_parity_mismatch(select_buf_index) = '1'

	Evaluated to	Count	Threshold
Bin	False	52198	1
Bin	True	4180	1

"=" expression on line 477:

txtb_parity_mismatch(curr_txtb_index_i) = '1'

	Evaluated to	Count	Threshold
Bin	False	20524	1
Bin	True	2881	1

"and" expression on line 481:

 txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1' 
 <------------LHS------------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	80218	1
Bin	True	False	1986	1
Bin	True	True	728	1

"=" expression on line 481:

txtb_parity_mismatch_tx = '1'

	Evaluated to	Count	Threshold
Bin	False	166497	1
Bin	True	2714	1

"=" expression on line 481:

txtb_clk_en_q = '1'

	Evaluated to	Count	Threshold
Bin	False	88265	1
Bin	True	80946	1

"=" expression on line 489:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	60372	1
Bin	True	49681	1

"=" expression on line 497:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	244700	1
Bin	True	178271	1

"=" expression on line 529:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	160339	1
Bin	True	105105	1

"=" expression on line 533:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	82796	1
Bin	True	178271	1

"=" expression on line 548:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 561:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 564:

store_ts_l_w = '1'

	Evaluated to	Count	Threshold
Bin	False	543765415	1
Bin	True	26263	1

"=" expression on line 575:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 582:

buffer_md_w = '1'

	Evaluated to	Count	Threshold
Bin	False	543765891	1
Bin	True	25787	1

"=" expression on line 597:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 603:

buffer_frame_test_w = '1'

	Evaluated to	Count	Threshold
Bin	False	543765774	1
Bin	True	25904	1

"=" expression on line 619:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 626:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	543766110	1
Bin	True	25568	1

"=" expression on line 641:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 644:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	543766110	1
Bin	True	25568	1

"=" expression on line 655:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 661:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	543766110	1
Bin	True	25568	1

"=" expression on line 672:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 675:

frame_valid_com_set = '1'

	Evaluated to	Count	Threshold
Bin	False	543766110	1
Bin	True	25568	1

"=" expression on line 677:

frame_valid_com_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	543740092	1
Bin	True	26018	1

"=" expression on line 691:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 697:

store_last_txtb_index = '1'

	Evaluated to	Count	Threshold
Bin	False	543766403	1
Bin	True	25275	1

"=" expression on line 702:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	543766110	1
Bin	True	25568	1

"and" expression on line 709:

 last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1' 
 <---------------LHS---------------->     <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	25275	1
Bin	True	False	10022	1
Bin	True	True	10020	1

"/=" expression on line 709:

last_txtb_index /= curr_txtb_index_i

	Evaluated to	Count	Threshold
Bin	False	56112	1
Bin	True	20042	1

"=" expression on line 709:

store_last_txtb_index = '1'

	Evaluated to	Count	Threshold
Bin	False	40859	1
Bin	True	35295	1

"=" expression on line 721:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 728:

select_buf_index = select_buf_index_reg

	Evaluated to	Count	Threshold
Bin	False	53530	1
Bin	True	46084	1

"=" expression on line 737:

load_ts_lw_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	350554	1
Bin	True	50412	1

"=" expression on line 738:

load_ts_uw_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	297941	1
Bin	True	52613	1

"=" expression on line 739:

load_ffmt_w_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	246077	1
Bin	True	51864	1

"=" expression on line 740:

load_ident_w_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	194443	1
Bin	True	51634	1

"=" expression on line 741:

load_frame_test_w_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	142211	1
Bin	True	52232	1

"=" expression on line 746:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"or" expression on lines 756 to 757:

 txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' or txtb_hw_cmd.arbl = '1' or txtb_hw_cmd.failed = '1' 
 <----------------------------------LHS----------------------------------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	28467	1
Bin	False	True	9436	1
Bin	True	False	15829	1

"or" expression on lines 756 to 757:

 txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' or txtb_hw_cmd.arbl = '1' 
 <---------------------LHS---------------------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	37903	1
Bin	False	True	455	1
Bin	True	False	15374	1

"or" expression on line 756:

 txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' 
 <---------LHS--------->    <--------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	38358	1
Bin	False	True	4262	1
Bin	True	False	11112	1

"=" expression on line 756:

txtb_hw_cmd.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	42620	1
Bin	True	11112	1

"=" expression on line 756:

txtb_hw_cmd.err = '1'

	Evaluated to	Count	Threshold
Bin	False	49470	1
Bin	True	4262	1

"=" expression on line 757:

txtb_hw_cmd.arbl = '1'

	Evaluated to	Count	Threshold
Bin	False	53277	1
Bin	True	455	1

"=" expression on line 757:

txtb_hw_cmd.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	44296	1
Bin	True	9436	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

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