Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_C_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| GEN_FILT_POS |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
100.0 % (5/5) |
N.A. |
N.A. |
100.0 % (10/10) |
| GEN_FILT_NEG |
100.0 % (1/1) |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (1/1) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
Signal assignment statement:
121: masked_input <= filter_input and filter_mask; Count: 112809
Threshold: 1
Signal assignment statement:
122: masked_value <= filter_value and filter_mask; Count: 4482
Threshold: 1
Covered toggles:
Port:
FILTER_MASK(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
Port:
FILTER_MASK(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
Port:
FILTER_MASK(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1688 | 1 |
Port:
FILTER_MASK(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
Port:
FILTER_MASK(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 90 | 1 |
| Bin | 1 | 0 | 1690 | 1 |
Port:
FILTER_MASK(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1692 | 1 |
Port:
FILTER_MASK(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 122 | 1 |
| Bin | 1 | 0 | 1722 | 1 |
Port:
FILTER_MASK(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
Port:
FILTER_MASK(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
Port:
FILTER_MASK(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Port:
FILTER_MASK(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1680 | 1 |
Port:
FILTER_MASK(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1626 | 1 |
Port:
FILTER_MASK(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36 | 1 |
| Bin | 1 | 0 | 1636 | 1 |
Port:
FILTER_MASK(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
Port:
FILTER_MASK(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
Port:
FILTER_MASK(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 1643 | 1 |
Port:
FILTER_MASK(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1631 | 1 |
Port:
FILTER_MASK(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
Port:
FILTER_MASK(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1680 | 1 |
Port:
FILTER_MASK(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1659 | 1 |
Port:
FILTER_MASK(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
Port:
FILTER_MASK(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Port:
FILTER_MASK(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
Port:
FILTER_MASK(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Port:
FILTER_MASK(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1671 | 1 |
Port:
FILTER_MASK(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
Port:
FILTER_MASK(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
Port:
FILTER_MASK(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Port:
FILTER_MASK(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
Port:
FILTER_VALUE(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 1816 | 1 |
Port:
FILTER_VALUE(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 189 | 1 |
| Bin | 1 | 0 | 1789 | 1 |
Port:
FILTER_VALUE(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1805 | 1 |
Port:
FILTER_VALUE(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 186 | 1 |
| Bin | 1 | 0 | 1786 | 1 |
Port:
FILTER_VALUE(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 1799 | 1 |
Port:
FILTER_VALUE(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 1816 | 1 |
Port:
FILTER_VALUE(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 224 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
Port:
FILTER_VALUE(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 224 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
Port:
FILTER_VALUE(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 1799 | 1 |
Port:
FILTER_VALUE(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Port:
FILTER_VALUE(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 196 | 1 |
| Bin | 1 | 0 | 1796 | 1 |
Port:
FILTER_VALUE(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 115 | 1 |
| Bin | 1 | 0 | 1715 | 1 |
Port:
FILTER_VALUE(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116 | 1 |
| Bin | 1 | 0 | 1716 | 1 |
Port:
FILTER_VALUE(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1701 | 1 |
Port:
FILTER_VALUE(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 117 | 1 |
| Bin | 1 | 0 | 1717 | 1 |
Port:
FILTER_VALUE(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
Port:
FILTER_VALUE(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Port:
FILTER_VALUE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
Port:
FILTER_VALUE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1680 | 1 |
Port:
FILTER_VALUE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 85 | 1 |
| Bin | 1 | 0 | 1685 | 1 |
Port:
FILTER_VALUE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Port:
FILTER_VALUE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
Port:
FILTER_VALUE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
Port:
FILTER_VALUE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Port:
FILTER_VALUE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 112 | 1 |
| Bin | 1 | 0 | 1712 | 1 |
Port:
FILTER_VALUE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Port:
FILTER_VALUE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Port:
FILTER_VALUE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
Port:
FILTER_VALUE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 128 | 1 |
| Bin | 1 | 0 | 1728 | 1 |
Port:
FILTER_INPUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34332 | 1 |
| Bin | 1 | 0 | 30165 | 1 |
Port:
FILTER_INPUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20951 | 1 |
| Bin | 1 | 0 | 16748 | 1 |
Port:
FILTER_INPUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34995 | 1 |
| Bin | 1 | 0 | 29978 | 1 |
Port:
FILTER_INPUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26409 | 1 |
| Bin | 1 | 0 | 21440 | 1 |
Port:
FILTER_INPUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37621 | 1 |
| Bin | 1 | 0 | 32560 | 1 |
Port:
FILTER_INPUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27574 | 1 |
| Bin | 1 | 0 | 22162 | 1 |
Port:
FILTER_INPUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37576 | 1 |
| Bin | 1 | 0 | 32729 | 1 |
Port:
FILTER_INPUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26623 | 1 |
| Bin | 1 | 0 | 21662 | 1 |
Port:
FILTER_INPUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34131 | 1 |
| Bin | 1 | 0 | 30013 | 1 |
Port:
FILTER_INPUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25018 | 1 |
| Bin | 1 | 0 | 20939 | 1 |
Port:
FILTER_INPUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35861 | 1 |
| Bin | 1 | 0 | 31802 | 1 |
Port:
FILTER_INPUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6676 | 1 |
| Bin | 1 | 0 | 77411 | 1 |
Port:
FILTER_INPUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 76980 | 1 |
Port:
FILTER_INPUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6016 | 1 |
| Bin | 1 | 0 | 75936 | 1 |
Port:
FILTER_INPUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6457 | 1 |
| Bin | 1 | 0 | 77301 | 1 |
Port:
FILTER_INPUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6203 | 1 |
| Bin | 1 | 0 | 75854 | 1 |
Port:
FILTER_INPUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6655 | 1 |
| Bin | 1 | 0 | 77348 | 1 |
Port:
FILTER_INPUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6116 | 1 |
| Bin | 1 | 0 | 76014 | 1 |
Port:
FILTER_INPUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6759 | 1 |
| Bin | 1 | 0 | 77172 | 1 |
Port:
FILTER_INPUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6340 | 1 |
| Bin | 1 | 0 | 76882 | 1 |
Port:
FILTER_INPUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7191 | 1 |
| Bin | 1 | 0 | 78168 | 1 |
Port:
FILTER_INPUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6170 | 1 |
| Bin | 1 | 0 | 76119 | 1 |
Port:
FILTER_INPUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 77753 | 1 |
Port:
FILTER_INPUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6122 | 1 |
| Bin | 1 | 0 | 76213 | 1 |
Port:
FILTER_INPUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6712 | 1 |
| Bin | 1 | 0 | 78180 | 1 |
Port:
FILTER_INPUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6213 | 1 |
| Bin | 1 | 0 | 76204 | 1 |
Port:
FILTER_INPUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7044 | 1 |
| Bin | 1 | 0 | 78347 | 1 |
Port:
FILTER_INPUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6316 | 1 |
| Bin | 1 | 0 | 75925 | 1 |
Port:
FILTER_INPUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6757 | 1 |
| Bin | 1 | 0 | 77490 | 1 |
Port:
ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1841 | 1 |
| Bin | 1 | 0 | 1841 | 1 |
Port:
VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 523 | 1 |
| Bin | 1 | 0 | 2123 | 1 |
Signal:
MASKED_INPUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
Signal:
MASKED_INPUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 122 | 1 |
| Bin | 1 | 0 | 1722 | 1 |
Signal:
MASKED_INPUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 120 | 1 |
| Bin | 1 | 0 | 1720 | 1 |
Signal:
MASKED_INPUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
Signal:
MASKED_INPUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
Signal:
MASKED_INPUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
Signal:
MASKED_INPUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
Signal:
MASKED_INPUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 115 | 1 |
| Bin | 1 | 0 | 1715 | 1 |
Signal:
MASKED_INPUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 121 | 1 |
| Bin | 1 | 0 | 1721 | 1 |
Signal:
MASKED_INPUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 120 | 1 |
| Bin | 1 | 0 | 1720 | 1 |
Signal:
MASKED_INPUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 1691 | 1 |
Signal:
MASKED_INPUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 1610 | 1 |
Signal:
MASKED_INPUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 1617 | 1 |
Signal:
MASKED_INPUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 1617 | 1 |
Signal:
MASKED_INPUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11 | 1 |
| Bin | 1 | 0 | 1611 | 1 |
Signal:
MASKED_INPUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24 | 1 |
| Bin | 1 | 0 | 1624 | 1 |
Signal:
MASKED_INPUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
Signal:
MASKED_INPUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14 | 1 |
| Bin | 1 | 0 | 1614 | 1 |
Signal:
MASKED_INPUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1666 | 1 |
Signal:
MASKED_INPUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1640 | 1 |
Signal:
MASKED_INPUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 39 | 1 |
| Bin | 1 | 0 | 1639 | 1 |
Signal:
MASKED_INPUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
MASKED_INPUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
Signal:
MASKED_INPUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Signal:
MASKED_INPUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 1648 | 1 |
Signal:
MASKED_INPUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1640 | 1 |
Signal:
MASKED_INPUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 1643 | 1 |
Signal:
MASKED_INPUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Signal:
MASKED_INPUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
Signal:
MASKED_VALUE(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Signal:
MASKED_VALUE(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
Signal:
MASKED_VALUE(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Signal:
MASKED_VALUE(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Signal:
MASKED_VALUE(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Signal:
MASKED_VALUE(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Signal:
MASKED_VALUE(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
Signal:
MASKED_VALUE(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1671 | 1 |
Signal:
MASKED_VALUE(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 69 | 1 |
| Bin | 1 | 0 | 1669 | 1 |
Signal:
MASKED_VALUE(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
Signal:
MASKED_VALUE(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
Signal:
MASKED_VALUE(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 1610 | 1 |
Signal:
MASKED_VALUE(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1626 | 1 |
Signal:
MASKED_VALUE(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
Signal:
MASKED_VALUE(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
Signal:
MASKED_VALUE(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16 | 1 |
| Bin | 1 | 0 | 1616 | 1 |
Signal:
MASKED_VALUE(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24 | 1 |
| Bin | 1 | 0 | 1624 | 1 |
Signal:
MASKED_VALUE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11 | 1 |
| Bin | 1 | 0 | 1611 | 1 |
Signal:
MASKED_VALUE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
MASKED_VALUE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Signal:
MASKED_VALUE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 69 | 1 |
| Bin | 1 | 0 | 1669 | 1 |
Signal:
MASKED_VALUE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
MASKED_VALUE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
MASKED_VALUE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1658 | 1 |
Signal:
MASKED_VALUE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Signal:
MASKED_VALUE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Signal:
MASKED_VALUE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Signal:
MASKED_VALUE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
Signal:
MASKED_VALUE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: