NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.INT_STAT_DOI_REG_COMP.BIT_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.INT_STAT_DOI_REG_COMP.BIT_GEN(0)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 147 to 149:

147:        reg_value_r(i) <= data_in(i) when (wr_en = '1') 
148:                                        else 
149:                            reset_value_i(i);

Count: 2219493
Threshold: 1

Signal assignment statement on line 147:

147: reg_value_r(i) <= data_in(i) when (wr_en = '1')
Count: 294
Threshold: 1

Signal assignment statement on line 149:

149: reset_value_i(i);
Count: 2219199
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 147:

147: reg_value_r(i) <= data_in(i) when (wr_en = '1')

	Evaluated to	Count	Threshold
Bin	True	294	1
Bin	False	2219199	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 147:

wr_en = '1'

	Evaluated to	Count	Threshold
Bin	False	2219199	1
Bin	True	294	1