Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| ENDIAN_SWAPPER_TX_INST |
100.0 % (7/7) |
N.A. |
100.0 % (192/192) |
N.A. |
N.A. |
N.A. |
100.0 % (199/199) |
| PROTOCOL_CONTROL_FSM_INST |
100.0 % (1177/1177) |
100.0 % (790/790) |
100.0 % (850/850) |
100.0 % (1215/1215) |
100.0 % (76/76) |
N.A. |
100.0 % (4108/4108) |
| CONTROL_COUNTER_INST |
100.0 % (44/44) |
100.0 % (40/40) |
100.0 % (158/158) |
100.0 % (33/33) |
N.A. |
N.A. |
100.0 % (275/275) |
| REINTEGRATION_COUNTER_INST |
100.0 % (13/13) |
100.0 % (12/12) |
100.0 % (46/46) |
100.0 % (18/18) |
N.A. |
N.A. |
100.0 % (89/89) |
| RETRANSMITT_COUNTER_INST |
100.0 % (15/15) |
100.0 % (14/14) |
100.0 % (46/46) |
100.0 % (25/25) |
N.A. |
N.A. |
100.0 % (100/100) |
| ERR_DETECTOR_INST |
100.0 % (71/71) |
100.0 % (72/72) |
100.0 % (388/388) |
100.0 % (123/123) |
N.A. |
100.0 % (13/13) |
100.0 % (667/667) |
| TX_SHIFT_REG_INST |
100.0 % (52/52) |
100.0 % (52/52) |
100.0 % (780/780) |
100.0 % (86/86) |
N.A. |
N.A. |
100.0 % (970/970) |
| RX_SHIFT_REG_INST |
100.0 % (85/85) |
100.0 % (98/98) |
100.0 % (508/508) |
100.0 % (95/95) |
N.A. |
N.A. |
100.0 % (786/786) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
Signal assignment statement:
988: pc_dbg <= pc_dbg_i; Count: 562979
Threshold: 1
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
Port:
MR_MODE_ACF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
Port:
MR_MODE_STM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1760 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_MODE_FDE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1800 | 1 |
| Bin | 1 | 0 | 200 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
MR_MODE_TSTM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 2626 | 1 |
Port:
MR_MODE_SAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Port:
MR_SETTINGS_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
MR_SETTINGS_NISOFD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
Port:
MR_SETTINGS_RTRTH(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
Port:
MR_SETTINGS_RTRTH(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Port:
MR_SETTINGS_RTRTH(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
Port:
MR_SETTINGS_RTRTH(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Port:
MR_SETTINGS_RTRLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2454 | 1 |
| Bin | 1 | 0 | 4054 | 1 |
Port:
MR_SETTINGS_ILBP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
Port:
MR_SETTINGS_PEX | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1672 | 1 |
Port:
MR_COMMAND_ERCRST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
Port:
MR_COMMAND_CPEXS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
Port:
MR_SSP_CFG_SSP_SRC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
Port:
MR_SSP_CFG_SSP_SRC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 817 | 1 |
| Bin | 1 | 0 | 2407 | 1 |
Port:
ALC_ALC_BIT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
Port:
ALC_ALC_BIT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1686 | 1 |
Port:
ALC_ALC_BIT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
Port:
ALC_ALC_BIT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 171 | 1 |
| Bin | 1 | 0 | 1769 | 1 |
Port:
ALC_ALC_BIT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 1894 | 1 |
Port:
ALC_ALC_ID_FIELD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
Port:
ALC_ALC_ID_FIELD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1638 | 1 |
Port:
ALC_ALC_ID_FIELD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Port:
ERR_CAPT_ERR_TYPE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 793 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
Port:
ERR_CAPT_ERR_TYPE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1252 | 1 |
| Bin | 1 | 0 | 2850 | 1 |
Port:
ERR_CAPT_ERR_TYPE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 336 | 1 |
| Bin | 1 | 0 | 1935 | 1 |
Port:
ERR_CAPT_ERR_POS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4185 | 1 |
| Bin | 1 | 0 | 2591 | 1 |
Port:
ERR_CAPT_ERR_POS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4402 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
Port:
ERR_CAPT_ERR_POS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3666 | 1 |
| Bin | 1 | 0 | 2070 | 1 |
Port:
ERR_CAPT_ERR_POS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2960 | 1 |
| Bin | 1 | 0 | 1361 | 1 |
Port:
ERR_CAPT_ERR_ERP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 290 | 1 |
| Bin | 1 | 0 | 1890 | 1 |
Port:
MR_STATUS_PEXS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
Port:
PC_DBG.IS_SOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24462 | 1 |
| Bin | 1 | 0 | 26062 | 1 |
Port:
PC_DBG.IS_ARBITRATION | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55248 | 1 |
| Bin | 1 | 0 | 56848 | 1 |
Port:
PC_DBG.IS_CONTROL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50561 | 1 |
| Bin | 1 | 0 | 52161 | 1 |
Port:
PC_DBG.IS_DATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
PC_DBG.IS_STUFF_COUNT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13456 | 1 |
| Bin | 1 | 0 | 15056 | 1 |
Port:
PC_DBG.IS_CRC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31170 | 1 |
| Bin | 1 | 0 | 32770 | 1 |
Port:
PC_DBG.IS_CRC_DELIM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29717 | 1 |
| Bin | 1 | 0 | 31317 | 1 |
Port:
PC_DBG.IS_ACK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29563 | 1 |
| Bin | 1 | 0 | 31163 | 1 |
Port:
PC_DBG.IS_ACK_DELIM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28146 | 1 |
| Bin | 1 | 0 | 29746 | 1 |
Port:
PC_DBG.IS_EOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27259 | 1 |
| Bin | 1 | 0 | 28859 | 1 |
Port:
PC_DBG.IS_OVERLOAD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 529 | 1 |
| Bin | 1 | 0 | 2129 | 1 |
Port:
PC_DBG.IS_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26658 | 1 |
| Bin | 1 | 0 | 28253 | 1 |
Port:
PC_DBG.IS_INTERMISSION | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51238 | 1 |
| Bin | 1 | 0 | 52837 | 1 |
Port:
PC_DBG.IS_SUSPEND | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2324 | 1 |
| Bin | 1 | 0 | 3924 | 1 |
Port:
TRAN_WORD(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8251 | 1 |
| Bin | 1 | 0 | 9851 | 1 |
Port:
TRAN_WORD(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8670 | 1 |
| Bin | 1 | 0 | 10270 | 1 |
Port:
TRAN_WORD(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8250 | 1 |
| Bin | 1 | 0 | 9850 | 1 |
Port:
TRAN_WORD(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26016 | 1 |
| Bin | 1 | 0 | 27616 | 1 |
Port:
TRAN_WORD(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20559 | 1 |
| Bin | 1 | 0 | 22159 | 1 |
Port:
TRAN_WORD(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26228 | 1 |
| Bin | 1 | 0 | 27828 | 1 |
Port:
TRAN_WORD(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21530 | 1 |
| Bin | 1 | 0 | 23130 | 1 |
Port:
TRAN_WORD(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25986 | 1 |
| Bin | 1 | 0 | 27586 | 1 |
Port:
TRAN_WORD(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22777 | 1 |
| Bin | 1 | 0 | 24377 | 1 |
Port:
TRAN_WORD(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25704 | 1 |
| Bin | 1 | 0 | 27304 | 1 |
Port:
TRAN_WORD(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22032 | 1 |
| Bin | 1 | 0 | 23632 | 1 |
Port:
TRAN_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25833 | 1 |
| Bin | 1 | 0 | 27433 | 1 |
Port:
TRAN_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22441 | 1 |
| Bin | 1 | 0 | 24041 | 1 |
Port:
TRAN_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26355 | 1 |
| Bin | 1 | 0 | 27955 | 1 |
Port:
TRAN_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14208 | 1 |
| Bin | 1 | 0 | 15808 | 1 |
Port:
TRAN_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15135 | 1 |
| Bin | 1 | 0 | 16735 | 1 |
Port:
TRAN_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14400 | 1 |
| Bin | 1 | 0 | 16000 | 1 |
Port:
TRAN_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15059 | 1 |
| Bin | 1 | 0 | 16659 | 1 |
Port:
TRAN_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14849 | 1 |
| Bin | 1 | 0 | 16449 | 1 |
Port:
TRAN_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15821 | 1 |
| Bin | 1 | 0 | 17421 | 1 |
Port:
TRAN_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14688 | 1 |
| Bin | 1 | 0 | 16288 | 1 |
Port:
TRAN_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15846 | 1 |
| Bin | 1 | 0 | 17446 | 1 |
Port:
TRAN_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25928 | 1 |
| Bin | 1 | 0 | 27528 | 1 |
Port:
TRAN_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16627 | 1 |
| Bin | 1 | 0 | 18227 | 1 |
Port:
TRAN_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35438 | 1 |
| Bin | 1 | 0 | 37038 | 1 |
Port:
TRAN_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26739 | 1 |
| Bin | 1 | 0 | 28339 | 1 |
Port:
TRAN_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19032 | 1 |
| Bin | 1 | 0 | 20632 | 1 |
Port:
TRAN_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16938 | 1 |
| Bin | 1 | 0 | 18538 | 1 |
Port:
TRAN_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26470 | 1 |
| Bin | 1 | 0 | 28070 | 1 |
Port:
TRAN_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26680 | 1 |
| Bin | 1 | 0 | 28280 | 1 |
Port:
TRAN_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27552 | 1 |
| Bin | 1 | 0 | 29152 | 1 |
Port:
TRAN_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35377 | 1 |
| Bin | 1 | 0 | 36977 | 1 |
Port:
TRAN_DLC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1530 | 1 |
| Bin | 1 | 0 | 3129 | 1 |
Port:
TRAN_DLC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1943 | 1 |
| Bin | 1 | 0 | 3543 | 1 |
Port:
TRAN_DLC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1905 | 1 |
| Bin | 1 | 0 | 3504 | 1 |
Port:
TRAN_DLC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3494 | 1 |
| Bin | 1 | 0 | 5094 | 1 |
Port:
TRAN_IS_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1161 | 1 |
| Bin | 1 | 0 | 2759 | 1 |
Port:
TRAN_IDENT_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2564 | 1 |
| Bin | 1 | 0 | 4164 | 1 |
Port:
TRAN_FRAME_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2708 | 1 |
| Bin | 1 | 0 | 4308 | 1 |
Port:
TRAN_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2008 | 1 |
| Bin | 1 | 0 | 3608 | 1 |
Port:
TRAN_IDENTIFIER(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3946 | 1 |
| Bin | 1 | 0 | 5484 | 1 |
Port:
TRAN_IDENTIFIER(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3920 | 1 |
| Bin | 1 | 0 | 5542 | 1 |
Port:
TRAN_IDENTIFIER(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3792 | 1 |
| Bin | 1 | 0 | 5324 | 1 |
Port:
TRAN_IDENTIFIER(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4128 | 1 |
| Bin | 1 | 0 | 5746 | 1 |
Port:
TRAN_IDENTIFIER(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3888 | 1 |
| Bin | 1 | 0 | 5425 | 1 |
Port:
TRAN_IDENTIFIER(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4157 | 1 |
| Bin | 1 | 0 | 5770 | 1 |
Port:
TRAN_IDENTIFIER(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3886 | 1 |
| Bin | 1 | 0 | 5504 | 1 |
Port:
TRAN_IDENTIFIER(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4233 | 1 |
| Bin | 1 | 0 | 5783 | 1 |
Port:
TRAN_IDENTIFIER(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3889 | 1 |
| Bin | 1 | 0 | 5506 | 1 |
Port:
TRAN_IDENTIFIER(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4204 | 1 |
| Bin | 1 | 0 | 5749 | 1 |
Port:
TRAN_IDENTIFIER(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3808 | 1 |
| Bin | 1 | 0 | 5429 | 1 |
Port:
TRAN_IDENTIFIER(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1667 | 1 |
| Bin | 1 | 0 | 9368 | 1 |
Port:
TRAN_IDENTIFIER(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713 | 1 |
| Bin | 1 | 0 | 9584 | 1 |
Port:
TRAN_IDENTIFIER(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1692 | 1 |
| Bin | 1 | 0 | 9464 | 1 |
Port:
TRAN_IDENTIFIER(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1708 | 1 |
| Bin | 1 | 0 | 9676 | 1 |
Port:
TRAN_IDENTIFIER(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1710 | 1 |
| Bin | 1 | 0 | 9487 | 1 |
Port:
TRAN_IDENTIFIER(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1603 | 1 |
| Bin | 1 | 0 | 9370 | 1 |
Port:
TRAN_IDENTIFIER(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 9410 | 1 |
Port:
TRAN_IDENTIFIER(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1672 | 1 |
| Bin | 1 | 0 | 9469 | 1 |
Port:
TRAN_IDENTIFIER(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1704 | 1 |
| Bin | 1 | 0 | 9526 | 1 |
Port:
TRAN_IDENTIFIER(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1702 | 1 |
| Bin | 1 | 0 | 9536 | 1 |
Port:
TRAN_IDENTIFIER(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1736 | 1 |
| Bin | 1 | 0 | 9656 | 1 |
Port:
TRAN_IDENTIFIER(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1654 | 1 |
| Bin | 1 | 0 | 9406 | 1 |
Port:
TRAN_IDENTIFIER(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1706 | 1 |
| Bin | 1 | 0 | 9513 | 1 |
Port:
TRAN_IDENTIFIER(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1714 | 1 |
| Bin | 1 | 0 | 9618 | 1 |
Port:
TRAN_IDENTIFIER(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1700 | 1 |
| Bin | 1 | 0 | 9481 | 1 |
Port:
TRAN_IDENTIFIER(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 9571 | 1 |
Port:
TRAN_IDENTIFIER(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1744 | 1 |
| Bin | 1 | 0 | 9585 | 1 |
Port:
TRAN_IDENTIFIER(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 9381 | 1 |
Port:
TRAN_FRAME_TEST.FSTC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
Port:
TRAN_FRAME_TEST.FCRC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Port:
TRAN_FRAME_TEST.SDLC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 3284 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 183 | 1 |
| Bin | 1 | 0 | 1828 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 235 | 1 |
| Bin | 1 | 0 | 1880 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 429 | 1 |
| Bin | 1 | 0 | 2074 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 646 | 1 |
| Bin | 1 | 0 | 2291 | 1 |
Port:
TRAN_FRAME_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25071 | 1 |
| Bin | 1 | 0 | 26671 | 1 |
Port:
TRAN_FRAME_PARITY_ERROR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 762 | 1 |
| Bin | 1 | 0 | 2362 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24816 | 1 |
| Bin | 1 | 0 | 26416 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4237 | 1 |
| Bin | 1 | 0 | 5837 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 455 | 1 |
| Bin | 1 | 0 | 2055 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9015 | 1 |
| Bin | 1 | 0 | 10615 | 1 |
Port:
TXTB_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78974 | 1 |
| Bin | 1 | 0 | 80574 | 1 |
Port:
TXTB_CHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10007 | 1 |
| Bin | 1 | 0 | 11607 | 1 |
Port:
REC_IDENT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34332 | 1 |
| Bin | 1 | 0 | 30165 | 1 |
Port:
REC_IDENT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20951 | 1 |
| Bin | 1 | 0 | 16748 | 1 |
Port:
REC_IDENT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34995 | 1 |
| Bin | 1 | 0 | 29978 | 1 |
Port:
REC_IDENT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26409 | 1 |
| Bin | 1 | 0 | 21440 | 1 |
Port:
REC_IDENT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37621 | 1 |
| Bin | 1 | 0 | 32560 | 1 |
Port:
REC_IDENT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27574 | 1 |
| Bin | 1 | 0 | 22162 | 1 |
Port:
REC_IDENT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37576 | 1 |
| Bin | 1 | 0 | 32729 | 1 |
Port:
REC_IDENT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26623 | 1 |
| Bin | 1 | 0 | 21662 | 1 |
Port:
REC_IDENT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34131 | 1 |
| Bin | 1 | 0 | 30013 | 1 |
Port:
REC_IDENT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25018 | 1 |
| Bin | 1 | 0 | 20939 | 1 |
Port:
REC_IDENT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35861 | 1 |
| Bin | 1 | 0 | 31802 | 1 |
Port:
REC_IDENT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6676 | 1 |
| Bin | 1 | 0 | 77411 | 1 |
Port:
REC_IDENT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 76980 | 1 |
Port:
REC_IDENT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6016 | 1 |
| Bin | 1 | 0 | 75936 | 1 |
Port:
REC_IDENT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6457 | 1 |
| Bin | 1 | 0 | 77301 | 1 |
Port:
REC_IDENT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6203 | 1 |
| Bin | 1 | 0 | 75854 | 1 |
Port:
REC_IDENT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6655 | 1 |
| Bin | 1 | 0 | 77348 | 1 |
Port:
REC_IDENT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6116 | 1 |
| Bin | 1 | 0 | 76014 | 1 |
Port:
REC_IDENT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6759 | 1 |
| Bin | 1 | 0 | 77172 | 1 |
Port:
REC_IDENT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6340 | 1 |
| Bin | 1 | 0 | 76882 | 1 |
Port:
REC_IDENT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7191 | 1 |
| Bin | 1 | 0 | 78168 | 1 |
Port:
REC_IDENT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6170 | 1 |
| Bin | 1 | 0 | 76119 | 1 |
Port:
REC_IDENT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 77753 | 1 |
Port:
REC_IDENT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6122 | 1 |
| Bin | 1 | 0 | 76213 | 1 |
Port:
REC_IDENT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6712 | 1 |
| Bin | 1 | 0 | 78180 | 1 |
Port:
REC_IDENT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6213 | 1 |
| Bin | 1 | 0 | 76204 | 1 |
Port:
REC_IDENT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7044 | 1 |
| Bin | 1 | 0 | 78347 | 1 |
Port:
REC_IDENT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6316 | 1 |
| Bin | 1 | 0 | 75925 | 1 |
Port:
REC_IDENT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6757 | 1 |
| Bin | 1 | 0 | 77490 | 1 |
Port:
REC_DLC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20320 | 1 |
| Bin | 1 | 0 | 58988 | 1 |
Port:
REC_DLC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22531 | 1 |
| Bin | 1 | 0 | 28242 | 1 |
Port:
REC_DLC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22383 | 1 |
| Bin | 1 | 0 | 27966 | 1 |
Port:
REC_DLC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26951 | 1 |
| Bin | 1 | 0 | 33011 | 1 |
Port:
REC_IS_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22038 | 1 |
| Bin | 1 | 0 | 23636 | 1 |
Port:
REC_IDENT_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15760 | 1 |
| Bin | 1 | 0 | 17358 | 1 |
Port:
REC_FRAME_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28440 | 1 |
| Bin | 1 | 0 | 30036 | 1 |
Port:
REC_LBPF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 180 | 1 |
| Bin | 1 | 0 | 1780 | 1 |
Port:
REC_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20406 | 1 |
| Bin | 1 | 0 | 22002 | 1 |
Port:
REC_ESI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2145 | 1 |
| Bin | 1 | 0 | 3743 | 1 |
Port:
REC_IVLD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50520 | 1 |
| Bin | 1 | 0 | 52113 | 1 |
Port:
STORE_METADATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28520 | 1 |
| Bin | 1 | 0 | 30120 | 1 |
Port:
REC_ABORT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30824 | 1 |
| Bin | 1 | 0 | 32424 | 1 |
Port:
STORE_DATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88897 | 1 |
| Bin | 1 | 0 | 90497 | 1 |
Port:
STORE_DATA_WORD(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 237198 | 1 |
| Bin | 1 | 0 | 238797 | 1 |
Port:
STORE_DATA_WORD(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 243752 | 1 |
| Bin | 1 | 0 | 245348 | 1 |
Port:
STORE_DATA_WORD(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 254056 | 1 |
| Bin | 1 | 0 | 255652 | 1 |
Port:
STORE_DATA_WORD(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 261408 | 1 |
| Bin | 1 | 0 | 263004 | 1 |
Port:
STORE_DATA_WORD(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270752 | 1 |
| Bin | 1 | 0 | 272349 | 1 |
Port:
STORE_DATA_WORD(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 281246 | 1 |
| Bin | 1 | 0 | 282842 | 1 |
Port:
STORE_DATA_WORD(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 289484 | 1 |
| Bin | 1 | 0 | 291079 | 1 |
Port:
STORE_DATA_WORD(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 297255 | 1 |
| Bin | 1 | 0 | 298852 | 1 |
Port:
STORE_DATA_WORD(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 286221 | 1 |
| Bin | 1 | 0 | 287818 | 1 |
Port:
STORE_DATA_WORD(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 294374 | 1 |
| Bin | 1 | 0 | 295971 | 1 |
Port:
STORE_DATA_WORD(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 302753 | 1 |
| Bin | 1 | 0 | 304349 | 1 |
Port:
STORE_DATA_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 311493 | 1 |
| Bin | 1 | 0 | 313091 | 1 |
Port:
STORE_DATA_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 323361 | 1 |
| Bin | 1 | 0 | 324957 | 1 |
Port:
STORE_DATA_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 330483 | 1 |
| Bin | 1 | 0 | 332080 | 1 |
Port:
STORE_DATA_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 338889 | 1 |
| Bin | 1 | 0 | 340488 | 1 |
Port:
STORE_DATA_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 345150 | 1 |
| Bin | 1 | 0 | 346748 | 1 |
Port:
STORE_DATA_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 386346 | 1 |
| Bin | 1 | 0 | 387945 | 1 |
Port:
STORE_DATA_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 400757 | 1 |
| Bin | 1 | 0 | 402354 | 1 |
Port:
STORE_DATA_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 409685 | 1 |
| Bin | 1 | 0 | 411281 | 1 |
Port:
STORE_DATA_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 419496 | 1 |
| Bin | 1 | 0 | 421093 | 1 |
Port:
STORE_DATA_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 432274 | 1 |
| Bin | 1 | 0 | 433870 | 1 |
Port:
STORE_DATA_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 442097 | 1 |
| Bin | 1 | 0 | 443695 | 1 |
Port:
STORE_DATA_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 454252 | 1 |
| Bin | 1 | 0 | 455847 | 1 |
Port:
STORE_DATA_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465041 | 1 |
| Bin | 1 | 0 | 466639 | 1 |
Port:
STORE_DATA_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 510943 | 1 |
| Bin | 1 | 0 | 512538 | 1 |
Port:
STORE_DATA_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522813 | 1 |
| Bin | 1 | 0 | 524410 | 1 |
Port:
STORE_DATA_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 532557 | 1 |
| Bin | 1 | 0 | 534152 | 1 |
Port:
STORE_DATA_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 542224 | 1 |
| Bin | 1 | 0 | 543819 | 1 |
Port:
STORE_DATA_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555100 | 1 |
| Bin | 1 | 0 | 556695 | 1 |
Port:
STORE_DATA_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564607 | 1 |
| Bin | 1 | 0 | 566201 | 1 |
Port:
STORE_DATA_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576164 | 1 |
| Bin | 1 | 0 | 577759 | 1 |
Port:
STORE_DATA_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586427 | 1 |
| Bin | 1 | 0 | 588021 | 1 |
Port:
SOF_PULSE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79747 | 1 |
| Bin | 1 | 0 | 81347 | 1 |
Port:
IS_TRANSMITTER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19892 | 1 |
| Bin | 1 | 0 | 21492 | 1 |
Port:
IS_RECEIVER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30888 | 1 |
| Bin | 1 | 0 | 32482 | 1 |
Port:
ARBITRATION_LOST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1172 | 1 |
| Bin | 1 | 0 | 2772 | 1 |
Port:
SET_TRANSMITTER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 39810 | 1 |
| Bin | 1 | 0 | 41410 | 1 |
Port:
SET_RECEIVER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30469 | 1 |
| Bin | 1 | 0 | 32069 | 1 |
Port:
SET_IDLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95674 | 1 |
| Bin | 1 | 0 | 97274 | 1 |
Port:
IS_ERR_ACTIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8424 | 1 |
| Bin | 1 | 0 | 8415 | 1 |
Port:
IS_ERR_PASSIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
Port:
IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8227 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Port:
ERR_DETECTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123242 | 1 |
| Bin | 1 | 0 | 124842 | 1 |
Port:
PRIMARY_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22658 | 1 |
| Bin | 1 | 0 | 24258 | 1 |
Port:
ACT_ERR_OVR_FLAG | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19607 | 1 |
| Bin | 1 | 0 | 21205 | 1 |
Port:
ERR_DELIM_LATE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 390 | 1 |
| Bin | 1 | 0 | 1990 | 1 |
Port:
SET_ERR_ACTIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Port:
ERR_CTRS_UNCHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 791 | 1 |
| Bin | 1 | 0 | 2391 | 1 |
Port:
TX_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11044003 | 1 |
| Bin | 1 | 0 | 11045602 | 1 |
Port:
RX_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10015414 | 1 |
| Bin | 1 | 0 | 10017014 | 1 |
Port:
TX_DATA_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 644444 | 1 |
| Bin | 1 | 0 | 642846 | 1 |
Port:
TX_DATA_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635336 | 1 |
| Bin | 1 | 0 | 633738 | 1 |
Port:
RX_DATA_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Port:
STUFF_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24816 | 1 |
| Bin | 1 | 0 | 26416 | 1 |
Port:
DESTUFF_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55285 | 1 |
| Bin | 1 | 0 | 56885 | 1 |
Port:
FIXED_STUFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13466 | 1 |
| Bin | 1 | 0 | 15066 | 1 |
Port:
TX_FRAME_NO_SOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
Port:
DST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116920 | 1 |
| Bin | 1 | 0 | 118520 | 1 |
Port:
DST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 241878 | 1 |
| Bin | 1 | 0 | 243473 | 1 |
Port:
DST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 483649 | 1 |
| Bin | 1 | 0 | 485246 | 1 |
Port:
BST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33334 | 1 |
| Bin | 1 | 0 | 34934 | 1 |
Port:
BST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70225 | 1 |
| Bin | 1 | 0 | 71823 | 1 |
Port:
BST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 140700 | 1 |
| Bin | 1 | 0 | 142298 | 1 |
Port:
STUFF_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20489 | 1 |
| Bin | 1 | 0 | 22089 | 1 |
Port:
BIT_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9381 | 1 |
| Bin | 1 | 0 | 10981 | 1 |
Port:
BTMC_RESET | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28129 | 1 |
| Bin | 1 | 0 | 29729 | 1 |
Port:
DBT_MEASURE_START | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2323 | 1 |
| Bin | 1 | 0 | 3923 | 1 |
Port:
GEN_FIRST_SSP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2323 | 1 |
| Bin | 1 | 0 | 3923 | 1 |
Port:
SYNC_EDGE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1555148 | 1 |
| Bin | 1 | 0 | 1556748 | 1 |
Port:
BIT_ERR_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66912 | 1 |
| Bin | 1 | 0 | 65320 | 1 |
Port:
CRC_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55285 | 1 |
| Bin | 1 | 0 | 56885 | 1 |
Port:
CRC_SPEC_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 112536 | 1 |
| Bin | 1 | 0 | 114132 | 1 |
Port:
CRC_CALC_FROM_RX | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83068 | 1 |
| Bin | 1 | 0 | 84659 | 1 |
Port:
LOAD_INIT_VECT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 112514 | 1 |
| Bin | 1 | 0 | 114114 | 1 |
Port:
CRC_15(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1452642 | 1 |
| Bin | 1 | 0 | 1454241 | 1 |
Port:
CRC_15(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1404381 | 1 |
| Bin | 1 | 0 | 1405979 | 1 |
Port:
CRC_15(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1416815 | 1 |
| Bin | 1 | 0 | 1418414 | 1 |
Port:
CRC_15(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1431040 | 1 |
| Bin | 1 | 0 | 1432636 | 1 |
Port:
CRC_15(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1444591 | 1 |
| Bin | 1 | 0 | 1446189 | 1 |
Port:
CRC_15(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1438246 | 1 |
| Bin | 1 | 0 | 1439842 | 1 |
Port:
CRC_15(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1452223 | 1 |
| Bin | 1 | 0 | 1453819 | 1 |
Port:
CRC_15(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1489085 | 1 |
| Bin | 1 | 0 | 1490683 | 1 |
Port:
CRC_15(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1428572 | 1 |
| Bin | 1 | 0 | 1430168 | 1 |
Port:
CRC_15(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1442138 | 1 |
| Bin | 1 | 0 | 1443734 | 1 |
Port:
CRC_15(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1454104 | 1 |
| Bin | 1 | 0 | 1455703 | 1 |
Port:
CRC_15(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1453743 | 1 |
| Bin | 1 | 0 | 1455342 | 1 |
Port:
CRC_15(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1440570 | 1 |
| Bin | 1 | 0 | 1442165 | 1 |
Port:
CRC_15(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1456437 | 1 |
| Bin | 1 | 0 | 1458034 | 1 |
Port:
CRC_15(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1470076 | 1 |
| Bin | 1 | 0 | 1471674 | 1 |
Port:
CRC_17(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734039 | 1 |
| Bin | 1 | 0 | 1735633 | 1 |
Port:
CRC_17(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1744508 | 1 |
| Bin | 1 | 0 | 1746106 | 1 |
Port:
CRC_17(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1759054 | 1 |
| Bin | 1 | 0 | 1760651 | 1 |
Port:
CRC_17(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1757156 | 1 |
| Bin | 1 | 0 | 1758753 | 1 |
Port:
CRC_17(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1695908 | 1 |
| Bin | 1 | 0 | 1697506 | 1 |
Port:
CRC_17(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1710517 | 1 |
| Bin | 1 | 0 | 1712115 | 1 |
Port:
CRC_17(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1657718 | 1 |
| Bin | 1 | 0 | 1659317 | 1 |
Port:
CRC_17(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1671362 | 1 |
| Bin | 1 | 0 | 1672959 | 1 |
Port:
CRC_17(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1685982 | 1 |
| Bin | 1 | 0 | 1687581 | 1 |
Port:
CRC_17(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1699437 | 1 |
| Bin | 1 | 0 | 1701036 | 1 |
Port:
CRC_17(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713617 | 1 |
| Bin | 1 | 0 | 1715217 | 1 |
Port:
CRC_17(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713382 | 1 |
| Bin | 1 | 0 | 1714978 | 1 |
Port:
CRC_17(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1725540 | 1 |
| Bin | 1 | 0 | 1727138 | 1 |
Port:
CRC_17(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1744070 | 1 |
| Bin | 1 | 0 | 1745668 | 1 |
Port:
CRC_17(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713985 | 1 |
| Bin | 1 | 0 | 1715584 | 1 |
Port:
CRC_17(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1729286 | 1 |
| Bin | 1 | 0 | 1730885 | 1 |
Port:
CRC_17(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1757719 | 1 |
| Bin | 1 | 0 | 1759317 | 1 |
Port:
CRC_21(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1738348 | 1 |
| Bin | 1 | 0 | 1739941 | 1 |
Port:
CRC_21(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1694492 | 1 |
| Bin | 1 | 0 | 1696089 | 1 |
Port:
CRC_21(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1709182 | 1 |
| Bin | 1 | 0 | 1710780 | 1 |
Port:
CRC_21(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1723668 | 1 |
| Bin | 1 | 0 | 1725266 | 1 |
Port:
CRC_21(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1736428 | 1 |
| Bin | 1 | 0 | 1738027 | 1 |
Port:
CRC_21(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1749537 | 1 |
| Bin | 1 | 0 | 1751135 | 1 |
Port:
CRC_21(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1762507 | 1 |
| Bin | 1 | 0 | 1764105 | 1 |
Port:
CRC_21(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1777446 | 1 |
| Bin | 1 | 0 | 1779044 | 1 |
Port:
CRC_21(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1718146 | 1 |
| Bin | 1 | 0 | 1719743 | 1 |
Port:
CRC_21(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1733293 | 1 |
| Bin | 1 | 0 | 1734892 | 1 |
Port:
CRC_21(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1723964 | 1 |
| Bin | 1 | 0 | 1725560 | 1 |
Port:
CRC_21(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1737663 | 1 |
| Bin | 1 | 0 | 1739261 | 1 |
Port:
CRC_21(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1753350 | 1 |
| Bin | 1 | 0 | 1754945 | 1 |
Port:
CRC_21(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1768568 | 1 |
| Bin | 1 | 0 | 1770168 | 1 |
Port:
CRC_21(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1710305 | 1 |
| Bin | 1 | 0 | 1711902 | 1 |
Port:
CRC_21(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1724000 | 1 |
| Bin | 1 | 0 | 1725597 | 1 |
Port:
CRC_21(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1737131 | 1 |
| Bin | 1 | 0 | 1738729 | 1 |
Port:
CRC_21(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1753239 | 1 |
| Bin | 1 | 0 | 1754837 | 1 |
Port:
CRC_21(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1752204 | 1 |
| Bin | 1 | 0 | 1753800 | 1 |
Port:
CRC_21(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1764851 | 1 |
| Bin | 1 | 0 | 1766449 | 1 |
Port:
CRC_21(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1777838 | 1 |
| Bin | 1 | 0 | 1779434 | 1 |
Port:
SP_CONTROL(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4206 | 1 |
| Bin | 1 | 0 | 5806 | 1 |
Port:
SP_CONTROL(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25548 | 1 |
| Bin | 1 | 0 | 27148 | 1 |
Port:
SP_CONTROL_Q(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2348 | 1 |
| Bin | 1 | 0 | 3948 | 1 |
Port:
SP_CONTROL_Q(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18058 | 1 |
| Bin | 1 | 0 | 19658 | 1 |
Port:
NBT_CTRS_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
DBT_CTRS_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66645 | 1 |
| Bin | 1 | 0 | 68245 | 1 |
Port:
SYNC_CONTROL(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 99647 | 1 |
| Bin | 1 | 0 | 99642 | 1 |
Port:
SYNC_CONTROL(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91759 | 1 |
| Bin | 1 | 0 | 91764 | 1 |
Port:
SSP_RESET | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34780 | 1 |
| Bin | 1 | 0 | 36380 | 1 |
Port:
TRAN_DELAY_MEAS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35025 | 1 |
| Bin | 1 | 0 | 36625 | 1 |
Port:
TRAN_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
REC_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15179 | 1 |
| Bin | 1 | 0 | 16779 | 1 |
Port:
DECREMENT_REC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14982 | 1 |
| Bin | 1 | 0 | 16582 | 1 |
Port:
BIT_ERR_AFTER_ACK_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8 | 1 |
| Bin | 1 | 0 | 1608 | 1 |
Port:
BR_SHIFTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47787 | 1 |
| Bin | 1 | 0 | 49387 | 1 |
Port:
FORM_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 87083 | 1 |
| Bin | 1 | 0 | 88683 | 1 |
Port:
ACK_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8001 | 1 |
| Bin | 1 | 0 | 9601 | 1 |
Port:
CRC_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1612 | 1 |
| Bin | 1 | 0 | 3212 | 1 |
Port:
RETR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Port:
RETR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 132 | 1 |
| Bin | 1 | 0 | 1732 | 1 |
Port:
RETR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 255 | 1 |
| Bin | 1 | 0 | 1855 | 1 |
Port:
RETR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Signal:
TRAN_WORD_SWAPPED(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35438 | 1 |
| Bin | 1 | 0 | 37038 | 1 |
Signal:
TRAN_WORD_SWAPPED(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26739 | 1 |
| Bin | 1 | 0 | 28339 | 1 |
Signal:
TRAN_WORD_SWAPPED(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19032 | 1 |
| Bin | 1 | 0 | 20632 | 1 |
Signal:
TRAN_WORD_SWAPPED(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16938 | 1 |
| Bin | 1 | 0 | 18538 | 1 |
Signal:
TRAN_WORD_SWAPPED(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26470 | 1 |
| Bin | 1 | 0 | 28070 | 1 |
Signal:
TRAN_WORD_SWAPPED(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26680 | 1 |
| Bin | 1 | 0 | 28280 | 1 |
Signal:
TRAN_WORD_SWAPPED(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27552 | 1 |
| Bin | 1 | 0 | 29152 | 1 |
Signal:
TRAN_WORD_SWAPPED(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35377 | 1 |
| Bin | 1 | 0 | 36977 | 1 |
Signal:
TRAN_WORD_SWAPPED(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14400 | 1 |
| Bin | 1 | 0 | 16000 | 1 |
Signal:
TRAN_WORD_SWAPPED(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15059 | 1 |
| Bin | 1 | 0 | 16659 | 1 |
Signal:
TRAN_WORD_SWAPPED(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14849 | 1 |
| Bin | 1 | 0 | 16449 | 1 |
Signal:
TRAN_WORD_SWAPPED(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15821 | 1 |
| Bin | 1 | 0 | 17421 | 1 |
Signal:
TRAN_WORD_SWAPPED(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14688 | 1 |
| Bin | 1 | 0 | 16288 | 1 |
Signal:
TRAN_WORD_SWAPPED(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15846 | 1 |
| Bin | 1 | 0 | 17446 | 1 |
Signal:
TRAN_WORD_SWAPPED(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25928 | 1 |
| Bin | 1 | 0 | 27528 | 1 |
Signal:
TRAN_WORD_SWAPPED(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16627 | 1 |
| Bin | 1 | 0 | 18227 | 1 |
Signal:
TRAN_WORD_SWAPPED(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22777 | 1 |
| Bin | 1 | 0 | 24377 | 1 |
Signal:
TRAN_WORD_SWAPPED(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25704 | 1 |
| Bin | 1 | 0 | 27304 | 1 |
Signal:
TRAN_WORD_SWAPPED(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22032 | 1 |
| Bin | 1 | 0 | 23632 | 1 |
Signal:
TRAN_WORD_SWAPPED(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25833 | 1 |
| Bin | 1 | 0 | 27433 | 1 |
Signal:
TRAN_WORD_SWAPPED(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22441 | 1 |
| Bin | 1 | 0 | 24041 | 1 |
Signal:
TRAN_WORD_SWAPPED(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26355 | 1 |
| Bin | 1 | 0 | 27955 | 1 |
Signal:
TRAN_WORD_SWAPPED(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14208 | 1 |
| Bin | 1 | 0 | 15808 | 1 |
Signal:
TRAN_WORD_SWAPPED(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15135 | 1 |
| Bin | 1 | 0 | 16735 | 1 |
Signal:
TRAN_WORD_SWAPPED(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8251 | 1 |
| Bin | 1 | 0 | 9851 | 1 |
Signal:
TRAN_WORD_SWAPPED(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8670 | 1 |
| Bin | 1 | 0 | 10270 | 1 |
Signal:
TRAN_WORD_SWAPPED(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8250 | 1 |
| Bin | 1 | 0 | 9850 | 1 |
Signal:
TRAN_WORD_SWAPPED(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26016 | 1 |
| Bin | 1 | 0 | 27616 | 1 |
Signal:
TRAN_WORD_SWAPPED(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20559 | 1 |
| Bin | 1 | 0 | 22159 | 1 |
Signal:
TRAN_WORD_SWAPPED(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26228 | 1 |
| Bin | 1 | 0 | 27828 | 1 |
Signal:
TRAN_WORD_SWAPPED(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21530 | 1 |
| Bin | 1 | 0 | 23130 | 1 |
Signal:
TRAN_WORD_SWAPPED(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25986 | 1 |
| Bin | 1 | 0 | 27586 | 1 |
Signal:
ERR_FRM_REQ | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30824 | 1 |
| Bin | 1 | 0 | 32424 | 1 |
Signal:
TX_LOAD_BASE_ID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49704 | 1 |
| Bin | 1 | 0 | 51304 | 1 |
Signal:
TX_LOAD_EXT_ID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37532 | 1 |
| Bin | 1 | 0 | 39132 | 1 |
Signal:
TX_LOAD_DLC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 121205 | 1 |
| Bin | 1 | 0 | 122805 | 1 |
Signal:
TX_LOAD_DATA_WORD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 157486 | 1 |
| Bin | 1 | 0 | 159086 | 1 |
Signal:
TX_LOAD_STUFF_COUNT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40197 | 1 |
| Bin | 1 | 0 | 41797 | 1 |
Signal:
TX_LOAD_CRC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57101 | 1 |
| Bin | 1 | 0 | 58701 | 1 |
Signal:
TX_SHIFT_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55036 | 1 |
| Bin | 1 | 0 | 56636 | 1 |
Signal:
TX_DOMINANT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102910 | 1 |
| Bin | 1 | 0 | 104508 | 1 |
Signal:
RX_CLEAR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70279 | 1 |
| Bin | 1 | 0 | 71879 | 1 |
Signal:
RX_STORE_BASE_ID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53369 | 1 |
| Bin | 1 | 0 | 54969 | 1 |
Signal:
RX_STORE_EXT_ID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14167 | 1 |
| Bin | 1 | 0 | 15767 | 1 |
Signal:
RX_STORE_IDE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104516 | 1 |
| Bin | 1 | 0 | 106116 | 1 |
Signal:
RX_STORE_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 133397 | 1 |
| Bin | 1 | 0 | 134997 | 1 |
Signal:
RX_STORE_EDL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100870 | 1 |
| Bin | 1 | 0 | 102470 | 1 |
Signal:
RX_STORE_DLC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49346 | 1 |
| Bin | 1 | 0 | 50946 | 1 |
Signal:
RX_STORE_ESI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56154 | 1 |
| Bin | 1 | 0 | 57754 | 1 |
Signal:
RX_STORE_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56258 | 1 |
| Bin | 1 | 0 | 57858 | 1 |
Signal:
RX_STORE_STUFF_COUNT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26678 | 1 |
| Bin | 1 | 0 | 28278 | 1 |
Signal:
RX_SHIFT_ENA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 271239 | 1 |
| Bin | 1 | 0 | 561616 | 1 |
Signal:
RX_SHIFT_ENA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 276807 | 1 |
| Bin | 1 | 0 | 556048 | 1 |
Signal:
RX_SHIFT_ENA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 283080 | 1 |
| Bin | 1 | 0 | 549775 | 1 |
Signal:
RX_SHIFT_ENA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 296458 | 1 |
| Bin | 1 | 0 | 536397 | 1 |
Signal:
RX_SHIFT_IN_SEL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Signal:
REC_IS_RTR_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22038 | 1 |
| Bin | 1 | 0 | 23636 | 1 |
Signal:
REC_DLC_D(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564607 | 1 |
| Bin | 1 | 0 | 566201 | 1 |
Signal:
REC_DLC_D(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576164 | 1 |
| Bin | 1 | 0 | 577759 | 1 |
Signal:
REC_DLC_D(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586427 | 1 |
| Bin | 1 | 0 | 588021 | 1 |
Signal:
REC_DLC_D(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Signal:
REC_DLC_Q(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20320 | 1 |
| Bin | 1 | 0 | 21919 | 1 |
Signal:
REC_DLC_Q(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22531 | 1 |
| Bin | 1 | 0 | 24130 | 1 |
Signal:
REC_DLC_Q(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22383 | 1 |
| Bin | 1 | 0 | 23980 | 1 |
Signal:
REC_DLC_Q(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26951 | 1 |
| Bin | 1 | 0 | 28549 | 1 |
Signal:
REC_FRAME_TYPE_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28440 | 1 |
| Bin | 1 | 0 | 30036 | 1 |
Signal:
CTRL_CTR_PLOAD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 830082 | 1 |
| Bin | 1 | 0 | 831681 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16717 | 1 |
| Bin | 1 | 0 | 18317 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18114 | 1 |
| Bin | 1 | 0 | 19714 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19404 | 1 |
| Bin | 1 | 0 | 21004 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29382 | 1 |
| Bin | 1 | 0 | 30982 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 81832 | 1 |
| Bin | 1 | 0 | 83432 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152935 | 1 |
| Bin | 1 | 0 | 154534 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 266397 | 1 |
| Bin | 1 | 0 | 267996 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 400847 | 1 |
| Bin | 1 | 0 | 402445 | 1 |
Signal:
CTRL_CTR_PLOAD_VAL(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 284777 | 1 |
| Bin | 1 | 0 | 286375 | 1 |
Signal:
CTRL_CTR_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 211888 | 1 |
| Bin | 1 | 0 | 213482 | 1 |
Signal:
CTRL_CTR_ZERO | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 350694 | 1 |
| Bin | 1 | 0 | 350701 | 1 |
Signal:
CTRL_CTR_ONE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 346470 | 1 |
| Bin | 1 | 0 | 348070 | 1 |
Signal:
CTRL_COUNTED_BYTE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555551 | 1 |
| Bin | 1 | 0 | 557151 | 1 |
Signal:
CTRL_COUNTED_BYTE_INDEX(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 137781 | 1 |
| Bin | 1 | 0 | 139381 | 1 |
Signal:
CTRL_COUNTED_BYTE_INDEX(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 276272 | 1 |
| Bin | 1 | 0 | 277872 | 1 |
Signal:
CTRL_CTR_MEM_INDEX(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4934 | 1 |
| Bin | 1 | 0 | 6534 | 1 |
Signal:
CTRL_CTR_MEM_INDEX(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12610 | 1 |
| Bin | 1 | 0 | 14210 | 1 |
Signal:
CTRL_CTR_MEM_INDEX(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19144 | 1 |
| Bin | 1 | 0 | 19144 | 1 |
Signal:
CTRL_CTR_MEM_INDEX(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40973 | 1 |
| Bin | 1 | 0 | 42573 | 1 |
Signal:
CTRL_CTR_MEM_INDEX(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 68453 | 1 |
| Bin | 1 | 0 | 68453 | 1 |
Signal:
COMPL_CTR_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4533937 | 1 |
| Bin | 1 | 0 | 4535537 | 1 |
Signal:
REINTEG_CTR_CLR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170 | 1 |
| Bin | 1 | 0 | 1770 | 1 |
Signal:
REINTEG_CTR_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21938 | 1 |
| Bin | 1 | 0 | 23538 | 1 |
Signal:
REINTEG_CTR_EXPIRED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170 | 1 |
| Bin | 1 | 0 | 1770 | 1 |
Signal:
RETR_CTR_CLEAR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20123 | 1 |
| Bin | 1 | 0 | 21723 | 1 |
Signal:
RETR_CTR_ADD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10101 | 1 |
| Bin | 1 | 0 | 11701 | 1 |
Signal:
RETR_LIMIT_REACHED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1853 | 1 |
| Bin | 1 | 0 | 1853 | 1 |
Signal:
FORM_ERR_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 87083 | 1 |
| Bin | 1 | 0 | 88683 | 1 |
Signal:
ACK_ERR_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8001 | 1 |
| Bin | 1 | 0 | 9601 | 1 |
Signal:
CRC_CHECK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59432 | 1 |
| Bin | 1 | 0 | 61032 | 1 |
Signal:
BIT_ERR_ARB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1557 | 1 |
| Bin | 1 | 0 | 3157 | 1 |
Signal:
CRC_MATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27803 | 1 |
| Bin | 1 | 0 | 29403 | 1 |
Signal:
CRC_ERR_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1612 | 1 |
| Bin | 1 | 0 | 3212 | 1 |
Signal:
CRC_CLEAR_MATCH_FLAG | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56817 | 1 |
| Bin | 1 | 0 | 58417 | 1 |
Signal:
CRC_SRC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24595 | 1 |
| Bin | 1 | 0 | 26195 | 1 |
Signal:
CRC_SRC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28233 | 1 |
| Bin | 1 | 0 | 29829 | 1 |
Signal:
ERR_POS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83538 | 1 |
| Bin | 1 | 0 | 81943 | 1 |
Signal:
ERR_POS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57414 | 1 |
| Bin | 1 | 0 | 55814 | 1 |
Signal:
ERR_POS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88875 | 1 |
| Bin | 1 | 0 | 87275 | 1 |
Signal:
ERR_POS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 122492 | 1 |
| Bin | 1 | 0 | 120892 | 1 |
Signal:
RX_CRC(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 701728 | 1 |
| Bin | 1 | 0 | 1344959 | 1 |
Signal:
RX_CRC(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 617784 | 1 |
| Bin | 1 | 0 | 1265848 | 1 |
Signal:
RX_CRC(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 655293 | 1 |
| Bin | 1 | 0 | 1160355 | 1 |
Signal:
RX_CRC(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 633504 | 1 |
| Bin | 1 | 0 | 1228270 | 1 |
Signal:
RX_CRC(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1297485 | 1 |
| Bin | 1 | 0 | 2061120 | 1 |
Signal:
RX_CRC(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 734490 | 1 |
| Bin | 1 | 0 | 1192630 | 1 |
Signal:
RX_CRC(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 584639 | 1 |
| Bin | 1 | 0 | 561025 | 1 |
Signal:
RX_CRC(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564221 | 1 |
| Bin | 1 | 0 | 592790 | 1 |
Signal:
RX_CRC(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 593957 | 1 |
| Bin | 1 | 0 | 577433 | 1 |
Signal:
RX_CRC(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586188 | 1 |
| Bin | 1 | 0 | 609963 | 1 |
Signal:
RX_CRC(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 622165 | 1 |
| Bin | 1 | 0 | 598129 | 1 |
Signal:
RX_CRC(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 609198 | 1 |
| Bin | 1 | 0 | 637387 | 1 |
Signal:
RX_CRC(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 647375 | 1 |
| Bin | 1 | 0 | 618286 | 1 |
Signal:
RX_CRC(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 511003 | 1 |
| Bin | 1 | 0 | 512581 | 1 |
Signal:
RX_CRC(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522869 | 1 |
| Bin | 1 | 0 | 524443 | 1 |
Signal:
RX_CRC(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 532596 | 1 |
| Bin | 1 | 0 | 534236 | 1 |
Signal:
RX_CRC(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 542253 | 1 |
| Bin | 1 | 0 | 543880 | 1 |
Signal:
RX_CRC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555203 | 1 |
| Bin | 1 | 0 | 556735 | 1 |
Signal:
RX_CRC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564666 | 1 |
| Bin | 1 | 0 | 566279 | 1 |
Signal:
RX_CRC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576233 | 1 |
| Bin | 1 | 0 | 577836 | 1 |
Signal:
RX_CRC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586482 | 1 |
| Bin | 1 | 0 | 588092 | 1 |
Signal:
RX_STUFF_COUNT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3649 | 1 |
| Bin | 1 | 0 | 5249 | 1 |
Signal:
RX_STUFF_COUNT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7084 | 1 |
| Bin | 1 | 0 | 8683 | 1 |
Signal:
RX_STUFF_COUNT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7751 | 1 |
| Bin | 1 | 0 | 9350 | 1 |
Signal:
RX_STUFF_COUNT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6695 | 1 |
| Bin | 1 | 0 | 8295 | 1 |
Signal:
FIXED_STUFF_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13466 | 1 |
| Bin | 1 | 0 | 15066 | 1 |
Signal:
ARBITRATION_LOST_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1172 | 1 |
| Bin | 1 | 0 | 2772 | 1 |
Signal:
ARBITRATION_PART(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15717 | 1 |
| Bin | 1 | 0 | 17317 | 1 |
Signal:
ARBITRATION_PART(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52648 | 1 |
| Bin | 1 | 0 | 54248 | 1 |
Signal:
ARBITRATION_PART(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 121694 | 1 |
| Bin | 1 | 0 | 123294 | 1 |
Port:
PC_DBG_I.IS_SOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24462 | 1 |
| Bin | 1 | 0 | 26062 | 1 |
Port:
PC_DBG_I.IS_ARBITRATION | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55248 | 1 |
| Bin | 1 | 0 | 56848 | 1 |
Port:
PC_DBG_I.IS_CONTROL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50561 | 1 |
| Bin | 1 | 0 | 52161 | 1 |
Port:
PC_DBG_I.IS_DATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
PC_DBG_I.IS_STUFF_COUNT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13456 | 1 |
| Bin | 1 | 0 | 15056 | 1 |
Port:
PC_DBG_I.IS_CRC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31170 | 1 |
| Bin | 1 | 0 | 32770 | 1 |
Port:
PC_DBG_I.IS_CRC_DELIM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29717 | 1 |
| Bin | 1 | 0 | 31317 | 1 |
Port:
PC_DBG_I.IS_ACK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29563 | 1 |
| Bin | 1 | 0 | 31163 | 1 |
Port:
PC_DBG_I.IS_ACK_DELIM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28146 | 1 |
| Bin | 1 | 0 | 29746 | 1 |
Port:
PC_DBG_I.IS_EOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27259 | 1 |
| Bin | 1 | 0 | 28859 | 1 |
Port:
PC_DBG_I.IS_OVERLOAD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 529 | 1 |
| Bin | 1 | 0 | 2129 | 1 |
Port:
PC_DBG_I.IS_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26658 | 1 |
| Bin | 1 | 0 | 28253 | 1 |
Port:
PC_DBG_I.IS_INTERMISSION | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51238 | 1 |
| Bin | 1 | 0 | 52837 | 1 |
Port:
PC_DBG_I.IS_SUSPEND | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2324 | 1 |
| Bin | 1 | 0 | 3924 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: