NVC code coverage report

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST.BYTE_SHIFT_REG_GEN(1).NEXT_BYTES_GEN	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST.BYTE_SHIFT_REG_GEN(1).NEXT_BYTES_GEN

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

143:            shift_reg_in(i) <= shift_reg_q(i - 1)(7) when (byte_input_sel(i) = '0') 
144:                                                     else 
145:                                               input;

Count: 3879553
Threshold: 1

Signal assignment statement:

143: shift_reg_in(i) <= shift_reg_q(i - 1)(7) when (byte_input_sel(i) = '0')
Count: 1885965
Threshold: 1

Signal assignment statement:

145: input;
Count: 1993588
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

143: shift_reg_in(i) <= shift_reg_q(i - 1)(7) when (byte_input_sel(i) = '0')

	Evaluated to	Count	Threshold
Bin	True	1885965	1
Bin	False	1993588	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

143: shift_reg_in(i) <= shift_reg_q(i - 1)(7) when (byte_input_sel(i) = '0')

	Evaluated to	Count	Threshold
Bin	False	1993588	1
Bin	True	1885965	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST.BYTE_SHIFT_REG_GEN(1).NEXT_BYTES_GEN

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: