NVC code coverage report

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BIT_GEN(0)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(1)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(2)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(3)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(4)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_T.FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (40/40)	100.0 % (3/3)	N.A.	N.A.	100.0 % (44/44)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_T.FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_REG_COMP

100.0 % (1/1)

N.A.

100.0 % (40/40)

100.0 % (3/3)

N.A.

100.0 % (44/44)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

140: wr_en <= write and cs;
Count: 127206
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	29063051	1
Bin	1	0	29063711	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	4612	1
Bin	1	0	3952	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	44044	1
Bin	1	0	744476	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	37637	1
Bin	1	0	750883	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	35980	1
Bin	1	0	752540	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	49211	1
Bin	1	0	739309	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	36691	1
Bin	1	0	751829	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	58534	1
Bin	1	0	59194	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	4079	1
Bin	1	0	4739	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	412	1
Bin	1	0	1072	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	334	1
Bin	1	0	994	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	358	1
Bin	1	0	1018	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	362	1
Bin	1	0	1022	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1050	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	412	1
Bin	1	0	1896	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	334	1
Bin	1	0	1974	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	358	1
Bin	1	0	1950	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	362	1
Bin	1	0	1946	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1918	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	4063	1
Bin	1	0	4723	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

140:    wr_en <= write and cs; 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	4079	1
Bin	'1'	'0'	58534	1
Bin	'1'	'1'	4063	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_T.FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: