NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.SYNC_READ_GEN

File:  /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.SYNC_READ_GEN 100.0 % (2/2) 100.0 % (2/2) N.A. N.A. N.A. N.A. 100.0 % (4/4)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 197 to 199:

197:            if (rising_edge(clk_sys)) then 
198:                data_out <= int_read_data; 
199:            end if; 
Count: 683976
Threshold: 1

Signal assignment statement on line 198:

198:                data_out <= int_read_data; 
Count: 341823
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 197:

197:            if (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue3418231
BinFalse3421531

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Uncovered functional coverage:

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