NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	90.0 % (27/30)	N.A.	N.A.	99.8 % (1638/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (13/13)	N.A.	N.A.	100.0 % (105/105)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (516/516)	93.3 % (14/15)	N.A.	N.A.	99.8 % (561/562)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208: txtb_port_b_data_out <= txtb_port_b_data_out_i;
Count: 5979
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 1602
Threshold: 1

Signal assignment statement on line 277:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 91
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 1511
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 10156556
Threshold: 1

Signal assignment statement on line 283:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 10141378
Threshold: 1

Signal assignment statement on line 285:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 15178
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 96360
Threshold: 1

Signal assignment statement on line 287:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 95313
Threshold: 1

Signal assignment statement on line 289:

289: mr_tst_control_twrstb;
Count: 1047
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 705574
Threshold: 1

Signal assignment statement on line 291:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 696336
Threshold: 1

Signal assignment statement on line 293:

293: mr_tst_wdata_tst_wdata;
Count: 9238
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 85940
Threshold: 1

Signal assignment statement on line 296:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 84658
Threshold: 1

Signal assignment statement on line 298:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 1282
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 6326
Threshold: 1

Signal assignment statement on line 300:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 593
Threshold: 1

Signal assignment statement on line 302:

302: (others => '0');
Count: 5733
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	91	1
Bin	False	1511	1

	Evaluated to	Count	Threshold
Bin	True	10141378	1
Bin	False	15178	1

	Evaluated to	Count	Threshold
Bin	True	95313	1
Bin	False	1047	1

	Evaluated to	Count	Threshold
Bin	True	696336	1
Bin	False	9238	1

	Evaluated to	Count	Threshold
Bin	True	84658	1
Bin	False	1282	1

	Evaluated to	Count	Threshold
Bin	True	593	1
Bin	False	5733	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	124	1
Bin	(31)	1	0	289	1
Bin	(30)	0	1	123	1
Bin	(30)	1	0	288	1
Bin	(29)	0	1	113	1
Bin	(29)	1	0	278	1
Bin	(28)	0	1	132	1
Bin	(28)	1	0	297	1
Bin	(27)	0	1	139	1
Bin	(27)	1	0	304	1
Bin	(26)	0	1	132	1
Bin	(26)	1	0	297	1
Bin	(25)	0	1	134	1
Bin	(25)	1	0	299	1
Bin	(24)	0	1	134	1
Bin	(24)	1	0	299	1
Bin	(23)	0	1	135	1
Bin	(23)	1	0	300	1
Bin	(22)	0	1	139	1
Bin	(22)	1	0	304	1
Bin	(21)	0	1	142	1
Bin	(21)	1	0	307	1
Bin	(20)	0	1	134	1
Bin	(20)	1	0	299	1
Bin	(19)	0	1	128	1
Bin	(19)	1	0	293	1
Bin	(18)	0	1	140	1
Bin	(18)	1	0	305	1
Bin	(17)	0	1	133	1
Bin	(17)	1	0	298	1
Bin	(16)	0	1	134	1
Bin	(16)	1	0	299	1
Bin	(15)	0	1	123	1
Bin	(15)	1	0	288	1
Bin	(14)	0	1	133	1
Bin	(14)	1	0	298	1
Bin	(13)	0	1	134	1
Bin	(13)	1	0	299	1
Bin	(12)	0	1	131	1
Bin	(12)	1	0	296	1
Bin	(11)	0	1	135	1
Bin	(11)	1	0	300	1
Bin	(10)	0	1	137	1
Bin	(10)	1	0	302	1
Bin	(9)	0	1	133	1
Bin	(9)	1	0	298	1
Bin	(8)	0	1	132	1
Bin	(8)	1	0	297	1
Bin	(7)	0	1	135	1
Bin	(7)	1	0	300	1
Bin	(6)	0	1	137	1
Bin	(6)	1	0	302	1
Bin	(5)	0	1	138	1
Bin	(5)	1	0	303	1
Bin	(4)	0	1	124	1
Bin	(4)	1	0	289	1
Bin	(3)	0	1	127	1
Bin	(3)	1	0	292	1
Bin	(2)	0	1	132	1
Bin	(2)	1	0	297	1
Bin	(1)	0	1	134	1
Bin	(1)	1	0	299	1
Bin	(0)	0	1	134	1
Bin	(0)	1	0	299	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	293	1
Bin	(31)	1	0	448	1
Bin	(30)	0	1	259	1
Bin	(30)	1	0	414	1
Bin	(29)	0	1	272	1
Bin	(29)	1	0	427	1
Bin	(28)	0	1	633	1
Bin	(28)	1	0	784	1
Bin	(27)	0	1	710	1
Bin	(27)	1	0	862	1
Bin	(26)	0	1	621	1
Bin	(26)	1	0	774	1
Bin	(25)	0	1	699	1
Bin	(25)	1	0	851	1
Bin	(24)	0	1	856	1
Bin	(24)	1	0	1009	1
Bin	(23)	0	1	699	1
Bin	(23)	1	0	850	1
Bin	(22)	0	1	766	1
Bin	(22)	1	0	918	1
Bin	(21)	0	1	746	1
Bin	(21)	1	0	895	1
Bin	(20)	0	1	745	1
Bin	(20)	1	0	899	1
Bin	(19)	0	1	900	1
Bin	(19)	1	0	1050	1
Bin	(18)	0	1	928	1
Bin	(18)	1	0	1078	1
Bin	(17)	0	1	485	1
Bin	(17)	1	0	636	1
Bin	(16)	0	1	468	1
Bin	(16)	1	0	621	1
Bin	(15)	0	1	457	1
Bin	(15)	1	0	610	1
Bin	(14)	0	1	480	1
Bin	(14)	1	0	633	1
Bin	(13)	0	1	539	1
Bin	(13)	1	0	691	1
Bin	(12)	0	1	500	1
Bin	(12)	1	0	654	1
Bin	(11)	0	1	579	1
Bin	(11)	1	0	733	1
Bin	(10)	0	1	628	1
Bin	(10)	1	0	781	1
Bin	(9)	0	1	806	1
Bin	(9)	1	0	954	1
Bin	(8)	0	1	592	1
Bin	(8)	1	0	744	1
Bin	(7)	0	1	948	1
Bin	(7)	1	0	1089	1
Bin	(6)	0	1	869	1
Bin	(6)	1	0	1016	1
Bin	(5)	0	1	1003	1
Bin	(5)	1	0	1151	1
Bin	(4)	0	1	654	1
Bin	(4)	1	0	807	1
Bin	(3)	0	1	600	1
Bin	(3)	1	0	749	1
Bin	(2)	0	1	948	1
Bin	(2)	1	0	1096	1
Bin	(1)	0	1	856	1
Bin	(1)	1	0	1005	1
Bin	(0)	0	1	1145	1
Bin	(0)	1	0	1290	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	551	1
Bin	1	0	716	1

Signal:

TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101691	1
Bin	(4)	1	0	4940852	1
Bin	(3)	0	1	136075	1
Bin	(3)	1	0	4906458	1
Bin	(2)	0	1	116602	1
Bin	(2)	1	0	4926077	1
Bin	(1)	0	1	4798117	1
Bin	(1)	1	0	244856	1
Bin	(0)	0	1	3686814	1
Bin	(0)	1	0	1356763	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11578	1
Bin	1	0	11782	1

Signal:

TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	23095	1
Bin	(31)	1	0	322640	1
Bin	(30)	0	1	23818	1
Bin	(30)	1	0	321907	1
Bin	(29)	0	1	23510	1
Bin	(29)	1	0	322211	1
Bin	(28)	0	1	30231	1
Bin	(28)	1	0	315520	1
Bin	(27)	0	1	28531	1
Bin	(27)	1	0	317214	1
Bin	(26)	0	1	30066	1
Bin	(26)	1	0	315669	1
Bin	(25)	0	1	29557	1
Bin	(25)	1	0	316174	1
Bin	(24)	0	1	27505	1
Bin	(24)	1	0	318236	1
Bin	(23)	0	1	26729	1
Bin	(23)	1	0	319020	1
Bin	(22)	0	1	27182	1
Bin	(22)	1	0	318557	1
Bin	(21)	0	1	24794	1
Bin	(21)	1	0	320945	1
Bin	(20)	0	1	26974	1
Bin	(20)	1	0	318769	1
Bin	(19)	0	1	40520	1
Bin	(19)	1	0	305215	1
Bin	(18)	0	1	43417	1
Bin	(18)	1	0	302341	1
Bin	(17)	0	1	42893	1
Bin	(17)	1	0	302866	1
Bin	(16)	0	1	87810	1
Bin	(16)	1	0	257937	1
Bin	(15)	0	1	24220	1
Bin	(15)	1	0	321521	1
Bin	(14)	0	1	28110	1
Bin	(14)	1	0	317625	1
Bin	(13)	0	1	25082	1
Bin	(13)	1	0	320663	1
Bin	(12)	0	1	26102	1
Bin	(12)	1	0	319645	1
Bin	(11)	0	1	45968	1
Bin	(11)	1	0	299771	1
Bin	(10)	0	1	48242	1
Bin	(10)	1	0	297501	1
Bin	(9)	0	1	55869	1
Bin	(9)	1	0	289882	1
Bin	(8)	0	1	55357	1
Bin	(8)	1	0	290376	1
Bin	(7)	0	1	50515	1
Bin	(7)	1	0	295228	1
Bin	(6)	0	1	48415	1
Bin	(6)	1	0	297326	1
Bin	(5)	0	1	50343	1
Bin	(5)	1	0	295392	1
Bin	(4)	0	1	54680	1
Bin	(4)	1	0	291061	1
Bin	(3)	0	1	61043	1
Bin	(3)	1	0	284688	1
Bin	(2)	0	1	63069	1
Bin	(2)	1	0	282666	1
Bin	(1)	0	1	99109	1
Bin	(1)	1	0	246635	1
Bin	(0)	0	1	86857	1
Bin	(0)	1	0	258909	1

Signal:

TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3340	1
Bin	(4)	1	0	3505	1
Bin	(3)	0	1	179	1
Bin	(3)	1	0	344	1
Bin	(2)	0	1	5257	1
Bin	(2)	1	0	5422	1
Bin	(1)	0	1	4041	1
Bin	(1)	1	0	4041	1
Bin	(0)	0	1	11361	1
Bin	(0)	1	0	11526	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	293	1
Bin	(31)	1	0	448	1
Bin	(30)	0	1	259	1
Bin	(30)	1	0	414	1
Bin	(29)	0	1	272	1
Bin	(29)	1	0	427	1
Bin	(28)	0	1	633	1
Bin	(28)	1	0	784	1
Bin	(27)	0	1	710	1
Bin	(27)	1	0	862	1
Bin	(26)	0	1	621	1
Bin	(26)	1	0	774	1
Bin	(25)	0	1	699	1
Bin	(25)	1	0	851	1
Bin	(24)	0	1	856	1
Bin	(24)	1	0	1009	1
Bin	(23)	0	1	699	1
Bin	(23)	1	0	850	1
Bin	(22)	0	1	766	1
Bin	(22)	1	0	918	1
Bin	(21)	0	1	746	1
Bin	(21)	1	0	895	1
Bin	(20)	0	1	745	1
Bin	(20)	1	0	899	1
Bin	(19)	0	1	900	1
Bin	(19)	1	0	1050	1
Bin	(18)	0	1	928	1
Bin	(18)	1	0	1078	1
Bin	(17)	0	1	485	1
Bin	(17)	1	0	636	1
Bin	(16)	0	1	468	1
Bin	(16)	1	0	621	1
Bin	(15)	0	1	457	1
Bin	(15)	1	0	610	1
Bin	(14)	0	1	480	1
Bin	(14)	1	0	633	1
Bin	(13)	0	1	539	1
Bin	(13)	1	0	691	1
Bin	(12)	0	1	500	1
Bin	(12)	1	0	654	1
Bin	(11)	0	1	579	1
Bin	(11)	1	0	733	1
Bin	(10)	0	1	628	1
Bin	(10)	1	0	781	1
Bin	(9)	0	1	806	1
Bin	(9)	1	0	954	1
Bin	(8)	0	1	592	1
Bin	(8)	1	0	744	1
Bin	(7)	0	1	948	1
Bin	(7)	1	0	1089	1
Bin	(6)	0	1	869	1
Bin	(6)	1	0	1016	1
Bin	(5)	0	1	1003	1
Bin	(5)	1	0	1151	1
Bin	(4)	0	1	654	1
Bin	(4)	1	0	807	1
Bin	(3)	0	1	600	1
Bin	(3)	1	0	749	1
Bin	(2)	0	1	948	1
Bin	(2)	1	0	1096	1
Bin	(1)	0	1	856	1
Bin	(1)	1	0	1005	1
Bin	(0)	0	1	1145	1
Bin	(0)	1	0	1290	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Signal:

PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	33	1
Bin	(20)	1	0	700	1
Bin	(19)	0	1	3	1
Bin	(19)	1	0	730	1
Bin	(18)	0	1	5	1
Bin	(18)	1	0	728	1
Bin	(17)	0	1	7	1
Bin	(17)	1	0	726	1
Bin	(16)	0	1	4	1
Bin	(16)	1	0	729	1
Bin	(15)	0	1	17	1
Bin	(15)	1	0	716	1
Bin	(14)	0	1	11	1
Bin	(14)	1	0	722	1
Bin	(13)	0	1	20	1
Bin	(13)	1	0	713	1
Bin	(12)	0	1	28	1
Bin	(12)	1	0	705	1
Bin	(11)	0	1	24	1
Bin	(11)	1	0	709	1
Bin	(10)	0	1	10	1
Bin	(10)	1	0	723	1
Bin	(9)	0	1	40	1
Bin	(9)	1	0	693	1
Bin	(8)	0	1	29	1
Bin	(8)	1	0	704	1
Bin	(7)	0	1	28	1
Bin	(7)	1	0	705	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	690	1
Bin	(5)	0	1	78	1
Bin	(5)	1	0	655	1
Bin	(4)	0	1	157	1
Bin	(4)	1	0	576	1
Bin	(3)	0	1	316	1
Bin	(3)	1	0	417	1
Bin	(2)	0	1	397	1
Bin	(2)	1	0	336	1
Bin	(1)	0	1	290	1
Bin	(1)	1	0	443	1
Bin	(0)	0	1	249	1
Bin	(0)	1	0	484	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1713	1
Bin	1	0	1571	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	1402	1
Bin	1	0	1567	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

If statement on lines 277 to 280:

Signal assignment statement on line 277:

Signal assignment statement on line 280:

If statement on lines 283 to 285:

Signal assignment statement on line 283:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 287:

Signal assignment statement on line 289:

If statement on lines 291 to 293:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 296 to 298:

Signal assignment statement on line 296:

Signal assignment statement on line 298:

If statement on lines 300 to 302:

Signal assignment statement on line 300:

Signal assignment statement on line 302:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

"if" / "when" / "else" condition on line 283:

"if" / "when" / "else" condition on line 287:

"if" / "when" / "else" condition on line 291:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 300:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

"and" expression on lines 277 to 278:

Excluded expressions:

Covered expressions:

"and" expression on lines 277 to 278:

"=" expression on line 277:

"=" expression on line 283:

"=" expression on line 287:

"=" expression on line 291:

"=" expression on line 296:

"=" expression on line 300:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: