Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| CLK_GATE_TXT_BUFFER_RAM_COMP |
100.0 % (4/4) |
100.0 % (2/2) |
100.0 % (10/10) |
100.0 % (8/8) |
N.A. |
N.A. |
100.0 % (24/24) |
| TXT_BUFFER_RAM_INST |
100.0 % (55/55) |
100.0 % (38/38) |
100.0 % (2160/2160) |
100.0 % (62/62) |
N.A. |
N.A. |
100.0 % (2315/2315) |
| TXT_BUFFER_FSM_INST |
100.0 % (79/79) |
100.0 % (94/94) |
100.0 % (70/70) |
100.0 % (151/151) |
100.0 % (16/16) |
N.A. |
100.0 % (410/410) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
247: else
248: '0'; Count: 342972
Threshold: 1
Signal assignment statement:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') Count: 157246
Threshold: 1
Signal assignment statement:
248: '0'; Count: 185726
Threshold: 1
If statement:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
260: else
261: (others => '0'); Count: 160855
Threshold: 1
Signal assignment statement:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') Count: 76563
Threshold: 1
Signal assignment statement:
261: (others => '0'); Count: 84292
Threshold: 1
If statement:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
270: else
271: '1' when (mr_tst_control_tmaena = '1')
272: else
273: '0'; Count: 531960
Threshold: 1
Signal assignment statement:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') Count: 262132
Threshold: 1
Signal assignment statement:
271: '1' when (mr_tst_control_tmaena = '1') Count: 648
Threshold: 1
Signal assignment statement:
273: '0'; Count: 269180
Threshold: 1
If statement:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID)
283: else
284: '0'; Count: 408139
Threshold: 1
Signal assignment statement:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and Count: 420
Threshold: 1
Signal assignment statement:
284: '0'; Count: 407719
Threshold: 1
If statement:
294: if (res_n = '0') then
295: mr_tx_command_txce_q <= '0';
...
301: mr_tx_command_txca_q <= mr_tx_command_txca;
302: end if; Count: 1055177083
Threshold: 1
Signal assignment statement:
295: mr_tx_command_txce_q <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
296: mr_tx_command_txcr_q <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
297: mr_tx_command_txca_q <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
299: mr_tx_command_txce_q <= mr_tx_command_txce; Count: 526374300
Threshold: 1
Signal assignment statement:
300: mr_tx_command_txcr_q <= mr_tx_command_txcr; Count: 526374300
Threshold: 1
Signal assignment statement:
301: mr_tx_command_txca_q <= mr_tx_command_txca; Count: 526374300
Threshold: 1
If statement:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
306: else
307: '0'; Count: 18584
Threshold: 1
Signal assignment statement:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') Count: 105
Threshold: 1
Signal assignment statement:
307: '0'; Count: 18479
Threshold: 1
If statement:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
309: else
310: '0'; Count: 59642
Threshold: 1
Signal assignment statement:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') Count: 17842
Threshold: 1
Signal assignment statement:
310: '0'; Count: 41800
Threshold: 1
If statement:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
313: else
314: '0'; Count: 21344
Threshold: 1
Signal assignment statement:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') Count: 984
Threshold: 1
Signal assignment statement:
314: '0'; Count: 20360
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 157246 | 1 |
| Bin | False | 185726 | 1 |
"if" / "when" / "else" condition:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 76563 | 1 |
| Bin | False | 84292 | 1 |
"if" / "when" / "else" condition:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 262132 | 1 |
| Bin | False | 269828 | 1 |
"if" / "when" / "else" condition:
271: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 648 | 1 |
| Bin | False | 269180 | 1 |
"if" / "when" / "else" condition:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 420 | 1 |
| Bin | False | 407719 | 1 |
"if" / "when" / "else" condition:
294: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2418499 | 1 |
| Bin | False | 1052758584 | 1 |
"if" / "when" / "else" condition:
298: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526374300 | 1 |
| Bin | False | 526384284 | 1 |
"if" / "when" / "else" condition:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 105 | 1 |
| Bin | False | 18479 | 1 |
"if" / "when" / "else" condition:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 17842 | 1 |
| Bin | False | 41800 | 1 |
"if" / "when" / "else" condition:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 984 | 1 |
| Bin | False | 20360 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
MR_MODE_TXBBM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
Port:
MR_SETTINGS_TBFBO | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2533 | 1 |
| Bin | 1 | 0 | 943 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
Port:
MR_TX_COMMAND_TXCE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
Port:
MR_TX_COMMAND_TXCR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20943 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
Port:
MR_TX_COMMAND_TXCA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
Port:
MR_TX_COMMAND_TXBI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6540 | 1 |
| Bin | 1 | 0 | 8136 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 648 | 1 |
| Bin | 1 | 0 | 2248 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32309 | 1 |
| Bin | 1 | 0 | 35200 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3617 | 1 |
| Bin | 1 | 0 | 5217 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5031 | 1 |
| Bin | 1 | 0 | 6631 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10323 | 1 |
| Bin | 1 | 0 | 11923 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22448 | 1 |
| Bin | 1 | 0 | 24048 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44884 | 1 |
| Bin | 1 | 0 | 46484 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 235 | 1 |
| Bin | 1 | 0 | 1835 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 2114 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 979 | 1 |
| Bin | 1 | 0 | 2579 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1535 | 1 |
| Bin | 1 | 0 | 3135 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1484 | 1 |
| Bin | 1 | 0 | 3084 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1491 | 1 |
| Bin | 1 | 0 | 3091 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1631 | 1 |
| Bin | 1 | 0 | 3231 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 3245 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1629 | 1 |
| Bin | 1 | 0 | 3229 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1641 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713 | 1 |
| Bin | 1 | 0 | 3313 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1587 | 1 |
| Bin | 1 | 0 | 3187 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1526 | 1 |
| Bin | 1 | 0 | 3126 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1560 | 1 |
| Bin | 1 | 0 | 3160 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1658 | 1 |
| Bin | 1 | 0 | 3258 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1636 | 1 |
| Bin | 1 | 0 | 3236 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1632 | 1 |
| Bin | 1 | 0 | 3232 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 3270 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1575 | 1 |
| Bin | 1 | 0 | 3175 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1501 | 1 |
| Bin | 1 | 0 | 3101 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1559 | 1 |
| Bin | 1 | 0 | 3159 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1672 | 1 |
| Bin | 1 | 0 | 3272 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1681 | 1 |
| Bin | 1 | 0 | 3281 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1633 | 1 |
| Bin | 1 | 0 | 3233 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1567 | 1 |
| Bin | 1 | 0 | 3167 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1601 | 1 |
| Bin | 1 | 0 | 3201 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1637 | 1 |
| Bin | 1 | 0 | 3237 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1655 | 1 |
| Bin | 1 | 0 | 3255 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1656 | 1 |
| Bin | 1 | 0 | 3256 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1722 | 1 |
| Bin | 1 | 0 | 3322 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 582 | 1 |
| Bin | 1 | 0 | 2182 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 567 | 1 |
| Bin | 1 | 0 | 2167 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 574 | 1 |
| Bin | 1 | 0 | 2174 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 637 | 1 |
| Bin | 1 | 0 | 2237 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 652 | 1 |
| Bin | 1 | 0 | 2252 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 654 | 1 |
| Bin | 1 | 0 | 2254 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 670 | 1 |
| Bin | 1 | 0 | 2270 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 647 | 1 |
| Bin | 1 | 0 | 2247 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 634 | 1 |
| Bin | 1 | 0 | 2234 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 650 | 1 |
| Bin | 1 | 0 | 2250 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 651 | 1 |
| Bin | 1 | 0 | 2251 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 656 | 1 |
| Bin | 1 | 0 | 2256 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 641 | 1 |
| Bin | 1 | 0 | 2241 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 628 | 1 |
| Bin | 1 | 0 | 2228 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 624 | 1 |
| Bin | 1 | 0 | 2224 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 641 | 1 |
| Bin | 1 | 0 | 2241 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 623 | 1 |
| Bin | 1 | 0 | 2223 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 612 | 1 |
| Bin | 1 | 0 | 2212 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 602 | 1 |
| Bin | 1 | 0 | 2202 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 637 | 1 |
| Bin | 1 | 0 | 2237 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640 | 1 |
| Bin | 1 | 0 | 2240 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 620 | 1 |
| Bin | 1 | 0 | 2220 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 654 | 1 |
| Bin | 1 | 0 | 2254 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 652 | 1 |
| Bin | 1 | 0 | 2252 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 645 | 1 |
| Bin | 1 | 0 | 2245 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 621 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 637 | 1 |
| Bin | 1 | 0 | 2237 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 636 | 1 |
| Bin | 1 | 0 | 2236 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 651 | 1 |
| Bin | 1 | 0 | 2251 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640 | 1 |
| Bin | 1 | 0 | 2240 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61362 | 1 |
| Bin | 1 | 0 | 1030083 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67108 | 1 |
| Bin | 1 | 0 | 1024337 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63097 | 1 |
| Bin | 1 | 0 | 1028348 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91439 | 1 |
| Bin | 1 | 0 | 1000006 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79643 | 1 |
| Bin | 1 | 0 | 1011802 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76527 | 1 |
| Bin | 1 | 0 | 1014918 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88276 | 1 |
| Bin | 1 | 0 | 1003169 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78188 | 1 |
| Bin | 1 | 0 | 1013257 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70931 | 1 |
| Bin | 1 | 0 | 1020514 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108138 | 1 |
| Bin | 1 | 0 | 983307 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74867 | 1 |
| Bin | 1 | 0 | 1016578 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80468 | 1 |
| Bin | 1 | 0 | 1010977 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110009 | 1 |
| Bin | 1 | 0 | 981436 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 131558 | 1 |
| Bin | 1 | 0 | 959887 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123951 | 1 |
| Bin | 1 | 0 | 967494 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 193513 | 1 |
| Bin | 1 | 0 | 897932 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 72382 | 1 |
| Bin | 1 | 0 | 1019063 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 86120 | 1 |
| Bin | 1 | 0 | 1005325 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76572 | 1 |
| Bin | 1 | 0 | 1014873 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80428 | 1 |
| Bin | 1 | 0 | 1011017 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 97296 | 1 |
| Bin | 1 | 0 | 994149 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116973 | 1 |
| Bin | 1 | 0 | 974472 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170870 | 1 |
| Bin | 1 | 0 | 920575 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 150526 | 1 |
| Bin | 1 | 0 | 940919 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126416 | 1 |
| Bin | 1 | 0 | 965029 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109550 | 1 |
| Bin | 1 | 0 | 981895 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103929 | 1 |
| Bin | 1 | 0 | 987516 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162358 | 1 |
| Bin | 1 | 0 | 929087 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 135873 | 1 |
| Bin | 1 | 0 | 955572 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 159944 | 1 |
| Bin | 1 | 0 | 931501 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236123 | 1 |
| Bin | 1 | 0 | 855322 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 198401 | 1 |
| Bin | 1 | 0 | 893044 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640015 | 1 |
| Bin | 1 | 0 | 150105 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328560 | 1 |
| Bin | 1 | 0 | 27467073 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576099 | 1 |
| Bin | 1 | 0 | 27219534 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436079 | 1 |
| Bin | 1 | 0 | 27359554 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27015237 | 1 |
| Bin | 1 | 0 | 780396 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17655249 | 1 |
| Bin | 1 | 0 | 10140384 | 1 |
Port:
TXTB_PORT_A_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 157546 | 1 |
| Bin | 1 | 0 | 159146 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
Port:
TXTB_STATE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4860 | 1 |
| Bin | 1 | 0 | 3263 | 1 |
Port:
TXTB_STATE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12196 | 1 |
| Bin | 1 | 0 | 13793 | 1 |
Port:
TXTB_STATE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14267 | 1 |
| Bin | 1 | 0 | 15867 | 1 |
Port:
TXTB_STATE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14780 | 1 |
| Bin | 1 | 0 | 16380 | 1 |
Port:
TXTB_HW_CMD_INT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11933 | 1 |
| Bin | 1 | 0 | 13533 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24816 | 1 |
| Bin | 1 | 0 | 26416 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4237 | 1 |
| Bin | 1 | 0 | 5837 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 455 | 1 |
| Bin | 1 | 0 | 2055 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9015 | 1 |
| Bin | 1 | 0 | 10615 | 1 |
Port:
TXTB_HW_CMD_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7411 | 1 |
| Bin | 1 | 0 | 5811 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4885 | 1 |
| Bin | 1 | 0 | 6485 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5104 | 1 |
| Bin | 1 | 0 | 6704 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4826 | 1 |
| Bin | 1 | 0 | 6426 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13137 | 1 |
| Bin | 1 | 0 | 14737 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10560 | 1 |
| Bin | 1 | 0 | 12160 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13437 | 1 |
| Bin | 1 | 0 | 15037 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11280 | 1 |
| Bin | 1 | 0 | 12880 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13088 | 1 |
| Bin | 1 | 0 | 14688 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11410 | 1 |
| Bin | 1 | 0 | 13010 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12605 | 1 |
| Bin | 1 | 0 | 14205 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11211 | 1 |
| Bin | 1 | 0 | 12811 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12801 | 1 |
| Bin | 1 | 0 | 14401 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11380 | 1 |
| Bin | 1 | 0 | 12980 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12980 | 1 |
| Bin | 1 | 0 | 14580 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7275 | 1 |
| Bin | 1 | 0 | 8875 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8051 | 1 |
| Bin | 1 | 0 | 9651 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7517 | 1 |
| Bin | 1 | 0 | 9117 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8026 | 1 |
| Bin | 1 | 0 | 9626 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8058 | 1 |
| Bin | 1 | 0 | 9658 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8567 | 1 |
| Bin | 1 | 0 | 10167 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7599 | 1 |
| Bin | 1 | 0 | 9199 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7962 | 1 |
| Bin | 1 | 0 | 9562 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13451 | 1 |
| Bin | 1 | 0 | 15051 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8985 | 1 |
| Bin | 1 | 0 | 10585 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19216 | 1 |
| Bin | 1 | 0 | 20816 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15185 | 1 |
| Bin | 1 | 0 | 16785 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9841 | 1 |
| Bin | 1 | 0 | 11441 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9202 | 1 |
| Bin | 1 | 0 | 10802 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14812 | 1 |
| Bin | 1 | 0 | 16412 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13864 | 1 |
| Bin | 1 | 0 | 15464 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14634 | 1 |
| Bin | 1 | 0 | 16234 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18554 | 1 |
| Bin | 1 | 0 | 20154 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26805 | 1 |
| Bin | 1 | 0 | 28405 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3865 | 1 |
| Bin | 1 | 0 | 5465 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45730 | 1 |
| Bin | 1 | 0 | 47330 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37881 | 1 |
| Bin | 1 | 0 | 37884 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101251 | 1 |
| Bin | 1 | 0 | 102848 | 1 |
Port:
TXTB_PORT_B_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104886 | 1 |
| Bin | 1 | 0 | 106486 | 1 |
Port:
IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8227 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Port:
TXTB_AVAILABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14361 | 1 |
| Bin | 1 | 0 | 15961 | 1 |
Port:
TXTB_ALLOW_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12340 | 1 |
| Bin | 1 | 0 | 13940 | 1 |
Port:
TXTB_PARITY_CHECK_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 181146 | 1 |
| Bin | 1 | 0 | 182746 | 1 |
Port:
TXTB_PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2040 | 1 |
| Bin | 1 | 0 | 3640 | 1 |
Port:
TXTB_PARITY_ERROR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 420 | 1 |
| Bin | 1 | 0 | 2020 | 1 |
Signal:
TXTB_USER_ACCESSIBLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13940 | 1 |
| Bin | 1 | 0 | 12340 | 1 |
Signal:
TXTB_UNMASK_DATA_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12340 | 1 |
| Bin | 1 | 0 | 13940 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7982 | 1 |
| Bin | 1 | 0 | 9531 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8391 | 1 |
| Bin | 1 | 0 | 9941 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7951 | 1 |
| Bin | 1 | 0 | 9500 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21337 | 1 |
| Bin | 1 | 0 | 22803 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18079 | 1 |
| Bin | 1 | 0 | 19542 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21592 | 1 |
| Bin | 1 | 0 | 23060 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19020 | 1 |
| Bin | 1 | 0 | 20484 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21640 | 1 |
| Bin | 1 | 0 | 23098 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19308 | 1 |
| Bin | 1 | 0 | 20759 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21402 | 1 |
| Bin | 1 | 0 | 22867 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19325 | 1 |
| Bin | 1 | 0 | 20764 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21408 | 1 |
| Bin | 1 | 0 | 22873 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19799 | 1 |
| Bin | 1 | 0 | 21245 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22132 | 1 |
| Bin | 1 | 0 | 23584 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12505 | 1 |
| Bin | 1 | 0 | 14008 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13382 | 1 |
| Bin | 1 | 0 | 14882 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12705 | 1 |
| Bin | 1 | 0 | 14215 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13403 | 1 |
| Bin | 1 | 0 | 14907 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13291 | 1 |
| Bin | 1 | 0 | 14792 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14133 | 1 |
| Bin | 1 | 0 | 15641 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12866 | 1 |
| Bin | 1 | 0 | 14378 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13590 | 1 |
| Bin | 1 | 0 | 15048 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24187 | 1 |
| Bin | 1 | 0 | 25506 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14564 | 1 |
| Bin | 1 | 0 | 16054 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32866 | 1 |
| Bin | 1 | 0 | 34054 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 23359 | 1 |
| Bin | 1 | 0 | 24661 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17257 | 1 |
| Bin | 1 | 0 | 18732 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15439 | 1 |
| Bin | 1 | 0 | 16942 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25480 | 1 |
| Bin | 1 | 0 | 26827 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24873 | 1 |
| Bin | 1 | 0 | 26216 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26244 | 1 |
| Bin | 1 | 0 | 27591 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34015 | 1 |
| Bin | 1 | 0 | 35197 | 1 |
Signal:
TXTB_PARITY_ERROR_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 420 | 1 |
| Bin | 1 | 0 | 2020 | 1 |
Signal:
MR_TX_COMMAND_TXCE_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
Signal:
MR_TX_COMMAND_TXCR_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20883 | 1 |
| Bin | 1 | 0 | 22483 | 1 |
Signal:
MR_TX_COMMAND_TXCA_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 3334 | 1 |
Signal:
TX_COMMAND_TXCE_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
Signal:
TX_COMMAND_TXCR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17842 | 1 |
| Bin | 1 | 0 | 19442 | 1 |
Signal:
ABORT_APPLIED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 984 | 1 |
| Bin | 1 | 0 | 2584 | 1 |
Signal:
ABORT_OR_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 984 | 1 |
| Bin | 1 | 0 | 2584 | 1 |
Signal:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 157246 | 1 |
| Bin | 1 | 0 | 158846 | 1 |
Signal:
TXTB_RAM_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 262780 | 1 |
| Bin | 1 | 0 | 264380 | 1 |
Signal:
CLK_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14047312 | 1 |
| Bin | 1 | 0 | 14048912 | 1 |
Signal:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2040 | 1 |
| Bin | 1 | 0 | 3640 | 1 |
Covered expressions:
"=" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 185426 | 1 |
| Bin | True | 157546 | 1 |
"=" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14540 | 1 |
| Bin | True | 328432 | 1 |
"and" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
<-------LHS--------> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 171186 | 1 |
| Bin | True | False | 300 | 1 |
| Bin | True | True | 157246 | 1 |
"=" expression
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 84292 | 1 |
| Bin | True | 76563 | 1 |
"=" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 427074 | 1 |
| Bin | True | 104886 | 1 |
"=" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 374714 | 1 |
| Bin | True | 157246 | 1 |
"or" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 269828 | 1 |
| Bin | False | True | 157246 | 1 |
| Bin | True | False | 104886 | 1 |
"=" expression
271: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 269180 | 1 |
| Bin | True | 648 | 1 |
"=" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 403082 | 1 |
| Bin | True | 5057 | 1 |
"=" expression
281: txtb_parity_check_valid = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 224954 | 1 |
| Bin | True | 183185 | 1 |
"and" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 180706 | 1 |
| Bin | True | False | 2578 | 1 |
| Bin | True | True | 2479 | 1 |
"=" expression
282: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 191399 | 1 |
| Bin | True | 216740 | 1 |
"and" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 216320 | 1 |
| Bin | True | False | 2059 | 1 |
| Bin | True | True | 420 | 1 |
"=" expression
294: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052758584 | 1 |
| Bin | True | 2418499 | 1 |
"=" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 18210 | 1 |
| Bin | True | 374 | 1 |
"=" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 11854 | 1 |
| Bin | True | 6730 | 1 |
"and" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 6625 | 1 |
| Bin | True | False | 269 | 1 |
| Bin | True | True | 105 | 1 |
"=" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 26705 | 1 |
| Bin | True | 32937 | 1 |
"=" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 29472 | 1 |
| Bin | True | 30170 | 1 |
"and" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 12328 | 1 |
| Bin | True | False | 15095 | 1 |
| Bin | True | True | 17842 | 1 |
"=" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 19605 | 1 |
| Bin | True | 1739 | 1 |
"=" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 12841 | 1 |
| Bin | True | 8503 | 1 |
"and" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 7519 | 1 |
| Bin | True | False | 755 | 1 |
| Bin | True | True | 984 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: