NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CLK_GATE_TXT_BUFFER_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
TXT_BUFFER_RAM_INST	100.0 % (56/56)	100.0 % (38/38)	100.0 % (2160/2160)	94.8 % (55/58)	N.A.	N.A.	99.8 % (2309/2312)
TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CLK_GATE_TXT_BUFFER_RAM_COMP

100.0 % (5/5)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (25/25)

TXT_BUFFER_RAM_INST

100.0 % (56/56)

100.0 % (38/38)

100.0 % (2160/2160)

94.8 % (55/58)

N.A.

99.8 % (2309/2312)

TXT_BUFFER_FSM_INST

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST	100.0 % (32/32)	100.0 % (20/20)	100.0 % (462/462)	100.0 % (53/53)	N.A.	N.A.	100.0 % (567/567)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST

100.0 % (32/32)

100.0 % (20/20)

100.0 % (462/462)

100.0 % (53/53)

N.A.

100.0 % (567/567)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

246:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
247:                             else 
248:                         '0';

Count: 353248
Threshold: 1

Signal assignment statement on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 161965
Threshold: 1

Signal assignment statement on line 248:

248: '0';
Count: 191283
Threshold: 1

If statement on lines 259 to 261:

259:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
260:                                                   else 
261:                                    (others => '0');

Count: 163819
Threshold: 1

Signal assignment statement on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 78291
Threshold: 1

Signal assignment statement on line 261:

261: (others => '0');
Count: 85528
Threshold: 1

If statement on lines 269 to 273:

269:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
270:                           else 
271:                       '1' when (mr_tst_control_tmaena = '1') 
272:                           else 
273:                       '0';

Count: 544014
Threshold: 1

Signal assignment statement on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 268157
Threshold: 1

Signal assignment statement on line 271:

271: '1' when (mr_tst_control_tmaena = '1')
Count: 648
Threshold: 1

Signal assignment statement on line 273:

273: '0';
Count: 275209
Threshold: 1

If statement on lines 280 to 284:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID) 
283:                                     else 
284:                                 '0';

Count: 413990
Threshold: 1

Signal assignment statement on line 280:

280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 411
Threshold: 1

Signal assignment statement on line 284:

284: '0';
Count: 413579
Threshold: 1

Signal assignment statement on line 286:

286: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 4024
Threshold: 1

If statement on lines 294 to 302:

294:        if (res_n = '0') then 
295:            mr_tx_command_txce_q <= '0'; 
...
301:            mr_tx_command_txca_q <= mr_tx_command_txca; 
302:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 295:

295: mr_tx_command_txce_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 296:

296: mr_tx_command_txcr_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 297:

297: mr_tx_command_txca_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 299:

299: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 543791678
Threshold: 1

Signal assignment statement on line 300:

300: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 543791678
Threshold: 1

Signal assignment statement on line 301:

301: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 543791678
Threshold: 1

If statement on lines 305 to 307:

305:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
306:                                 else 
307:                             '0';

Count: 18612
Threshold: 1

Signal assignment statement on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 105
Threshold: 1

Signal assignment statement on line 307:

307: '0';
Count: 18507
Threshold: 1

If statement on lines 308 to 310:

308:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
309:                                 else 
310:                             '0';

Count: 60558
Threshold: 1

Signal assignment statement on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 18261
Threshold: 1

Signal assignment statement on line 310:

310: '0';
Count: 42297
Threshold: 1

If statement on lines 312 to 314:

312:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
313:                         else 
314:                     '0';

Count: 21372
Threshold: 1

Signal assignment statement on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 984
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 20388
Threshold: 1

Signal assignment statement on line 317:

317: abort_or_skipped <= abort_applied;
Count: 5170
Threshold: 1

Signal assignment statement on line 405:

405: txtb_parity_mismatch <= parity_mismatch;
Count: 6922
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	161965	1
Bin	False	191283	1

"if" / "when" / "else" condition on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	78291	1
Bin	False	85528	1

"if" / "when" / "else" condition on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	268157	1
Bin	False	275857	1

"if" / "when" / "else" condition on line 271:

271: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	648	1
Bin	False	275209	1

"if" / "when" / "else" condition on lines 280 to 282:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	411	1
Bin	False	413579	1

"if" / "when" / "else" condition on line 294:

294: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 298:

298: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	105	1
Bin	False	18507	1

"if" / "when" / "else" condition on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	18261	1
Bin	False	42297	1

"if" / "when" / "else" condition on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	984	1
Bin	False	20388	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	584	1
Bin	(31)	1	0	2185	1
Bin	(30)	0	1	577	1
Bin	(30)	1	0	2178	1
Bin	(29)	0	1	579	1
Bin	(29)	1	0	2180	1
Bin	(28)	0	1	648	1
Bin	(28)	1	0	2249	1
Bin	(27)	0	1	636	1
Bin	(27)	1	0	2237	1
Bin	(26)	0	1	655	1
Bin	(26)	1	0	2256	1
Bin	(25)	0	1	646	1
Bin	(25)	1	0	2247	1
Bin	(24)	0	1	635	1
Bin	(24)	1	0	2236	1
Bin	(23)	0	1	656	1
Bin	(23)	1	0	2257	1
Bin	(22)	0	1	637	1
Bin	(22)	1	0	2238	1
Bin	(21)	0	1	659	1
Bin	(21)	1	0	2260	1
Bin	(20)	0	1	654	1
Bin	(20)	1	0	2255	1
Bin	(19)	0	1	662	1
Bin	(19)	1	0	2263	1
Bin	(18)	0	1	663	1
Bin	(18)	1	0	2264	1
Bin	(17)	0	1	634	1
Bin	(17)	1	0	2235	1
Bin	(16)	0	1	600	1
Bin	(16)	1	0	2201	1
Bin	(15)	0	1	629	1
Bin	(15)	1	0	2230	1
Bin	(14)	0	1	625	1
Bin	(14)	1	0	2226	1
Bin	(13)	0	1	619	1
Bin	(13)	1	0	2220	1
Bin	(12)	0	1	633	1
Bin	(12)	1	0	2234	1
Bin	(11)	0	1	609	1
Bin	(11)	1	0	2210	1
Bin	(10)	0	1	624	1
Bin	(10)	1	0	2225	1
Bin	(9)	0	1	625	1
Bin	(9)	1	0	2226	1
Bin	(8)	0	1	614	1
Bin	(8)	1	0	2215	1
Bin	(7)	0	1	648	1
Bin	(7)	1	0	2249	1
Bin	(6)	0	1	646	1
Bin	(6)	1	0	2247	1
Bin	(5)	0	1	644	1
Bin	(5)	1	0	2245	1
Bin	(4)	0	1	608	1
Bin	(4)	1	0	2209	1
Bin	(3)	0	1	641	1
Bin	(3)	1	0	2242	1
Bin	(2)	0	1	630	1
Bin	(2)	1	0	2231	1
Bin	(1)	0	1	642	1
Bin	(1)	1	0	2243	1
Bin	(0)	0	1	625	1
Bin	(0)	1	0	2226	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	4873	1
Bin	(3)	1	0	3276	1
Bin	(2)	0	1	12609	1
Bin	(2)	1	0	14206	1
Bin	(1)	0	1	14688	1
Bin	(1)	1	0	16288	1
Bin	(0)	0	1	15211	1
Bin	(0)	1	0	16812	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	12358	1
Bin	1	0	13959	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25275	1
Bin	LOCK	1	0	26876	1
Bin	VALID	0	1	11112	1
Bin	VALID	1	0	12713	1
Bin	ERR	0	1	4262	1
Bin	ERR	1	0	5863	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9436	1
Bin	FAILED	1	0	11037	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	4997	1
Bin	(31)	1	0	6598	1
Bin	(30)	0	1	5038	1
Bin	(30)	1	0	6639	1
Bin	(29)	0	1	4814	1
Bin	(29)	1	0	6415	1
Bin	(28)	0	1	13147	1
Bin	(28)	1	0	14748	1
Bin	(27)	0	1	11116	1
Bin	(27)	1	0	12717	1
Bin	(26)	0	1	12663	1
Bin	(26)	1	0	14264	1
Bin	(25)	0	1	11161	1
Bin	(25)	1	0	12762	1
Bin	(24)	0	1	13436	1
Bin	(24)	1	0	15037	1
Bin	(23)	0	1	11459	1
Bin	(23)	1	0	13060	1
Bin	(22)	0	1	13565	1
Bin	(22)	1	0	15166	1
Bin	(21)	0	1	10818	1
Bin	(21)	1	0	12419	1
Bin	(20)	0	1	13167	1
Bin	(20)	1	0	14768	1
Bin	(19)	0	1	11677	1
Bin	(19)	1	0	13278	1
Bin	(18)	0	1	13134	1
Bin	(18)	1	0	14735	1
Bin	(17)	0	1	7988	1
Bin	(17)	1	0	9589	1
Bin	(16)	0	1	8115	1
Bin	(16)	1	0	9716	1
Bin	(15)	0	1	8123	1
Bin	(15)	1	0	9724	1
Bin	(14)	0	1	8545	1
Bin	(14)	1	0	10146	1
Bin	(13)	0	1	8332	1
Bin	(13)	1	0	9933	1
Bin	(12)	0	1	8829	1
Bin	(12)	1	0	10430	1
Bin	(11)	0	1	8999	1
Bin	(11)	1	0	10600	1
Bin	(10)	0	1	9409	1
Bin	(10)	1	0	11010	1
Bin	(9)	0	1	13116	1
Bin	(9)	1	0	14717	1
Bin	(8)	0	1	8630	1
Bin	(8)	1	0	10231	1
Bin	(7)	0	1	19323	1
Bin	(7)	1	0	20924	1
Bin	(6)	0	1	14678	1
Bin	(6)	1	0	16279	1
Bin	(5)	0	1	10427	1
Bin	(5)	1	0	12028	1
Bin	(4)	0	1	9736	1
Bin	(4)	1	0	11337	1
Bin	(3)	0	1	14443	1
Bin	(3)	1	0	16044	1
Bin	(2)	0	1	14970	1
Bin	(2)	1	0	16571	1
Bin	(1)	0	1	15756	1
Bin	(1)	1	0	17357	1
Bin	(0)	0	1	19089	1
Bin	(0)	1	0	20690	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	14782	1
Bin	1	0	16383	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	12758	1
Bin	1	0	14359	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1860	1
Bin	1	0	3461	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	411	1
Bin	1	0	2012	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	14359	1
Bin	1	0	12758	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	12758	1
Bin	1	0	14359	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8196	1
Bin	(31)	1	0	9747	1
Bin	(30)	0	1	8279	1
Bin	(30)	1	0	9830	1
Bin	(29)	0	1	7965	1
Bin	(29)	1	0	9516	1
Bin	(28)	0	1	22115	1
Bin	(28)	1	0	23579	1
Bin	(27)	0	1	18547	1
Bin	(27)	1	0	20024	1
Bin	(26)	0	1	20808	1
Bin	(26)	1	0	22271	1
Bin	(25)	0	1	18728	1
Bin	(25)	1	0	20187	1
Bin	(24)	0	1	22083	1
Bin	(24)	1	0	23556	1
Bin	(23)	0	1	19176	1
Bin	(23)	1	0	20631	1
Bin	(22)	0	1	21513	1
Bin	(22)	1	0	22971	1
Bin	(21)	0	1	19521	1
Bin	(21)	1	0	20962	1
Bin	(20)	0	1	21310	1
Bin	(20)	1	0	22779	1
Bin	(19)	0	1	20038	1
Bin	(19)	1	0	21481	1
Bin	(18)	0	1	21634	1
Bin	(18)	1	0	23086	1
Bin	(17)	0	1	13269	1
Bin	(17)	1	0	14774	1
Bin	(16)	0	1	13435	1
Bin	(16)	1	0	14941	1
Bin	(15)	0	1	13227	1
Bin	(15)	1	0	14736	1
Bin	(14)	0	1	13738	1
Bin	(14)	1	0	15246	1
Bin	(13)	0	1	13395	1
Bin	(13)	1	0	14896	1
Bin	(12)	0	1	13849	1
Bin	(12)	1	0	15347	1
Bin	(11)	0	1	13820	1
Bin	(11)	1	0	15329	1
Bin	(10)	0	1	15348	1
Bin	(10)	1	0	16799	1
Bin	(9)	0	1	24174	1
Bin	(9)	1	0	25497	1
Bin	(8)	0	1	14700	1
Bin	(8)	1	0	16192	1
Bin	(7)	0	1	33045	1
Bin	(7)	1	0	34246	1
Bin	(6)	0	1	23230	1
Bin	(6)	1	0	24534	1
Bin	(5)	0	1	18006	1
Bin	(5)	1	0	19484	1
Bin	(4)	0	1	15787	1
Bin	(4)	1	0	17280	1
Bin	(3)	0	1	25683	1
Bin	(3)	1	0	27032	1
Bin	(2)	0	1	26512	1
Bin	(2)	1	0	27847	1
Bin	(1)	0	1	27253	1
Bin	(1)	1	0	28583	1
Bin	(0)	0	1	35110	1
Bin	(0)	1	0	36295	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	411	1
Bin	1	0	2012	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	1955	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	21327	1
Bin	1	0	22928	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	1734	1
Bin	1	0	3335	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1706	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	18261	1
Bin	1	0	19862	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	984	1
Bin	1	0	2585	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	984	1
Bin	1	0	2585	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	161965	1
Bin	1	0	163566	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	268805	1
Bin	1	0	270406	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	15269429	1
Bin	1	0	15271030	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1860	1
Bin	1	0	3461	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 246:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	176324	1
Bin	True	False	300	1
Bin	True	True	161965	1

"=" expression on line 246:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	190983	1
Bin	True	162265	1

"=" expression on line 246:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	14959	1
Bin	True	338289	1

"=" expression on line 259:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	85528	1
Bin	True	78291	1

"or" expression on line 269:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	275857	1
Bin	False	True	161965	1
Bin	True	False	106192	1

"=" expression on line 269:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	437822	1
Bin	True	106192	1

"=" expression on line 269:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	382049	1
Bin	True	161965	1

"=" expression on line 271:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	275209	1
Bin	True	648	1

"and" expression on lines 280 to 282:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	221257	1
Bin	True	False	1938	1
Bin	True	True	411	1

"and" expression on lines 280 to 281:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	183196	1
Bin	True	False	2669	1
Bin	True	True	2349	1

"=" expression on line 280:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	408972	1
Bin	True	5018	1

"=" expression on line 281:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	228445	1
Bin	True	185545	1

"=" expression on line 282:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	192322	1
Bin	True	221668	1

"=" expression on line 294:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"and" expression on line 305:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	6638	1
Bin	True	False	269	1
Bin	True	True	105	1

"=" expression on line 305:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	18238	1
Bin	True	374	1

"=" expression on line 305:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	11869	1
Bin	True	6743	1

"and" expression on line 308:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	12748	1
Bin	True	False	15132	1
Bin	True	True	18261	1

"=" expression on line 308:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	27165	1
Bin	True	33393	1

"=" expression on line 308:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	29549	1
Bin	True	31009	1

"and" expression on line 312:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	7532	1
Bin	True	False	755	1
Bin	True	True	984	1

"=" expression on line 312:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	19633	1
Bin	True	1739	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	12856	1
Bin	True	8516	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

Signal assignment statement on line 246:

Signal assignment statement on line 248:

If statement on lines 259 to 261:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

If statement on lines 269 to 273:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 273:

If statement on lines 280 to 284:

Signal assignment statement on line 280:

Signal assignment statement on line 284:

Signal assignment statement on line 286:

If statement on lines 294 to 302:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Signal assignment statement on line 297:

Signal assignment statement on line 299:

Signal assignment statement on line 300:

Signal assignment statement on line 301:

If statement on lines 305 to 307:

Signal assignment statement on line 305:

Signal assignment statement on line 307:

If statement on lines 308 to 310:

Signal assignment statement on line 308:

Signal assignment statement on line 310:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

Signal assignment statement on line 317:

Signal assignment statement on line 405:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

"if" / "when" / "else" condition on line 259:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 271:

"if" / "when" / "else" condition on lines 280 to 282:

"if" / "when" / "else" condition on line 294:

"if" / "when" / "else" condition on line 298:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

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