NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TEST_REGISTERS_REG_MAP_COMP	100.0 % (264/264)	100.0 % (343/343)	100.0 % (1064/1064)	100.0 % (286/286)	N.A.	100.0 % (7/7)	100.0 % (1964/1964)
TXT_BUF_TEST_DATA_PADDING_GEN(0)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(1)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
TXT_BUF_TEST_DATA_PADDING_GEN(3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
TXT_BUF_TEST_DATA_PADDING_GEN(4)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
TXT_BUF_TEST_DATA_PADDING_GEN(5)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
TXT_BUF_TEST_DATA_PADDING_GEN(6)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
TXT_BUF_TEST_DATA_PADDING_GEN(7)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

TEST_REGISTERS_REG_MAP_COMP

100.0 % (264/264)

100.0 % (343/343)

100.0 % (1064/1064)

100.0 % (286/286)

N.A.

100.0 % (7/7)

100.0 % (1964/1964)

TXT_BUF_TEST_DATA_PADDING_GEN(0)

100.0 % (1/1)

N.A.

100.0 % (1/1)

TXT_BUF_TEST_DATA_PADDING_GEN(1)

100.0 % (1/1)

N.A.

100.0 % (1/1)

TXT_BUF_TEST_DATA_PADDING_GEN(2)

100.0 % (2/2)

N.A.

100.0 % (2/2)

TXT_BUF_TEST_DATA_PADDING_GEN(3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

TXT_BUF_TEST_DATA_PADDING_GEN(4)

100.0 % (2/2)

N.A.

100.0 % (2/2)

TXT_BUF_TEST_DATA_PADDING_GEN(5)

100.0 % (2/2)

N.A.

100.0 % (2/2)

TXT_BUF_TEST_DATA_PADDING_GEN(6)

100.0 % (2/2)

N.A.

100.0 % (2/2)

TXT_BUF_TEST_DATA_PADDING_GEN(7)

100.0 % (2/2)

N.A.

100.0 % (2/2)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE	100.0 % (11/11)	100.0 % (10/10)	N.A.	N.A.	N.A.	N.A.	100.0 % (21/21)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE

100.0 % (11/11)

100.0 % (10/10)

N.A.

100.0 % (21/21)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement on lines 528 to 538:

528:        with mr_tst_out_i.tst_dest_tst_mtgt select mr_tst_in.tst_rdata_tst_rdata <= 
529:                 mr_tst_rdata_tst_rdata_rxb when TMTGT_RXBUF, 
...
537:            mr_tst_rdata_tst_rdata_txb_i(7) when TMTGT_TXTBUF8, 
538:                            (others => '0') when others;

Count: 70955
Threshold: 1

Signal assignment statement on line 529:

529: mr_tst_rdata_tst_rdata_rxb when TMTGT_RXBUF,
Count: 50191
Threshold: 1

Signal assignment statement on line 530:

530: mr_tst_rdata_tst_rdata_txb_i(0) when TMTGT_TXTBUF1,
Count: 3111
Threshold: 1

Signal assignment statement on line 531:

531: mr_tst_rdata_tst_rdata_txb_i(1) when TMTGT_TXTBUF2,
Count: 2923
Threshold: 1

Signal assignment statement on line 532:

532: mr_tst_rdata_tst_rdata_txb_i(2) when TMTGT_TXTBUF3,
Count: 2663
Threshold: 1

Signal assignment statement on line 533:

533: mr_tst_rdata_tst_rdata_txb_i(3) when TMTGT_TXTBUF4,
Count: 2433
Threshold: 1

Signal assignment statement on line 534:

534: mr_tst_rdata_tst_rdata_txb_i(4) when TMTGT_TXTBUF5,
Count: 839
Threshold: 1

Signal assignment statement on line 535:

535: mr_tst_rdata_tst_rdata_txb_i(5) when TMTGT_TXTBUF6,
Count: 765
Threshold: 1

Signal assignment statement on line 536:

536: mr_tst_rdata_tst_rdata_txb_i(6) when TMTGT_TXTBUF7,
Count: 822
Threshold: 1

Signal assignment statement on line 537:

537: mr_tst_rdata_tst_rdata_txb_i(7) when TMTGT_TXTBUF8,
Count: 747
Threshold: 1

Signal assignment statement on line 538:

538: (others => '0') when others;
Count: 6461
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice on line 529:

529: mr_tst_rdata_tst_rdata_rxb when TMTGT_RXBUF,

	Choice of	Count	Threshold
Bin	`TMTGT_RXBUF`	50191	1

"case" / "with" / "select" choice on line 530:

530: mr_tst_rdata_tst_rdata_txb_i(0) when TMTGT_TXTBUF1,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF1`	3111	1

"case" / "with" / "select" choice on line 531:

531: mr_tst_rdata_tst_rdata_txb_i(1) when TMTGT_TXTBUF2,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF2`	2923	1

"case" / "with" / "select" choice on line 532:

532: mr_tst_rdata_tst_rdata_txb_i(2) when TMTGT_TXTBUF3,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF3`	2663	1

"case" / "with" / "select" choice on line 533:

533: mr_tst_rdata_tst_rdata_txb_i(3) when TMTGT_TXTBUF4,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF4`	2433	1

"case" / "with" / "select" choice on line 534:

534: mr_tst_rdata_tst_rdata_txb_i(4) when TMTGT_TXTBUF5,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF5`	839	1

"case" / "with" / "select" choice on line 535:

535: mr_tst_rdata_tst_rdata_txb_i(5) when TMTGT_TXTBUF6,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF6`	765	1

"case" / "with" / "select" choice on line 536:

536: mr_tst_rdata_tst_rdata_txb_i(6) when TMTGT_TXTBUF7,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF7`	822	1

"case" / "with" / "select" choice on line 537:

537: mr_tst_rdata_tst_rdata_txb_i(7) when TMTGT_TXTBUF8,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF8`	747	1

"case" / "with" / "select" choice on line 538:

538: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	6461	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement on lines 528 to 538:

Signal assignment statement on line 529:

Signal assignment statement on line 530:

Signal assignment statement on line 531:

Signal assignment statement on line 532:

Signal assignment statement on line 533:

Signal assignment statement on line 534:

Signal assignment statement on line 535:

Signal assignment statement on line 536:

Signal assignment statement on line 537:

Signal assignment statement on line 538:

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice on line 529:

"case" / "with" / "select" choice on line 530:

"case" / "with" / "select" choice on line 531:

"case" / "with" / "select" choice on line 532:

"case" / "with" / "select" choice on line 533:

"case" / "with" / "select" choice on line 534:

"case" / "with" / "select" choice on line 535:

"case" / "with" / "select" choice on line 536:

"case" / "with" / "select" choice on line 537:

"case" / "with" / "select" choice on line 538:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: