NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TEST_REGISTERS_REG_MAP_COMP	100.0 % (254/254)	100.0 % (343/343)	100.0 % (1064/1064)	100.0 % (286/286)	N.A.	100.0 % (7/7)	100.0 % (1954/1954)
TXT_BUF_TEST_DATA_PADDING_GEN(0)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXT_BUF_TEST_DATA_PADDING_GEN(1)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXT_BUF_TEST_DATA_PADDING_GEN(2)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(3)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(4)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(5)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(6)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_TEST_DATA_PADDING_GEN(7)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE	100.0 % (11/11)	100.0 % (10/10)	N.A.	N.A.	N.A.	N.A.	100.0 % (21/21)

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement:

528:        with mr_tst_out_i.tst_dest_tst_mtgt select mr_tst_in.tst_rdata_tst_rdata <= 
529:                 mr_tst_rdata_tst_rdata_rxb when TMTGT_RXBUF, 
...
537:            mr_tst_rdata_tst_rdata_txb_i(7) when TMTGT_TXTBUF8, 
538:                            (others => '0') when others;

Count: 70914
Threshold: 1

Signal assignment statement:

529: mr_tst_rdata_tst_rdata_rxb when TMTGT_RXBUF,
Count: 50126
Threshold: 1

Signal assignment statement:

530: mr_tst_rdata_tst_rdata_txb_i(0) when TMTGT_TXTBUF1,
Count: 3116
Threshold: 1

Signal assignment statement:

531: mr_tst_rdata_tst_rdata_txb_i(1) when TMTGT_TXTBUF2,
Count: 2937
Threshold: 1

Signal assignment statement:

532: mr_tst_rdata_tst_rdata_txb_i(2) when TMTGT_TXTBUF3,
Count: 2659
Threshold: 1

Signal assignment statement:

533: mr_tst_rdata_tst_rdata_txb_i(3) when TMTGT_TXTBUF4,
Count: 2422
Threshold: 1

Signal assignment statement:

534: mr_tst_rdata_tst_rdata_txb_i(4) when TMTGT_TXTBUF5,
Count: 851
Threshold: 1

Signal assignment statement:

535: mr_tst_rdata_tst_rdata_txb_i(5) when TMTGT_TXTBUF6,
Count: 790
Threshold: 1

Signal assignment statement:

536: mr_tst_rdata_tst_rdata_txb_i(6) when TMTGT_TXTBUF7,
Count: 819
Threshold: 1

Signal assignment statement:

537: mr_tst_rdata_tst_rdata_txb_i(7) when TMTGT_TXTBUF8,
Count: 737
Threshold: 1

Signal assignment statement:

538: (others => '0') when others;
Count: 6457
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

529: mr_tst_rdata_tst_rdata_rxb when TMTGT_RXBUF,

	Choice of	Count	Threshold
Bin	`TMTGT_RXBUF`	50126	1

"case" / "with" / "select" choice:

530: mr_tst_rdata_tst_rdata_txb_i(0) when TMTGT_TXTBUF1,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF1`	3116	1

"case" / "with" / "select" choice:

531: mr_tst_rdata_tst_rdata_txb_i(1) when TMTGT_TXTBUF2,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF2`	2937	1

"case" / "with" / "select" choice:

532: mr_tst_rdata_tst_rdata_txb_i(2) when TMTGT_TXTBUF3,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF3`	2659	1

"case" / "with" / "select" choice:

533: mr_tst_rdata_tst_rdata_txb_i(3) when TMTGT_TXTBUF4,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF4`	2422	1

"case" / "with" / "select" choice:

534: mr_tst_rdata_tst_rdata_txb_i(4) when TMTGT_TXTBUF5,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF5`	851	1

"case" / "with" / "select" choice:

535: mr_tst_rdata_tst_rdata_txb_i(5) when TMTGT_TXTBUF6,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF6`	790	1

"case" / "with" / "select" choice:

536: mr_tst_rdata_tst_rdata_txb_i(6) when TMTGT_TXTBUF7,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF7`	819	1

"case" / "with" / "select" choice:

537: mr_tst_rdata_tst_rdata_txb_i(7) when TMTGT_TXTBUF8,

	Choice of	Count	Threshold
Bin	`TMTGT_TXTBUF8`	737	1

"case" / "with" / "select" choice:

538: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	6457	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: