NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
GEN_FILT_POS	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (12/12)	N.A.	N.A.	100.0 % (17/17)
GEN_FILTRAN_NEG	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.RANGE_FILTER_INST	100.0 % (7/7)	N.A.	100.0 % (178/178)	N.A.	N.A.	N.A.	100.0 % (185/185)

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement:

142: ID_reg_to_decimal(filter_input, value_dec);
Count: 110565
Threshold: 1

Sequential statement:

144: ID_reg_to_decimal(filter_upp_th, upper_th_dec);
Count: 3206
Threshold: 1

Sequential statement:

145: ID_reg_to_decimal(filter_low_th, lower_th_dec);
Count: 3206
Threshold: 1

Variable assignment statement:

133: base := ID_reg(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
Count: 116977
Threshold: 1

Variable assignment statement:

134: ext := ID_reg(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
Count: 116977
Threshold: 1

Variable assignment statement:

135: conc := base&ext;
Count: 116977
Threshold: 1

Signal assignment statement:

136: ID_dec <= to_integer(unsigned(conc));
Count: 116977
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

FILTER_UPP_TH(28)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_UPP_TH(27)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_UPP_TH(26)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(25)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(24)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(23)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_UPP_TH(22)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(21)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(20)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(19)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(18)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_UPP_TH(17)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(16)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(15)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(14)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(13)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(12)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(11)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(10)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(9)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(8)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(7)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(6)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(5)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(4)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(3)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(2)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(1)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_UPP_TH(0)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(28)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(27)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(26)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(25)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(24)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(23)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(22)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_LOW_TH(21)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_LOW_TH(20)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_LOW_TH(19)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(18)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

FILTER_LOW_TH(17)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(16)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(15)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(14)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(13)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(12)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(11)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(10)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(9)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(8)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(7)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(6)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(5)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(4)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(3)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(2)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(1)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_LOW_TH(0)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

FILTER_INPUT(28)

	From	To	Count	Threshold
Bin	0	1	34332	1
Bin	1	0	30165	1

Port:

FILTER_INPUT(27)

	From	To	Count	Threshold
Bin	0	1	20951	1
Bin	1	0	16748	1

Port:

FILTER_INPUT(26)

	From	To	Count	Threshold
Bin	0	1	34995	1
Bin	1	0	29978	1

Port:

FILTER_INPUT(25)

	From	To	Count	Threshold
Bin	0	1	26409	1
Bin	1	0	21440	1

Port:

FILTER_INPUT(24)

	From	To	Count	Threshold
Bin	0	1	37621	1
Bin	1	0	32560	1

Port:

FILTER_INPUT(23)

	From	To	Count	Threshold
Bin	0	1	27574	1
Bin	1	0	22162	1

Port:

FILTER_INPUT(22)

	From	To	Count	Threshold
Bin	0	1	37576	1
Bin	1	0	32729	1

Port:

FILTER_INPUT(21)

	From	To	Count	Threshold
Bin	0	1	26623	1
Bin	1	0	21662	1

Port:

FILTER_INPUT(20)

	From	To	Count	Threshold
Bin	0	1	34131	1
Bin	1	0	30013	1

Port:

FILTER_INPUT(19)

	From	To	Count	Threshold
Bin	0	1	25018	1
Bin	1	0	20939	1

Port:

FILTER_INPUT(18)

	From	To	Count	Threshold
Bin	0	1	35861	1
Bin	1	0	31802	1

Port:

FILTER_INPUT(17)

	From	To	Count	Threshold
Bin	0	1	6676	1
Bin	1	0	77411	1

Port:

FILTER_INPUT(16)

	From	To	Count	Threshold
Bin	0	1	6481	1
Bin	1	0	76980	1

Port:

FILTER_INPUT(15)

	From	To	Count	Threshold
Bin	0	1	6016	1
Bin	1	0	75936	1

Port:

FILTER_INPUT(14)

	From	To	Count	Threshold
Bin	0	1	6457	1
Bin	1	0	77301	1

Port:

FILTER_INPUT(13)

	From	To	Count	Threshold
Bin	0	1	6203	1
Bin	1	0	75854	1

Port:

FILTER_INPUT(12)

	From	To	Count	Threshold
Bin	0	1	6655	1
Bin	1	0	77348	1

Port:

FILTER_INPUT(11)

	From	To	Count	Threshold
Bin	0	1	6116	1
Bin	1	0	76014	1

Port:

FILTER_INPUT(10)

	From	To	Count	Threshold
Bin	0	1	6759	1
Bin	1	0	77172	1

Port:

FILTER_INPUT(9)

	From	To	Count	Threshold
Bin	0	1	6340	1
Bin	1	0	76882	1

Port:

FILTER_INPUT(8)

	From	To	Count	Threshold
Bin	0	1	7191	1
Bin	1	0	78168	1

Port:

FILTER_INPUT(7)

	From	To	Count	Threshold
Bin	0	1	6170	1
Bin	1	0	76119	1

Port:

FILTER_INPUT(6)

	From	To	Count	Threshold
Bin	0	1	6636	1
Bin	1	0	77753	1

Port:

FILTER_INPUT(5)

	From	To	Count	Threshold
Bin	0	1	6122	1
Bin	1	0	76213	1

Port:

FILTER_INPUT(4)

	From	To	Count	Threshold
Bin	0	1	6712	1
Bin	1	0	78180	1

Port:

FILTER_INPUT(3)

	From	To	Count	Threshold
Bin	0	1	6213	1
Bin	1	0	76204	1

Port:

FILTER_INPUT(2)

	From	To	Count	Threshold
Bin	0	1	7044	1
Bin	1	0	78347	1

Port:

FILTER_INPUT(1)

	From	To	Count	Threshold
Bin	0	1	6316	1
Bin	1	0	75925	1

Port:

FILTER_INPUT(0)

	From	To	Count	Threshold
Bin	0	1	6757	1
Bin	1	0	77490	1

Port:

ENABLE

	From	To	Count	Threshold
Bin	0	1	1606	1
Bin	1	0	1606	1

Port:

VALID

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	1771	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.RANGE_FILTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement:

Sequential statement:

Sequential statement:

Variable assignment statement:

Variable assignment statement:

Variable assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

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Covered toggles:

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