NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.DATA_EDGE_DETECTOR_INST	100.0 % (17/17)	100.0 % (12/12)	100.0 % (28/28)	100.0 % (35/35)	N.A.	N.A.	100.0 % (92/92)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

161:        if (res_n = '0') then 
162:            rx_data_prev        <= RECESSIVE; 
...
171:            end if; 
172:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

162: rx_data_prev <= RECESSIVE;
Count: 2418499
Threshold: 1

Signal assignment statement:

163: tx_data_prev <= RECESSIVE;
Count: 2418499
Threshold: 1

Signal assignment statement:

164: rx_data_sync_prev <= RECESSIVE;
Count: 2418499
Threshold: 1

Signal assignment statement:

166: rx_data_prev <= rx_data;
Count: 526374300
Threshold: 1

Signal assignment statement:

167: tx_data_prev <= tx_data;
Count: 526374300
Threshold: 1

If statement:

169:            if (tq_edge = '1') then 
170:                rx_data_sync_prev <= rx_data; 
171:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

170: rx_data_sync_prev <= rx_data;
Count: 331533534
Threshold: 1

If statement:

180:    tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE) 
181:                     else 
182:                 '0';

Count: 2539748
Threshold: 1

Signal assignment statement:

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)
Count: 635365
Threshold: 1

Signal assignment statement:

182: '0';
Count: 1904383
Threshold: 1

If statement:

189:    rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE) 
190:                     else 
191:                 '0';

Count: 5597348
Threshold: 1

Signal assignment statement:

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)
Count: 1399296
Threshold: 1

Signal assignment statement:

191: '0';
Count: 4198052
Threshold: 1

If statement:

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1') 
205:                     else 
206:                 '0';

Count: 226118655
Threshold: 1

Signal assignment statement:

201: sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and
Count: 1555148
Threshold: 1

Signal assignment statement:

206: '0';
Count: 224563507
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

161: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

165: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

169: if (tq_edge = '1') then

	Evaluated to	Count	Threshold
Bin	True	331533534	1
Bin	False	194840766	1

"if" / "when" / "else" condition:

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	True	635365	1
Bin	False	1904383	1

"if" / "when" / "else" condition:

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	True	1399296	1
Bin	False	4198052	1

"if" / "when" / "else" condition:

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1')

	Evaluated to	Count	Threshold
Bin	True	1555148	1
Bin	False	224563507	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

TX_DATA

	From	To	Count	Threshold
Bin	0	1	635336	1
Bin	1	0	633738	1

Port:

RX_DATA

	From	To	Count	Threshold
Bin	0	1	1400896	1
Bin	1	0	1399296	1

Port:

PREV_RX_SAMPLE

	From	To	Count	Threshold
Bin	0	1	1390558	1
Bin	1	0	1388958	1

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	108871268	1
Bin	1	0	108872865	1

Port:

TX_EDGE

	From	To	Count	Threshold
Bin	0	1	635365	1
Bin	1	0	636965	1

Port:

RX_EDGE

	From	To	Count	Threshold
Bin	0	1	1399296	1
Bin	1	0	1400896	1

Port:

SYNC_EDGE

	From	To	Count	Threshold
Bin	0	1	1555148	1
Bin	1	0	1556748	1

Signal:

RX_DATA_PREV

	From	To	Count	Threshold
Bin	0	1	1400896	1
Bin	1	0	1399296	1

Signal:

TX_DATA_PREV

	From	To	Count	Threshold
Bin	0	1	635336	1
Bin	1	0	633738	1

Signal:

RX_DATA_SYNC_PREV

	From	To	Count	Threshold
Bin	0	1	1399426	1
Bin	1	0	1397826	1

Signal:

RX_EDGE_I

	From	To	Count	Threshold
Bin	0	1	1399296	1
Bin	1	0	1400896	1

Signal:

TX_EDGE_I

	From	To	Count	Threshold
Bin	0	1	635365	1
Bin	1	0	636965	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

161: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

169: if (tq_edge = '1') then

	Evaluated to	Count	Threshold
Bin	False	194840766	1
Bin	True	331533534	1

"/=" expression

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	False	1270674	1
Bin	True	1269074	1

"=" expression

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	False	1269047	1
Bin	True	1270701	1

"and" expression

180:    tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE) 
                               <---------LHS--------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	635336	1
Bin	True	False	633709	1
Bin	True	True	635365	1

"/=" expression

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	False	2798806	1
Bin	True	2798542	1

"=" expression

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	False	2799091	1
Bin	True	2798257	1

"and" expression

189:    rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE) 
                               <---------LHS--------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1398961	1
Bin	True	False	1399246	1
Bin	True	True	1399296	1

"/=" expression

201: sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and

	Evaluated to	Count	Threshold
Bin	False	222044332	1
Bin	True	4074323	1

"=" expression

202: (rx_data_sync_prev = RECESSIVE) and

	Evaluated to	Count	Threshold
Bin	False	76658244	1
Bin	True	149460411	1

"and" expression

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and

	LHS	RHS	Count	Threshold
Bin	False	True	147425325	1
Bin	True	False	2039237	1
Bin	True	True	2035086	1

"/=" expression

203: (prev_rx_sample /= rx_data) and

	Evaluated to	Count	Threshold
Bin	False	185788801	1
Bin	True	40329854	1

"and" expression

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and

	LHS	RHS	Count	Threshold
Bin	False	True	38301070	1
Bin	True	False	6302	1
Bin	True	True	2028784	1

"=" expression

204: (tq_edge = '1')

	Evaluated to	Count	Threshold
Bin	False	109530885	1
Bin	True	116587770	1

"and" expression

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	115032622	1
Bin	True	False	473636	1
Bin	True	True	1555148	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.DATA_EDGE_DETECTOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/data_edge_detector.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"/=" expression

"=" expression

"and" expression

"/=" expression

"=" expression

"and" expression

"/=" expression

"=" expression

"and" expression

"/=" expression

"and" expression

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: