NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.DATA_EDGE_DETECTOR_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (28/28)	100.0 % (35/35)	N.A.	N.A.	100.0 % (94/94)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.DATA_EDGE_DETECTOR_INST

100.0 % (19/19)

100.0 % (12/12)

100.0 % (28/28)

100.0 % (35/35)

N.A.

100.0 % (94/94)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 161 to 172:

161:        if (res_n = '0') then 
162:            rx_data_prev        <= RECESSIVE; 
...
171:            end if; 
172:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 162:

162: rx_data_prev <= RECESSIVE;
Count: 2424883
Threshold: 1

Signal assignment statement on line 163:

163: tx_data_prev <= RECESSIVE;
Count: 2424883
Threshold: 1

Signal assignment statement on line 164:

164: rx_data_sync_prev <= RECESSIVE;
Count: 2424883
Threshold: 1

Signal assignment statement on line 166:

166: rx_data_prev <= rx_data;
Count: 543791678
Threshold: 1

Signal assignment statement on line 167:

167: tx_data_prev <= tx_data;
Count: 543791678
Threshold: 1

If statement on lines 169 to 171:

169:            if (tq_edge = '1') then 
170:                rx_data_sync_prev <= rx_data; 
171:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 170:

170: rx_data_sync_prev <= rx_data;
Count: 343847624
Threshold: 1

If statement on lines 180 to 182:

180:    tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE) 
181:                     else 
182:                 '0';

Count: 2533595
Threshold: 1

Signal assignment statement on line 180:

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)
Count: 633828
Threshold: 1

Signal assignment statement on line 182:

182: '0';
Count: 1899767
Threshold: 1

If statement on lines 189 to 191:

189:    rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE) 
190:                     else 
191:                 '0';

Count: 5603702
Threshold: 1

Signal assignment statement on line 189:

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)
Count: 1400928
Threshold: 1

Signal assignment statement on line 191:

191: '0';
Count: 4202774
Threshold: 1

If statement on lines 201 to 206:

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1') 
205:                     else 
206:                 '0';

Count: 229735331
Threshold: 1

Signal assignment statement on line 201:

201: sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and
Count: 1555192
Threshold: 1

Signal assignment statement on line 206:

206: '0';
Count: 228180139
Threshold: 1

Signal assignment statement on line 211:

211: rx_edge <= rx_edge_i;
Count: 2805057
Threshold: 1

Signal assignment statement on line 212:

212: tx_edge <= tx_edge_i;
Count: 1270858
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 161:

161: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 165:

165: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 169:

169: if (tq_edge = '1') then

	Evaluated to	Count	Threshold
Bin	True	343847624	1
Bin	False	199944054	1

"if" / "when" / "else" condition on line 180:

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	True	633828	1
Bin	False	1899767	1

"if" / "when" / "else" condition on line 189:

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	True	1400928	1
Bin	False	4202774	1

"if" / "when" / "else" condition on lines 201 to 204:

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1')

	Evaluated to	Count	Threshold
Bin	True	1555192	1
Bin	False	228180139	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_DATA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_DATA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PREV_RX_SAMPLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TQ_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TX_EDGE

	From	To	Count	Threshold
Bin	0	1	633828	1
Bin	1	0	635429	1

Port:

RX_EDGE

	From	To	Count	Threshold
Bin	0	1	1400928	1
Bin	1	0	1402528	1

Port:

SYNC_EDGE

	From	To	Count	Threshold
Bin	0	1	1555192	1
Bin	1	0	1556793	1

Signal:

RX_DATA_PREV

	From	To	Count	Threshold
Bin	0	1	1402528	1
Bin	1	0	1400927	1

Signal:

TX_DATA_PREV

	From	To	Count	Threshold
Bin	0	1	633797	1
Bin	1	0	632200	1

Signal:

RX_DATA_SYNC_PREV

	From	To	Count	Threshold
Bin	0	1	1401026	1
Bin	1	0	1399425	1

Signal:

RX_EDGE_I

	From	To	Count	Threshold
Bin	0	1	1400928	1
Bin	1	0	1402528	1

Signal:

TX_EDGE_I

	From	To	Count	Threshold
Bin	0	1	633828	1
Bin	1	0	635429	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 161:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 169:

tq_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	199944054	1
Bin	True	343847624	1

"and" expression on line 180:

 (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE) 
  <---------LHS--------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	633797	1
Bin	True	False	632169	1
Bin	True	True	633828	1

"/=" expression on line 180:

tx_data_prev /= tx_data

	Evaluated to	Count	Threshold
Bin	False	1267598	1
Bin	True	1265997	1

"=" expression on line 180:

tx_data_prev = RECESSIVE

	Evaluated to	Count	Threshold
Bin	False	1265970	1
Bin	True	1267625	1

"and" expression on line 189:

 (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE) 
  <---------LHS--------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1400637	1
Bin	True	False	1400876	1
Bin	True	True	1400928	1

"/=" expression on line 189:

rx_data_prev /= rx_data

	Evaluated to	Count	Threshold
Bin	False	2801898	1
Bin	True	2801804	1

"=" expression on line 189:

rx_data_prev = RECESSIVE

	Evaluated to	Count	Threshold
Bin	False	2802137	1
Bin	True	2801565	1

"and" expression on lines 201 to 204:

 (rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and (prev_rx_sample /= rx_data) and (tq_edge = '1') 
 <----------------------------------------------LHS----------------------------------------------->      <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	116855758	1
Bin	True	False	470674	1
Bin	True	True	1555192	1

"and" expression on lines 201 to 203:

 (rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and (prev_rx_sample /= rx_data) 
 <------------------------------LHS------------------------------->      <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	37893058	1
Bin	True	False	5914	1
Bin	True	True	2025866	1

"and" expression on lines 201 to 202:

 (rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) 
  <-----------LHS------------>       <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	151586557	1
Bin	True	False	2035696	1
Bin	True	True	2031780	1

"/=" expression on line 201:

rx_data_sync_prev /= rx_data

	Evaluated to	Count	Threshold
Bin	False	225667855	1
Bin	True	4067476	1

"=" expression on line 202:

rx_data_sync_prev = RECESSIVE

	Evaluated to	Count	Threshold
Bin	False	76116994	1
Bin	True	153618337	1

"/=" expression on line 203:

prev_rx_sample /= rx_data

	Evaluated to	Count	Threshold
Bin	False	189816407	1
Bin	True	39918924	1

"=" expression on line 204:

tq_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	111324381	1
Bin	True	118410950	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.DATA_EDGE_DETECTOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 161 to 172:

Signal assignment statement on line 162:

Signal assignment statement on line 163:

Signal assignment statement on line 164:

Signal assignment statement on line 166:

Signal assignment statement on line 167:

If statement on lines 169 to 171:

Signal assignment statement on line 170:

If statement on lines 180 to 182:

Signal assignment statement on line 180:

Signal assignment statement on line 182:

If statement on lines 189 to 191:

Signal assignment statement on line 189:

Signal assignment statement on line 191:

If statement on lines 201 to 206:

Signal assignment statement on line 201:

Signal assignment statement on line 206:

Signal assignment statement on line 211:

Signal assignment statement on line 212:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 161:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 180:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on lines 201 to 204:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 161:

"=" expression on line 169:

"and" expression on line 180:

"/=" expression on line 180:

"=" expression on line 180:

"and" expression on line 189:

"/=" expression on line 189:

"=" expression on line 189:

"and" expression on lines 201 to 204:

"and" expression on lines 201 to 203:

"and" expression on lines 201 to 202:

"/=" expression on line 201:

"=" expression on line 202:

"/=" expression on line 203:

"=" expression on line 204:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: