NVC code coverage report

NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)
SYNC_READ_GEN	100.0 % (2/2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST	100.0 % (1/1)	N.A.	100.0 % (1578/1578)	N.A.	N.A.	N.A.	100.0 % (1579/1579)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

191: int_read_data <= ram_memory(to_integer(unsigned(addr_B)));
Count: 109007
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13640743	1
Bin	1	0	13641403	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	2844	1
Bin	1	0	2844	1

Port:

ADDR_A(4)

	From	To	Count	Threshold
Bin	0	1	249177	1
Bin	1	0	24490131	1

Port:

ADDR_A(3)

	From	To	Count	Threshold
Bin	0	1	396317	1
Bin	1	0	24342955	1

Port:

ADDR_A(2)

	From	To	Count	Threshold
Bin	0	1	299363	1
Bin	1	0	24440323	1

Port:

ADDR_A(1)

	From	To	Count	Threshold
Bin	0	1	24190026	1
Bin	1	0	550460	1

Port:

ADDR_A(0)

	From	To	Count	Threshold
Bin	0	1	15933488	1
Bin	1	0	8808687	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	45992	1
Bin	1	0	46757	1

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	26137	1
Bin	1	0	755481	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	28439	1
Bin	1	0	753177	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	26928	1
Bin	1	0	754680	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	43833	1
Bin	1	0	737801	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	37427	1
Bin	1	0	744199	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	35755	1
Bin	1	0	745867	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	48972	1
Bin	1	0	732670	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	36476	1
Bin	1	0	745188	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	35264	1
Bin	1	0	746390	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	44313	1
Bin	1	0	737319	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	38609	1
Bin	1	0	743041	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	37036	1
Bin	1	0	744618	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	64114	1
Bin	1	0	717522	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	80461	1
Bin	1	0	701208	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	78460	1
Bin	1	0	703192	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	137847	1
Bin	1	0	643805	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	33084	1
Bin	1	0	748556	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	41608	1
Bin	1	0	740040	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	36008	1
Bin	1	0	745634	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	40010	1
Bin	1	0	741652	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	58183	1
Bin	1	0	723447	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	61092	1
Bin	1	0	720542	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	78858	1
Bin	1	0	702782	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	80475	1
Bin	1	0	701165	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	68584	1
Bin	1	0	713108	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	64854	1
Bin	1	0	716800	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	65729	1
Bin	1	0	715917	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	81874	1
Bin	1	0	699730	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	88367	1
Bin	1	0	693275	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	97980	1
Bin	1	0	683671	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	161690	1
Bin	1	0	619955	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	137224	1
Bin	1	0	644504	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	24721305	1
Bin	1	0	28617	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	24721613	1
Bin	1	0	28309	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	24633047	1
Bin	1	0	116875	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	24634059	1
Bin	1	0	115863	1

Port:

ADDR_B(4)

	From	To	Count	Threshold
Bin	0	1	10675	1
Bin	1	0	11335	1

Port:

ADDR_B(3)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	1148	1

Port:

ADDR_B(2)

	From	To	Count	Threshold
Bin	0	1	15796	1
Bin	1	0	16456	1

Port:

ADDR_B(1)

	From	To	Count	Threshold
Bin	0	1	13033	1
Bin	1	0	13033	1

Port:

ADDR_B(0)

	From	To	Count	Threshold
Bin	0	1	35766	1
Bin	1	0	36426	1

Port:

DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	797	1
Bin	1	0	1417	1

Port:

DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	824	1
Bin	1	0	1444	1

Port:

DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	888	1
Bin	1	0	1508	1

Port:

DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	2429	1
Bin	1	0	3038	1

Port:

DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	2410	1
Bin	1	0	3009	1

Port:

DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	2341	1
Bin	1	0	2951	1

Port:

DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	2351	1
Bin	1	0	2956	1

Port:

DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	2251	1
Bin	1	0	2861	1

Port:

DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	2638	1
Bin	1	0	3241	1

Port:

DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Port:

DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	2750	1
Bin	1	0	3346	1

Port:

DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Port:

DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	2365	1
Bin	1	0	2962	1

Port:

DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	2495	1
Bin	1	0	3095	1

Port:

DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	1523	1
Bin	1	0	2137	1

Port:

DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	1651	1
Bin	1	0	2267	1

Port:

DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	1565	1
Bin	1	0	2180	1

Port:

DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	1605	1
Bin	1	0	2219	1

Port:

DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	1539	1
Bin	1	0	2155	1

Port:

DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	1729	1
Bin	1	0	2341	1

Port:

DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	1747	1
Bin	1	0	2361	1

Port:

DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	1696	1
Bin	1	0	2311	1

Port:

DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	2507	1
Bin	1	0	3109	1

Port:

DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	1680	1
Bin	1	0	2293	1

Port:

DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	3152	1
Bin	1	0	3741	1

Port:

DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	2395	1
Bin	1	0	2993	1

Port:

DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	2387	1
Bin	1	0	2999	1

Port:

DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	1721	1
Bin	1	0	2337	1

Port:

DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	1906	1
Bin	1	0	2506	1

Port:

DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	2312	1
Bin	1	0	2911	1

Port:

DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	2184	1
Bin	1	0	2778	1

Port:

DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	2823	1
Bin	1	0	3416	1

Signal:

RAM_MEMORY(0)(31)

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	16178	1

Signal:

RAM_MEMORY(0)(30)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	16175	1

Signal:

RAM_MEMORY(0)(29)

	From	To	Count	Threshold
Bin	0	1	134	1
Bin	1	0	16134	1

Signal:

RAM_MEMORY(0)(28)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	16178	1

Signal:

RAM_MEMORY(0)(27)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16137	1

Signal:

RAM_MEMORY(0)(26)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	16256	1

Signal:

RAM_MEMORY(0)(25)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	16227	1

Signal:

RAM_MEMORY(0)(24)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	16217	1

Signal:

RAM_MEMORY(0)(23)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	16219	1

Signal:

RAM_MEMORY(0)(22)

	From	To	Count	Threshold
Bin	0	1	237	1
Bin	1	0	16206	1

Signal:

RAM_MEMORY(0)(21)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	16146	1

Signal:

RAM_MEMORY(0)(20)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16188	1

Signal:

RAM_MEMORY(0)(19)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	16253	1

Signal:

RAM_MEMORY(0)(18)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16188	1

Signal:

RAM_MEMORY(0)(17)

	From	To	Count	Threshold
Bin	0	1	157	1
Bin	1	0	16128	1

Signal:

RAM_MEMORY(0)(16)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	16166	1

Signal:

RAM_MEMORY(0)(15)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	14149	1

Signal:

RAM_MEMORY(0)(14)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	14125	1

Signal:

RAM_MEMORY(0)(13)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	14128	1

Signal:

RAM_MEMORY(0)(12)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	14169	1

Signal:

RAM_MEMORY(0)(11)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	14129	1

Signal:

RAM_MEMORY(0)(10)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	14129	1

Signal:

RAM_MEMORY(0)(9)

	From	To	Count	Threshold
Bin	0	1	887	1
Bin	1	0	15578	1

Signal:

RAM_MEMORY(0)(8)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	14125	1

Signal:

RAM_MEMORY(0)(7)

	From	To	Count	Threshold
Bin	0	1	1267	1
Bin	1	0	13932	1

Signal:

RAM_MEMORY(0)(6)

	From	To	Count	Threshold
Bin	0	1	986	1
Bin	1	0	13814	1

Signal:

RAM_MEMORY(0)(5)

	From	To	Count	Threshold
Bin	0	1	504	1
Bin	1	0	13525	1

Signal:

RAM_MEMORY(0)(4)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	13316	1

Signal:

RAM_MEMORY(0)(3)

	From	To	Count	Threshold
Bin	0	1	752	1
Bin	1	0	13549	1

Signal:

RAM_MEMORY(0)(2)

	From	To	Count	Threshold
Bin	0	1	876	1
Bin	1	0	13714	1

Signal:

RAM_MEMORY(0)(1)

	From	To	Count	Threshold
Bin	0	1	843	1
Bin	1	0	13651	1

Signal:

RAM_MEMORY(0)(0)

	From	To	Count	Threshold
Bin	0	1	883	1
Bin	1	0	13701	1

Signal:

RAM_MEMORY(1)(31)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	12768	1

Signal:

RAM_MEMORY(1)(30)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	12825	1

Signal:

RAM_MEMORY(1)(29)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	12806	1

Signal:

RAM_MEMORY(1)(28)

	From	To	Count	Threshold
Bin	0	1	1009	1
Bin	1	0	13456	1

Signal:

RAM_MEMORY(1)(27)

	From	To	Count	Threshold
Bin	0	1	998	1
Bin	1	0	13416	1

Signal:

RAM_MEMORY(1)(26)

	From	To	Count	Threshold
Bin	0	1	983	1
Bin	1	0	13463	1

Signal:

RAM_MEMORY(1)(25)

	From	To	Count	Threshold
Bin	0	1	1043	1
Bin	1	0	13471	1

Signal:

RAM_MEMORY(1)(24)

	From	To	Count	Threshold
Bin	0	1	1008	1
Bin	1	0	13439	1

Signal:

RAM_MEMORY(1)(23)

	From	To	Count	Threshold
Bin	0	1	977	1
Bin	1	0	13467	1

Signal:

RAM_MEMORY(1)(22)

	From	To	Count	Threshold
Bin	0	1	1007	1
Bin	1	0	13482	1

Signal:

RAM_MEMORY(1)(21)

	From	To	Count	Threshold
Bin	0	1	1057	1
Bin	1	0	13503	1

Signal:

RAM_MEMORY(1)(20)

	From	To	Count	Threshold
Bin	0	1	1033	1
Bin	1	0	13487	1

Signal:

RAM_MEMORY(1)(19)

	From	To	Count	Threshold
Bin	0	1	1016	1
Bin	1	0	13467	1

Signal:

RAM_MEMORY(1)(18)

	From	To	Count	Threshold
Bin	0	1	987	1
Bin	1	0	13420	1

Signal:

RAM_MEMORY(1)(17)

	From	To	Count	Threshold
Bin	0	1	605	1
Bin	1	0	13137	1

Signal:

RAM_MEMORY(1)(16)

	From	To	Count	Threshold
Bin	0	1	654	1
Bin	1	0	13147	1

Signal:

RAM_MEMORY(1)(15)

	From	To	Count	Threshold
Bin	0	1	634	1
Bin	1	0	14179	1

Signal:

RAM_MEMORY(1)(14)

	From	To	Count	Threshold
Bin	0	1	579	1
Bin	1	0	14222	1

Signal:

RAM_MEMORY(1)(13)

	From	To	Count	Threshold
Bin	0	1	528	1
Bin	1	0	14095	1

Signal:

RAM_MEMORY(1)(12)

	From	To	Count	Threshold
Bin	0	1	621	1
Bin	1	0	14179	1

Signal:

RAM_MEMORY(1)(11)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	14178	1

Signal:

RAM_MEMORY(1)(10)

	From	To	Count	Threshold
Bin	0	1	676	1
Bin	1	0	14144	1

Signal:

RAM_MEMORY(1)(9)

	From	To	Count	Threshold
Bin	0	1	550	1
Bin	1	0	14046	1

Signal:

RAM_MEMORY(1)(8)

	From	To	Count	Threshold
Bin	0	1	646	1
Bin	1	0	14240	1

Signal:

RAM_MEMORY(1)(7)

	From	To	Count	Threshold
Bin	0	1	604	1
Bin	1	0	14057	1

Signal:

RAM_MEMORY(1)(6)

	From	To	Count	Threshold
Bin	0	1	618	1
Bin	1	0	14173	1

Signal:

RAM_MEMORY(1)(5)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	14232	1

Signal:

RAM_MEMORY(1)(4)

	From	To	Count	Threshold
Bin	0	1	596	1
Bin	1	0	14225	1

Signal:

RAM_MEMORY(1)(3)

	From	To	Count	Threshold
Bin	0	1	598	1
Bin	1	0	14107	1

Signal:

RAM_MEMORY(1)(2)

	From	To	Count	Threshold
Bin	0	1	689	1
Bin	1	0	14286	1

Signal:

RAM_MEMORY(1)(1)

	From	To	Count	Threshold
Bin	0	1	649	1
Bin	1	0	14303	1

Signal:

RAM_MEMORY(1)(0)

	From	To	Count	Threshold
Bin	0	1	638	1
Bin	1	0	14244	1

Signal:

RAM_MEMORY(2)(31)

	From	To	Count	Threshold
Bin	0	1	262	1
Bin	1	0	15032	1

Signal:

RAM_MEMORY(2)(30)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	15026	1

Signal:

RAM_MEMORY(2)(29)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	15015	1

Signal:

RAM_MEMORY(2)(28)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	15003	1

Signal:

RAM_MEMORY(2)(27)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	15002	1

Signal:

RAM_MEMORY(2)(26)

	From	To	Count	Threshold
Bin	0	1	251	1
Bin	1	0	15040	1

Signal:

RAM_MEMORY(2)(25)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	14983	1

Signal:

RAM_MEMORY(2)(24)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	15019	1

Signal:

RAM_MEMORY(2)(23)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	14884	1

Signal:

RAM_MEMORY(2)(22)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	14919	1

Signal:

RAM_MEMORY(2)(21)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	14908	1

Signal:

RAM_MEMORY(2)(20)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	14912	1

Signal:

RAM_MEMORY(2)(19)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	14861	1

Signal:

RAM_MEMORY(2)(18)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	14870	1

Signal:

RAM_MEMORY(2)(17)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	14972	1

Signal:

RAM_MEMORY(2)(16)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	14853	1

Signal:

RAM_MEMORY(2)(15)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	14987	1

Signal:

RAM_MEMORY(2)(14)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	14968	1

Signal:

RAM_MEMORY(2)(13)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	15013	1

Signal:

RAM_MEMORY(2)(12)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	14992	1

Signal:

RAM_MEMORY(2)(11)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	14963	1

Signal:

RAM_MEMORY(2)(10)

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	15021	1

Signal:

RAM_MEMORY(2)(9)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	14984	1

Signal:

RAM_MEMORY(2)(8)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	14976	1

Signal:

RAM_MEMORY(2)(7)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	14863	1

Signal:

RAM_MEMORY(2)(6)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	14823	1

Signal:

RAM_MEMORY(2)(5)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	14856	1

Signal:

RAM_MEMORY(2)(4)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	14822	1

Signal:

RAM_MEMORY(2)(3)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	14856	1

Signal:

RAM_MEMORY(2)(2)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	14874	1

Signal:

RAM_MEMORY(2)(1)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	14931	1

Signal:

RAM_MEMORY(2)(0)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	14844	1

Signal:

RAM_MEMORY(3)(31)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	14268	1

Signal:

RAM_MEMORY(3)(30)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	14238	1

Signal:

RAM_MEMORY(3)(29)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	14252	1

Signal:

RAM_MEMORY(3)(28)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	14333	1

Signal:

RAM_MEMORY(3)(27)

	From	To	Count	Threshold
Bin	0	1	292	1
Bin	1	0	14355	1

Signal:

RAM_MEMORY(3)(26)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	14243	1

Signal:

RAM_MEMORY(3)(25)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	14242	1

Signal:

RAM_MEMORY(3)(24)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	14289	1

Signal:

RAM_MEMORY(3)(23)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	14348	1

Signal:

RAM_MEMORY(3)(22)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	14340	1

Signal:

RAM_MEMORY(3)(21)

	From	To	Count	Threshold
Bin	0	1	209	1
Bin	1	0	14302	1

Signal:

RAM_MEMORY(3)(20)

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	14377	1

Signal:

RAM_MEMORY(3)(19)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	14344	1

Signal:

RAM_MEMORY(3)(18)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	14326	1

Signal:

RAM_MEMORY(3)(17)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	14324	1

Signal:

RAM_MEMORY(3)(16)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	14311	1

Signal:

RAM_MEMORY(3)(15)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	14345	1

Signal:

RAM_MEMORY(3)(14)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	14379	1

Signal:

RAM_MEMORY(3)(13)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	14372	1

Signal:

RAM_MEMORY(3)(12)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	14349	1

Signal:

RAM_MEMORY(3)(11)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	14377	1

Signal:

RAM_MEMORY(3)(10)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	14402	1

Signal:

RAM_MEMORY(3)(9)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	14378	1

Signal:

RAM_MEMORY(3)(8)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	14376	1

Signal:

RAM_MEMORY(3)(7)

	From	To	Count	Threshold
Bin	0	1	226	1
Bin	1	0	14364	1

Signal:

RAM_MEMORY(3)(6)

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	14312	1

Signal:

RAM_MEMORY(3)(5)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	14301	1

Signal:

RAM_MEMORY(3)(4)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	14320	1

Signal:

RAM_MEMORY(3)(3)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	14331	1

Signal:

RAM_MEMORY(3)(2)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	14298	1

Signal:

RAM_MEMORY(3)(1)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	14335	1

Signal:

RAM_MEMORY(3)(0)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	14327	1

Signal:

RAM_MEMORY(4)(31)

	From	To	Count	Threshold
Bin	0	1	779	1
Bin	1	0	12193	1

Signal:

RAM_MEMORY(4)(30)

	From	To	Count	Threshold
Bin	0	1	720	1
Bin	1	0	12154	1

Signal:

RAM_MEMORY(4)(29)

	From	To	Count	Threshold
Bin	0	1	759	1
Bin	1	0	12207	1

Signal:

RAM_MEMORY(4)(28)

	From	To	Count	Threshold
Bin	0	1	718	1
Bin	1	0	12128	1

Signal:

RAM_MEMORY(4)(27)

	From	To	Count	Threshold
Bin	0	1	712	1
Bin	1	0	11951	1

Signal:

RAM_MEMORY(4)(26)

	From	To	Count	Threshold
Bin	0	1	704	1
Bin	1	0	12125	1

Signal:

RAM_MEMORY(4)(25)

	From	To	Count	Threshold
Bin	0	1	845	1
Bin	1	0	12240	1

Signal:

RAM_MEMORY(4)(24)

	From	To	Count	Threshold
Bin	0	1	751	1
Bin	1	0	12187	1

Signal:

RAM_MEMORY(4)(23)

	From	To	Count	Threshold
Bin	0	1	757	1
Bin	1	0	12144	1

Signal:

RAM_MEMORY(4)(22)

	From	To	Count	Threshold
Bin	0	1	670	1
Bin	1	0	12048	1

Signal:

RAM_MEMORY(4)(21)

	From	To	Count	Threshold
Bin	0	1	758	1
Bin	1	0	12054	1

Signal:

RAM_MEMORY(4)(20)

	From	To	Count	Threshold
Bin	0	1	779	1
Bin	1	0	12070	1

Signal:

RAM_MEMORY(4)(19)

	From	To	Count	Threshold
Bin	0	1	765	1
Bin	1	0	12028	1

Signal:

RAM_MEMORY(4)(18)

	From	To	Count	Threshold
Bin	0	1	652	1
Bin	1	0	11991	1

Signal:

RAM_MEMORY(4)(17)

	From	To	Count	Threshold
Bin	0	1	836	1
Bin	1	0	12120	1

Signal:

RAM_MEMORY(4)(16)

	From	To	Count	Threshold
Bin	0	1	722	1
Bin	1	0	11982	1

Signal:

RAM_MEMORY(4)(15)

	From	To	Count	Threshold
Bin	0	1	780	1
Bin	1	0	11917	1

Signal:

RAM_MEMORY(4)(14)

	From	To	Count	Threshold
Bin	0	1	819	1
Bin	1	0	11928	1

Signal:

RAM_MEMORY(4)(13)

	From	To	Count	Threshold
Bin	0	1	898	1
Bin	1	0	11989	1

Signal:

RAM_MEMORY(4)(12)

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	11926	1

Signal:

RAM_MEMORY(4)(11)

	From	To	Count	Threshold
Bin	0	1	786	1
Bin	1	0	11809	1

Signal:

RAM_MEMORY(4)(10)

	From	To	Count	Threshold
Bin	0	1	779	1
Bin	1	0	11863	1

Signal:

RAM_MEMORY(4)(9)

	From	To	Count	Threshold
Bin	0	1	775	1
Bin	1	0	11987	1

Signal:

RAM_MEMORY(4)(8)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	11937	1

Signal:

RAM_MEMORY(4)(7)

	From	To	Count	Threshold
Bin	0	1	887	1
Bin	1	0	11920	1

Signal:

RAM_MEMORY(4)(6)

	From	To	Count	Threshold
Bin	0	1	832	1
Bin	1	0	11827	1

Signal:

RAM_MEMORY(4)(5)

	From	To	Count	Threshold
Bin	0	1	906	1
Bin	1	0	11832	1

Signal:

RAM_MEMORY(4)(4)

	From	To	Count	Threshold
Bin	0	1	737	1
Bin	1	0	11847	1

Signal:

RAM_MEMORY(4)(3)

	From	To	Count	Threshold
Bin	0	1	855	1
Bin	1	0	11787	1

Signal:

RAM_MEMORY(4)(2)

	From	To	Count	Threshold
Bin	0	1	752	1
Bin	1	0	11728	1

Signal:

RAM_MEMORY(4)(1)

	From	To	Count	Threshold
Bin	0	1	877	1
Bin	1	0	11896	1

Signal:

RAM_MEMORY(4)(0)

	From	To	Count	Threshold
Bin	0	1	856	1
Bin	1	0	11890	1

Signal:

RAM_MEMORY(5)(31)

	From	To	Count	Threshold
Bin	0	1	619	1
Bin	1	0	12166	1

Signal:

RAM_MEMORY(5)(30)

	From	To	Count	Threshold
Bin	0	1	506	1
Bin	1	0	12279	1

Signal:

RAM_MEMORY(5)(29)

	From	To	Count	Threshold
Bin	0	1	532	1
Bin	1	0	11931	1

Signal:

RAM_MEMORY(5)(28)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	12197	1

Signal:

RAM_MEMORY(5)(27)

	From	To	Count	Threshold
Bin	0	1	644	1
Bin	1	0	12173	1

Signal:

RAM_MEMORY(5)(26)

	From	To	Count	Threshold
Bin	0	1	579	1
Bin	1	0	12294	1

Signal:

RAM_MEMORY(5)(25)

	From	To	Count	Threshold
Bin	0	1	575	1
Bin	1	0	12163	1

Signal:

RAM_MEMORY(5)(24)

	From	To	Count	Threshold
Bin	0	1	520	1
Bin	1	0	12033	1

Signal:

RAM_MEMORY(5)(23)

	From	To	Count	Threshold
Bin	0	1	657	1
Bin	1	0	11838	1

Signal:

RAM_MEMORY(5)(22)

	From	To	Count	Threshold
Bin	0	1	639	1
Bin	1	0	11981	1

Signal:

RAM_MEMORY(5)(21)

	From	To	Count	Threshold
Bin	0	1	623	1
Bin	1	0	11826	1

Signal:

RAM_MEMORY(5)(20)

	From	To	Count	Threshold
Bin	0	1	533	1
Bin	1	0	11988	1

Signal:

RAM_MEMORY(5)(19)

	From	To	Count	Threshold
Bin	0	1	579	1
Bin	1	0	11945	1

Signal:

RAM_MEMORY(5)(18)

	From	To	Count	Threshold
Bin	0	1	531	1
Bin	1	0	11870	1

Signal:

RAM_MEMORY(5)(17)

	From	To	Count	Threshold
Bin	0	1	680	1
Bin	1	0	11857	1

Signal:

RAM_MEMORY(5)(16)

	From	To	Count	Threshold
Bin	0	1	587	1
Bin	1	0	11965	1

Signal:

RAM_MEMORY(5)(15)

	From	To	Count	Threshold
Bin	0	1	786	1
Bin	1	0	11858	1

Signal:

RAM_MEMORY(5)(14)

	From	To	Count	Threshold
Bin	0	1	536	1
Bin	1	0	11611	1

Signal:

RAM_MEMORY(5)(13)

	From	To	Count	Threshold
Bin	0	1	710	1
Bin	1	0	11820	1

Signal:

RAM_MEMORY(5)(12)

	From	To	Count	Threshold
Bin	0	1	658	1
Bin	1	0	11843	1

Signal:

RAM_MEMORY(5)(11)

	From	To	Count	Threshold
Bin	0	1	751	1
Bin	1	0	11857	1

Signal:

RAM_MEMORY(5)(10)

	From	To	Count	Threshold
Bin	0	1	525	1
Bin	1	0	11823	1

Signal:

RAM_MEMORY(5)(9)

	From	To	Count	Threshold
Bin	0	1	720	1
Bin	1	0	11989	1

Signal:

RAM_MEMORY(5)(8)

	From	To	Count	Threshold
Bin	0	1	566	1
Bin	1	0	11790	1

Signal:

RAM_MEMORY(5)(7)

	From	To	Count	Threshold
Bin	0	1	618	1
Bin	1	0	11518	1

Signal:

RAM_MEMORY(5)(6)

	From	To	Count	Threshold
Bin	0	1	636	1
Bin	1	0	11679	1

Signal:

RAM_MEMORY(5)(5)

	From	To	Count	Threshold
Bin	0	1	738	1
Bin	1	0	11523	1

Signal:

RAM_MEMORY(5)(4)

	From	To	Count	Threshold
Bin	0	1	637	1
Bin	1	0	11700	1

Signal:

RAM_MEMORY(5)(3)

	From	To	Count	Threshold
Bin	0	1	733	1
Bin	1	0	11620	1

Signal:

RAM_MEMORY(5)(2)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	11595	1

Signal:

RAM_MEMORY(5)(1)

	From	To	Count	Threshold
Bin	0	1	777	1
Bin	1	0	11709	1

Signal:

RAM_MEMORY(5)(0)

	From	To	Count	Threshold
Bin	0	1	663	1
Bin	1	0	11742	1

Signal:

RAM_MEMORY(6)(31)

	From	To	Count	Threshold
Bin	0	1	623	1
Bin	1	0	11778	1

Signal:

RAM_MEMORY(6)(30)

	From	To	Count	Threshold
Bin	0	1	472	1
Bin	1	0	11768	1

Signal:

RAM_MEMORY(6)(29)

	From	To	Count	Threshold
Bin	0	1	572	1
Bin	1	0	11673	1

Signal:

RAM_MEMORY(6)(28)

	From	To	Count	Threshold
Bin	0	1	413	1
Bin	1	0	11655	1

Signal:

RAM_MEMORY(6)(27)

	From	To	Count	Threshold
Bin	0	1	618	1
Bin	1	0	11774	1

Signal:

RAM_MEMORY(6)(26)

	From	To	Count	Threshold
Bin	0	1	480	1
Bin	1	0	11607	1

Signal:

RAM_MEMORY(6)(25)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	11654	1

Signal:

RAM_MEMORY(6)(24)

	From	To	Count	Threshold
Bin	0	1	458	1
Bin	1	0	11536	1

Signal:

RAM_MEMORY(6)(23)

	From	To	Count	Threshold
Bin	0	1	481	1
Bin	1	0	11737	1

Signal:

RAM_MEMORY(6)(22)

	From	To	Count	Threshold
Bin	0	1	382	1
Bin	1	0	11628	1

Signal:

RAM_MEMORY(6)(21)

	From	To	Count	Threshold
Bin	0	1	554	1
Bin	1	0	11681	1

Signal:

RAM_MEMORY(6)(20)

	From	To	Count	Threshold
Bin	0	1	507	1
Bin	1	0	11687	1

Signal:

RAM_MEMORY(6)(19)

	From	To	Count	Threshold
Bin	0	1	503	1
Bin	1	0	11734	1

Signal:

RAM_MEMORY(6)(18)

	From	To	Count	Threshold
Bin	0	1	461	1
Bin	1	0	11580	1

Signal:

RAM_MEMORY(6)(17)

	From	To	Count	Threshold
Bin	0	1	529	1
Bin	1	0	11755	1

Signal:

RAM_MEMORY(6)(16)

	From	To	Count	Threshold
Bin	0	1	474	1
Bin	1	0	11716	1

Signal:

RAM_MEMORY(6)(15)

	From	To	Count	Threshold
Bin	0	1	582	1
Bin	1	0	11704	1

Signal:

RAM_MEMORY(6)(14)

	From	To	Count	Threshold
Bin	0	1	471	1
Bin	1	0	11717	1

Signal:

RAM_MEMORY(6)(13)

	From	To	Count	Threshold
Bin	0	1	503	1
Bin	1	0	11683	1

Signal:

RAM_MEMORY(6)(12)

	From	To	Count	Threshold
Bin	0	1	501	1
Bin	1	0	11579	1

Signal:

RAM_MEMORY(6)(11)

	From	To	Count	Threshold
Bin	0	1	485	1
Bin	1	0	11628	1

Signal:

RAM_MEMORY(6)(10)

	From	To	Count	Threshold
Bin	0	1	481	1
Bin	1	0	11708	1

Signal:

RAM_MEMORY(6)(9)

	From	To	Count	Threshold
Bin	0	1	578	1
Bin	1	0	11653	1

Signal:

RAM_MEMORY(6)(8)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	11606	1

Signal:

RAM_MEMORY(6)(7)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	11715	1

Signal:

RAM_MEMORY(6)(6)

	From	To	Count	Threshold
Bin	0	1	436	1
Bin	1	0	11740	1

Signal:

RAM_MEMORY(6)(5)

	From	To	Count	Threshold
Bin	0	1	610	1
Bin	1	0	11809	1

Signal:

RAM_MEMORY(6)(4)

	From	To	Count	Threshold
Bin	0	1	528	1
Bin	1	0	11704	1

Signal:

RAM_MEMORY(6)(3)

	From	To	Count	Threshold
Bin	0	1	531	1
Bin	1	0	11681	1

Signal:

RAM_MEMORY(6)(2)

	From	To	Count	Threshold
Bin	0	1	484	1
Bin	1	0	11709	1

Signal:

RAM_MEMORY(6)(1)

	From	To	Count	Threshold
Bin	0	1	502	1
Bin	1	0	11610	1

Signal:

RAM_MEMORY(6)(0)

	From	To	Count	Threshold
Bin	0	1	486	1
Bin	1	0	11627	1

Signal:

RAM_MEMORY(7)(31)

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	11274	1

Signal:

RAM_MEMORY(7)(30)

	From	To	Count	Threshold
Bin	0	1	387	1
Bin	1	0	11253	1

Signal:

RAM_MEMORY(7)(29)

	From	To	Count	Threshold
Bin	0	1	532	1
Bin	1	0	11442	1

Signal:

RAM_MEMORY(7)(28)

	From	To	Count	Threshold
Bin	0	1	351	1
Bin	1	0	11258	1

Signal:

RAM_MEMORY(7)(27)

	From	To	Count	Threshold
Bin	0	1	467	1
Bin	1	0	11320	1

Signal:

RAM_MEMORY(7)(26)

	From	To	Count	Threshold
Bin	0	1	427	1
Bin	1	0	11384	1

Signal:

RAM_MEMORY(7)(25)

	From	To	Count	Threshold
Bin	0	1	511	1
Bin	1	0	11351	1

Signal:

RAM_MEMORY(7)(24)

	From	To	Count	Threshold
Bin	0	1	429	1
Bin	1	0	11362	1

Signal:

RAM_MEMORY(7)(23)

	From	To	Count	Threshold
Bin	0	1	479	1
Bin	1	0	11336	1

Signal:

RAM_MEMORY(7)(22)

	From	To	Count	Threshold
Bin	0	1	420	1
Bin	1	0	11261	1

Signal:

RAM_MEMORY(7)(21)

	From	To	Count	Threshold
Bin	0	1	457	1
Bin	1	0	11342	1

Signal:

RAM_MEMORY(7)(20)

	From	To	Count	Threshold
Bin	0	1	373	1
Bin	1	0	11279	1

Signal:

RAM_MEMORY(7)(19)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	11328	1

Signal:

RAM_MEMORY(7)(18)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	11287	1

Signal:

RAM_MEMORY(7)(17)

	From	To	Count	Threshold
Bin	0	1	469	1
Bin	1	0	11364	1

Signal:

RAM_MEMORY(7)(16)

	From	To	Count	Threshold
Bin	0	1	439	1
Bin	1	0	11280	1

Signal:

RAM_MEMORY(7)(15)

	From	To	Count	Threshold
Bin	0	1	439	1
Bin	1	0	11435	1

Signal:

RAM_MEMORY(7)(14)

	From	To	Count	Threshold
Bin	0	1	383	1
Bin	1	0	11321	1

Signal:

RAM_MEMORY(7)(13)

	From	To	Count	Threshold
Bin	0	1	416	1
Bin	1	0	11291	1

Signal:

RAM_MEMORY(7)(12)

	From	To	Count	Threshold
Bin	0	1	396	1
Bin	1	0	11338	1

Signal:

RAM_MEMORY(7)(11)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	11359	1

Signal:

RAM_MEMORY(7)(10)

	From	To	Count	Threshold
Bin	0	1	387	1
Bin	1	0	11269	1

Signal:

RAM_MEMORY(7)(9)

	From	To	Count	Threshold
Bin	0	1	490	1
Bin	1	0	11318	1

Signal:

RAM_MEMORY(7)(8)

	From	To	Count	Threshold
Bin	0	1	350	1
Bin	1	0	11206	1

Signal:

RAM_MEMORY(7)(7)

	From	To	Count	Threshold
Bin	0	1	478	1
Bin	1	0	11388	1

Signal:

RAM_MEMORY(7)(6)

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	11323	1

Signal:

RAM_MEMORY(7)(5)

	From	To	Count	Threshold
Bin	0	1	451	1
Bin	1	0	11327	1

Signal:

RAM_MEMORY(7)(4)

	From	To	Count	Threshold
Bin	0	1	373	1
Bin	1	0	11405	1

Signal:

RAM_MEMORY(7)(3)

	From	To	Count	Threshold
Bin	0	1	540	1
Bin	1	0	11384	1

Signal:

RAM_MEMORY(7)(2)

	From	To	Count	Threshold
Bin	0	1	375	1
Bin	1	0	11310	1

Signal:

RAM_MEMORY(7)(1)

	From	To	Count	Threshold
Bin	0	1	408	1
Bin	1	0	11348	1

Signal:

RAM_MEMORY(7)(0)

	From	To	Count	Threshold
Bin	0	1	478	1
Bin	1	0	11364	1

Signal:

RAM_MEMORY(8)(31)

	From	To	Count	Threshold
Bin	0	1	327	1
Bin	1	0	10673	1

Signal:

RAM_MEMORY(8)(30)

	From	To	Count	Threshold
Bin	0	1	380	1
Bin	1	0	10840	1

Signal:

RAM_MEMORY(8)(29)

	From	To	Count	Threshold
Bin	0	1	431	1
Bin	1	0	10893	1

Signal:

RAM_MEMORY(8)(28)

	From	To	Count	Threshold
Bin	0	1	347	1
Bin	1	0	10788	1

Signal:

RAM_MEMORY(8)(27)

	From	To	Count	Threshold
Bin	0	1	368	1
Bin	1	0	10604	1

Signal:

RAM_MEMORY(8)(26)

	From	To	Count	Threshold
Bin	0	1	369	1
Bin	1	0	10855	1

Signal:

RAM_MEMORY(8)(25)

	From	To	Count	Threshold
Bin	0	1	393	1
Bin	1	0	10843	1

Signal:

RAM_MEMORY(8)(24)

	From	To	Count	Threshold
Bin	0	1	426	1
Bin	1	0	10821	1

Signal:

RAM_MEMORY(8)(23)

	From	To	Count	Threshold
Bin	0	1	373	1
Bin	1	0	10757	1

Signal:

RAM_MEMORY(8)(22)

	From	To	Count	Threshold
Bin	0	1	283	1
Bin	1	0	10872	1

Signal:

RAM_MEMORY(8)(21)

	From	To	Count	Threshold
Bin	0	1	372	1
Bin	1	0	10815	1

Signal:

RAM_MEMORY(8)(20)

	From	To	Count	Threshold
Bin	0	1	352	1
Bin	1	0	10713	1

Signal:

RAM_MEMORY(8)(19)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	10754	1

Signal:

RAM_MEMORY(8)(18)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	10776	1

Signal:

RAM_MEMORY(8)(17)

	From	To	Count	Threshold
Bin	0	1	430	1
Bin	1	0	10757	1

Signal:

RAM_MEMORY(8)(16)

	From	To	Count	Threshold
Bin	0	1	320	1
Bin	1	0	10830	1

Signal:

RAM_MEMORY(8)(15)

	From	To	Count	Threshold
Bin	0	1	486	1
Bin	1	0	10821	1

Signal:

RAM_MEMORY(8)(14)

	From	To	Count	Threshold
Bin	0	1	338	1
Bin	1	0	10820	1

Signal:

RAM_MEMORY(8)(13)

	From	To	Count	Threshold
Bin	0	1	445	1
Bin	1	0	10921	1

Signal:

RAM_MEMORY(8)(12)

	From	To	Count	Threshold
Bin	0	1	398	1
Bin	1	0	10821	1

Signal:

RAM_MEMORY(8)(11)

	From	To	Count	Threshold
Bin	0	1	454	1
Bin	1	0	10719	1

Signal:

RAM_MEMORY(8)(10)

	From	To	Count	Threshold
Bin	0	1	404	1
Bin	1	0	10681	1

Signal:

RAM_MEMORY(8)(9)

	From	To	Count	Threshold
Bin	0	1	409	1
Bin	1	0	10653	1

Signal:

RAM_MEMORY(8)(8)

	From	To	Count	Threshold
Bin	0	1	440	1
Bin	1	0	10846	1

Signal:

RAM_MEMORY(8)(7)

	From	To	Count	Threshold
Bin	0	1	414	1
Bin	1	0	10783	1

Signal:

RAM_MEMORY(8)(6)

	From	To	Count	Threshold
Bin	0	1	329	1
Bin	1	0	10786	1

Signal:

RAM_MEMORY(8)(5)

	From	To	Count	Threshold
Bin	0	1	457	1
Bin	1	0	10812	1

Signal:

RAM_MEMORY(8)(4)

	From	To	Count	Threshold
Bin	0	1	369	1
Bin	1	0	10873	1

Signal:

RAM_MEMORY(8)(3)

	From	To	Count	Threshold
Bin	0	1	455	1
Bin	1	0	10766	1

Signal:

RAM_MEMORY(8)(2)

	From	To	Count	Threshold
Bin	0	1	400	1
Bin	1	0	10853	1

Signal:

RAM_MEMORY(8)(1)

	From	To	Count	Threshold
Bin	0	1	357	1
Bin	1	0	10750	1

Signal:

RAM_MEMORY(8)(0)

	From	To	Count	Threshold
Bin	0	1	321	1
Bin	1	0	10827	1

Signal:

RAM_MEMORY(9)(31)

	From	To	Count	Threshold
Bin	0	1	395	1
Bin	1	0	10325	1

Signal:

RAM_MEMORY(9)(30)

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	10226	1

Signal:

RAM_MEMORY(9)(29)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	10267	1

Signal:

RAM_MEMORY(9)(28)

	From	To	Count	Threshold
Bin	0	1	321	1
Bin	1	0	10201	1

Signal:

RAM_MEMORY(9)(27)

	From	To	Count	Threshold
Bin	0	1	399	1
Bin	1	0	10228	1

Signal:

RAM_MEMORY(9)(26)

	From	To	Count	Threshold
Bin	0	1	417	1
Bin	1	0	10342	1

Signal:

RAM_MEMORY(9)(25)

	From	To	Count	Threshold
Bin	0	1	376	1
Bin	1	0	10230	1

Signal:

RAM_MEMORY(9)(24)

	From	To	Count	Threshold
Bin	0	1	403	1
Bin	1	0	10255	1

Signal:

RAM_MEMORY(9)(23)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	10264	1

Signal:

RAM_MEMORY(9)(22)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	10149	1

Signal:

RAM_MEMORY(9)(21)

	From	To	Count	Threshold
Bin	0	1	379	1
Bin	1	0	10229	1

Signal:

RAM_MEMORY(9)(20)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	10256	1

Signal:

RAM_MEMORY(9)(19)

	From	To	Count	Threshold
Bin	0	1	414	1
Bin	1	0	10209	1

Signal:

RAM_MEMORY(9)(18)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	10175	1

Signal:

RAM_MEMORY(9)(17)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	10144	1

Signal:

RAM_MEMORY(9)(16)

	From	To	Count	Threshold
Bin	0	1	322	1
Bin	1	0	10304	1

Signal:

RAM_MEMORY(9)(15)

	From	To	Count	Threshold
Bin	0	1	460	1
Bin	1	0	10201	1

Signal:

RAM_MEMORY(9)(14)

	From	To	Count	Threshold
Bin	0	1	381	1
Bin	1	0	10343	1

Signal:

RAM_MEMORY(9)(13)

	From	To	Count	Threshold
Bin	0	1	420	1
Bin	1	0	10257	1

Signal:

RAM_MEMORY(9)(12)

	From	To	Count	Threshold
Bin	0	1	331	1
Bin	1	0	10289	1

Signal:

RAM_MEMORY(9)(11)

	From	To	Count	Threshold
Bin	0	1	399	1
Bin	1	0	10255	1

Signal:

RAM_MEMORY(9)(10)

	From	To	Count	Threshold
Bin	0	1	408	1
Bin	1	0	10269	1

Signal:

RAM_MEMORY(9)(9)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	10229	1

Signal:

RAM_MEMORY(9)(8)

	From	To	Count	Threshold
Bin	0	1	386	1
Bin	1	0	10231	1

Signal:

RAM_MEMORY(9)(7)

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	10324	1

Signal:

RAM_MEMORY(9)(6)

	From	To	Count	Threshold
Bin	0	1	307	1
Bin	1	0	10338	1

Signal:

RAM_MEMORY(9)(5)

	From	To	Count	Threshold
Bin	0	1	466	1
Bin	1	0	10211	1

Signal:

RAM_MEMORY(9)(4)

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	10273	1

Signal:

RAM_MEMORY(9)(3)

	From	To	Count	Threshold
Bin	0	1	413	1
Bin	1	0	10222	1

Signal:

RAM_MEMORY(9)(2)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	10147	1

Signal:

RAM_MEMORY(9)(1)

	From	To	Count	Threshold
Bin	0	1	389	1
Bin	1	0	10239	1

Signal:

RAM_MEMORY(9)(0)

	From	To	Count	Threshold
Bin	0	1	372	1
Bin	1	0	10149	1

Signal:

RAM_MEMORY(10)(31)

	From	To	Count	Threshold
Bin	0	1	289	1
Bin	1	0	9738	1

Signal:

RAM_MEMORY(10)(30)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	9851	1

Signal:

RAM_MEMORY(10)(29)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	9766	1

Signal:

RAM_MEMORY(10)(28)

	From	To	Count	Threshold
Bin	0	1	317	1
Bin	1	0	9862	1

Signal:

RAM_MEMORY(10)(27)

	From	To	Count	Threshold
Bin	0	1	334	1
Bin	1	0	9813	1

Signal:

RAM_MEMORY(10)(26)

	From	To	Count	Threshold
Bin	0	1	258	1
Bin	1	0	9813	1

Signal:

RAM_MEMORY(10)(25)

	From	To	Count	Threshold
Bin	0	1	335	1
Bin	1	0	9851	1

Signal:

RAM_MEMORY(10)(24)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	9718	1

Signal:

RAM_MEMORY(10)(23)

	From	To	Count	Threshold
Bin	0	1	393	1
Bin	1	0	9758	1

Signal:

RAM_MEMORY(10)(22)

	From	To	Count	Threshold
Bin	0	1	383	1
Bin	1	0	9839	1

Signal:

RAM_MEMORY(10)(21)

	From	To	Count	Threshold
Bin	0	1	355	1
Bin	1	0	9833	1

Signal:

RAM_MEMORY(10)(20)

	From	To	Count	Threshold
Bin	0	1	288	1
Bin	1	0	9754	1

Signal:

RAM_MEMORY(10)(19)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	9813	1

Signal:

RAM_MEMORY(10)(18)

	From	To	Count	Threshold
Bin	0	1	357	1
Bin	1	0	9802	1

Signal:

RAM_MEMORY(10)(17)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	9700	1

Signal:

RAM_MEMORY(10)(16)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	9700	1

Signal:

RAM_MEMORY(10)(15)

	From	To	Count	Threshold
Bin	0	1	327	1
Bin	1	0	9819	1

Signal:

RAM_MEMORY(10)(14)

	From	To	Count	Threshold
Bin	0	1	337	1
Bin	1	0	9765	1

Signal:

RAM_MEMORY(10)(13)

	From	To	Count	Threshold
Bin	0	1	300	1
Bin	1	0	9861	1

Signal:

RAM_MEMORY(10)(12)

	From	To	Count	Threshold
Bin	0	1	302	1
Bin	1	0	9718	1

Signal:

RAM_MEMORY(10)(11)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	9700	1

Signal:

RAM_MEMORY(10)(10)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	9839	1

Signal:

RAM_MEMORY(10)(9)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	9728	1

Signal:

RAM_MEMORY(10)(8)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	9768	1

Signal:

RAM_MEMORY(10)(7)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	9748	1

Signal:

RAM_MEMORY(10)(6)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	9786	1

Signal:

RAM_MEMORY(10)(5)

	From	To	Count	Threshold
Bin	0	1	373	1
Bin	1	0	9765	1

Signal:

RAM_MEMORY(10)(4)

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	9819	1

Signal:

RAM_MEMORY(10)(3)

	From	To	Count	Threshold
Bin	0	1	393	1
Bin	1	0	9754	1

Signal:

RAM_MEMORY(10)(2)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	9813	1

Signal:

RAM_MEMORY(10)(1)

	From	To	Count	Threshold
Bin	0	1	435	1
Bin	1	0	9748	1

Signal:

RAM_MEMORY(10)(0)

	From	To	Count	Threshold
Bin	0	1	347	1
Bin	1	0	9755	1

Signal:

RAM_MEMORY(11)(31)

	From	To	Count	Threshold
Bin	0	1	362	1
Bin	1	0	9152	1

Signal:

RAM_MEMORY(11)(30)

	From	To	Count	Threshold
Bin	0	1	388	1
Bin	1	0	9226	1

Signal:

RAM_MEMORY(11)(29)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	9217	1

Signal:

RAM_MEMORY(11)(28)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	9087	1

Signal:

RAM_MEMORY(11)(27)

	From	To	Count	Threshold
Bin	0	1	379	1
Bin	1	0	9143	1

Signal:

RAM_MEMORY(11)(26)

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	9163	1

Signal:

RAM_MEMORY(11)(25)

	From	To	Count	Threshold
Bin	0	1	415	1
Bin	1	0	9208	1

Signal:

RAM_MEMORY(11)(24)

	From	To	Count	Threshold
Bin	0	1	302	1
Bin	1	0	9163	1

Signal:

RAM_MEMORY(11)(23)

	From	To	Count	Threshold
Bin	0	1	402	1
Bin	1	0	9170	1

Signal:

RAM_MEMORY(11)(22)

	From	To	Count	Threshold
Bin	0	1	376	1
Bin	1	0	9231	1

Signal:

RAM_MEMORY(11)(21)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	9235	1

Signal:

RAM_MEMORY(11)(20)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	9208	1

Signal:

RAM_MEMORY(11)(19)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	9172	1

Signal:

RAM_MEMORY(11)(18)

	From	To	Count	Threshold
Bin	0	1	295	1
Bin	1	0	9148	1

Signal:

RAM_MEMORY(11)(17)

	From	To	Count	Threshold
Bin	0	1	299	1
Bin	1	0	9181	1

Signal:

RAM_MEMORY(11)(16)

	From	To	Count	Threshold
Bin	0	1	393	1
Bin	1	0	9204	1

Signal:

RAM_MEMORY(11)(15)

	From	To	Count	Threshold
Bin	0	1	372	1
Bin	1	0	9152	1

Signal:

RAM_MEMORY(11)(14)

	From	To	Count	Threshold
Bin	0	1	341	1
Bin	1	0	9217	1

Signal:

RAM_MEMORY(11)(13)

	From	To	Count	Threshold
Bin	0	1	294	1
Bin	1	0	9152	1

Signal:

RAM_MEMORY(11)(12)

	From	To	Count	Threshold
Bin	0	1	303	1
Bin	1	0	9251	1

Signal:

RAM_MEMORY(11)(11)

	From	To	Count	Threshold
Bin	0	1	300	1
Bin	1	0	9143	1

Signal:

RAM_MEMORY(11)(10)

	From	To	Count	Threshold
Bin	0	1	290	1
Bin	1	0	9204	1

Signal:

RAM_MEMORY(11)(9)

	From	To	Count	Threshold
Bin	0	1	366	1
Bin	1	0	9161	1

Signal:

RAM_MEMORY(11)(8)

	From	To	Count	Threshold
Bin	0	1	366	1
Bin	1	0	9278	1

Signal:

RAM_MEMORY(11)(7)

	From	To	Count	Threshold
Bin	0	1	423	1
Bin	1	0	9226	1

Signal:

RAM_MEMORY(11)(6)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	9208	1

Signal:

RAM_MEMORY(11)(5)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	9161	1

Signal:

RAM_MEMORY(11)(4)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	9170	1

Signal:

RAM_MEMORY(11)(3)

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	9251	1

Signal:

RAM_MEMORY(11)(2)

	From	To	Count	Threshold
Bin	0	1	300	1
Bin	1	0	9199	1

Signal:

RAM_MEMORY(11)(1)

	From	To	Count	Threshold
Bin	0	1	343	1
Bin	1	0	9175	1

Signal:

RAM_MEMORY(11)(0)

	From	To	Count	Threshold
Bin	0	1	317	1
Bin	1	0	9217	1

Signal:

RAM_MEMORY(12)(31)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	8692	1

Signal:

RAM_MEMORY(12)(30)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	8773	1

Signal:

RAM_MEMORY(12)(29)

	From	To	Count	Threshold
Bin	0	1	341	1
Bin	1	0	8781	1

Signal:

RAM_MEMORY(12)(28)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	8773	1

Signal:

RAM_MEMORY(12)(27)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	8684	1

Signal:

RAM_MEMORY(12)(26)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	8684	1

Signal:

RAM_MEMORY(12)(25)

	From	To	Count	Threshold
Bin	0	1	281	1
Bin	1	0	8700	1

Signal:

RAM_MEMORY(12)(24)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	8692	1

Signal:

RAM_MEMORY(12)(23)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	8757	1

Signal:

RAM_MEMORY(12)(22)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	8700	1

Signal:

RAM_MEMORY(12)(21)

	From	To	Count	Threshold
Bin	0	1	313	1
Bin	1	0	8708	1

Signal:

RAM_MEMORY(12)(20)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	8781	1

Signal:

RAM_MEMORY(12)(19)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	8765	1

Signal:

RAM_MEMORY(12)(18)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	8700	1

Signal:

RAM_MEMORY(12)(17)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	8765	1

Signal:

RAM_MEMORY(12)(16)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	8700	1

Signal:

RAM_MEMORY(12)(15)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	8795	1

Signal:

RAM_MEMORY(12)(14)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	8722	1

Signal:

RAM_MEMORY(12)(13)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	8722	1

Signal:

RAM_MEMORY(12)(12)

	From	To	Count	Threshold
Bin	0	1	242	1
Bin	1	0	8730	1

Signal:

RAM_MEMORY(12)(11)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	8730	1

Signal:

RAM_MEMORY(12)(10)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	8730	1

Signal:

RAM_MEMORY(12)(9)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	8730	1

Signal:

RAM_MEMORY(12)(8)

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	8730	1

Signal:

RAM_MEMORY(12)(7)

	From	To	Count	Threshold
Bin	0	1	313	1
Bin	1	0	8781	1

Signal:

RAM_MEMORY(12)(6)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	8700	1

Signal:

RAM_MEMORY(12)(5)

	From	To	Count	Threshold
Bin	0	1	299	1
Bin	1	0	8765	1

Signal:

RAM_MEMORY(12)(4)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	8773	1

Signal:

RAM_MEMORY(12)(3)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	8692	1

Signal:

RAM_MEMORY(12)(2)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	8708	1

Signal:

RAM_MEMORY(12)(1)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	8700	1

Signal:

RAM_MEMORY(12)(0)

	From	To	Count	Threshold
Bin	0	1	262	1
Bin	1	0	8781	1

Signal:

RAM_MEMORY(13)(31)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	8156	1

Signal:

RAM_MEMORY(13)(30)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	8163	1

Signal:

RAM_MEMORY(13)(29)

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	8156	1

Signal:

RAM_MEMORY(13)(28)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	8098	1

Signal:

RAM_MEMORY(13)(27)

	From	To	Count	Threshold
Bin	0	1	281	1
Bin	1	0	8156	1

Signal:

RAM_MEMORY(13)(26)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	8163	1

Signal:

RAM_MEMORY(13)(25)

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(24)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	8084	1

Signal:

RAM_MEMORY(13)(23)

	From	To	Count	Threshold
Bin	0	1	323	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(22)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(21)

	From	To	Count	Threshold
Bin	0	1	312	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(20)

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	8098	1

Signal:

RAM_MEMORY(13)(19)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	8091	1

Signal:

RAM_MEMORY(13)(18)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(17)

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(16)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	8163	1

Signal:

RAM_MEMORY(13)(15)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	8091	1

Signal:

RAM_MEMORY(13)(14)

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	8091	1

Signal:

RAM_MEMORY(13)(13)

	From	To	Count	Threshold
Bin	0	1	272	1
Bin	1	0	8098	1

Signal:

RAM_MEMORY(13)(12)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	8098	1

Signal:

RAM_MEMORY(13)(11)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	8091	1

Signal:

RAM_MEMORY(13)(10)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	8163	1

Signal:

RAM_MEMORY(13)(9)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	8163	1

Signal:

RAM_MEMORY(13)(8)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	8156	1

Signal:

RAM_MEMORY(13)(7)

	From	To	Count	Threshold
Bin	0	1	196	1
Bin	1	0	8077	1

Signal:

RAM_MEMORY(13)(6)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	8163	1

Signal:

RAM_MEMORY(13)(5)

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	8177	1

Signal:

RAM_MEMORY(13)(4)

	From	To	Count	Threshold
Bin	0	1	295	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(3)

	From	To	Count	Threshold
Bin	0	1	289	1
Bin	1	0	8170	1

Signal:

RAM_MEMORY(13)(2)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	8156	1

Signal:

RAM_MEMORY(13)(1)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	8149	1

Signal:

RAM_MEMORY(13)(0)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	8084	1

Signal:

RAM_MEMORY(14)(31)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(30)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	7470	1

Signal:

RAM_MEMORY(14)(29)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	7553	1

Signal:

RAM_MEMORY(14)(28)

	From	To	Count	Threshold
Bin	0	1	286	1
Bin	1	0	7559	1

Signal:

RAM_MEMORY(14)(27)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	7559	1

Signal:

RAM_MEMORY(14)(26)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	7559	1

Signal:

RAM_MEMORY(14)(25)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	7547	1

Signal:

RAM_MEMORY(14)(24)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	7547	1

Signal:

RAM_MEMORY(14)(23)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	7488	1

Signal:

RAM_MEMORY(14)(22)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(21)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	7541	1

Signal:

RAM_MEMORY(14)(20)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(19)

	From	To	Count	Threshold
Bin	0	1	272	1
Bin	1	0	7553	1

Signal:

RAM_MEMORY(14)(18)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	7553	1

Signal:

RAM_MEMORY(14)(17)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	7559	1

Signal:

RAM_MEMORY(14)(16)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	7482	1

Signal:

RAM_MEMORY(14)(15)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(14)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	7488	1

Signal:

RAM_MEMORY(14)(13)

	From	To	Count	Threshold
Bin	0	1	283	1
Bin	1	0	7547	1

Signal:

RAM_MEMORY(14)(12)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	7488	1

Signal:

RAM_MEMORY(14)(11)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	7553	1

Signal:

RAM_MEMORY(14)(10)

	From	To	Count	Threshold
Bin	0	1	209	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(9)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	7470	1

Signal:

RAM_MEMORY(14)(8)

	From	To	Count	Threshold
Bin	0	1	177	1
Bin	1	0	7470	1

Signal:

RAM_MEMORY(14)(7)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	7553	1

Signal:

RAM_MEMORY(14)(6)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	7565	1

Signal:

RAM_MEMORY(14)(5)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(4)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	7541	1

Signal:

RAM_MEMORY(14)(3)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	7476	1

Signal:

RAM_MEMORY(14)(2)

	From	To	Count	Threshold
Bin	0	1	250	1
Bin	1	0	7547	1

Signal:

RAM_MEMORY(14)(1)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	7488	1

Signal:

RAM_MEMORY(14)(0)

	From	To	Count	Threshold
Bin	0	1	251	1
Bin	1	0	7553	1

Signal:

RAM_MEMORY(15)(31)

	From	To	Count	Threshold
Bin	0	1	242	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(30)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(29)

	From	To	Count	Threshold
Bin	0	1	290	1
Bin	1	0	6948	1

Signal:

RAM_MEMORY(15)(28)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(27)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(26)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(25)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	6943	1

Signal:

RAM_MEMORY(15)(24)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(23)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	6943	1

Signal:

RAM_MEMORY(15)(22)

	From	To	Count	Threshold
Bin	0	1	189	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(21)

	From	To	Count	Threshold
Bin	0	1	297	1
Bin	1	0	6953	1

Signal:

RAM_MEMORY(15)(20)

	From	To	Count	Threshold
Bin	0	1	232	1
Bin	1	0	6943	1

Signal:

RAM_MEMORY(15)(19)

	From	To	Count	Threshold
Bin	0	1	298	1
Bin	1	0	6948	1

Signal:

RAM_MEMORY(15)(18)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	6878	1

Signal:

RAM_MEMORY(15)(17)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	6938	1

Signal:

RAM_MEMORY(15)(16)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(15)

	From	To	Count	Threshold
Bin	0	1	209	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(14)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	6938	1

Signal:

RAM_MEMORY(15)(13)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	6933	1

Signal:

RAM_MEMORY(15)(12)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(11)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	6943	1

Signal:

RAM_MEMORY(15)(10)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(9)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(8)

	From	To	Count	Threshold
Bin	0	1	230	1
Bin	1	0	6938	1

Signal:

RAM_MEMORY(15)(7)

	From	To	Count	Threshold
Bin	0	1	292	1
Bin	1	0	6878	1

Signal:

RAM_MEMORY(15)(6)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(5)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	6868	1

Signal:

RAM_MEMORY(15)(4)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	6873	1

Signal:

RAM_MEMORY(15)(3)

	From	To	Count	Threshold
Bin	0	1	309	1
Bin	1	0	6948	1

Signal:

RAM_MEMORY(15)(2)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	6883	1

Signal:

RAM_MEMORY(15)(1)

	From	To	Count	Threshold
Bin	0	1	297	1
Bin	1	0	6953	1

Signal:

RAM_MEMORY(15)(0)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	6878	1

Signal:

RAM_MEMORY(16)(31)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(30)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(29)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(28)

	From	To	Count	Threshold
Bin	0	1	189	1
Bin	1	0	6356	1

Signal:

RAM_MEMORY(16)(27)

	From	To	Count	Threshold
Bin	0	1	194	1
Bin	1	0	6352	1

Signal:

RAM_MEMORY(16)(26)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(25)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(24)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(23)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(22)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	6356	1

Signal:

RAM_MEMORY(16)(21)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(20)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	6356	1

Signal:

RAM_MEMORY(16)(19)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	6356	1

Signal:

RAM_MEMORY(16)(18)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(17)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(16)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(15)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(14)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	6368	1

Signal:

RAM_MEMORY(16)(13)

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(12)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(11)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(10)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(9)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(8)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(16)(7)

	From	To	Count	Threshold
Bin	0	1	212	1
Bin	1	0	6352	1

Signal:

RAM_MEMORY(16)(6)

	From	To	Count	Threshold
Bin	0	1	175	1
Bin	1	0	6352	1

Signal:

RAM_MEMORY(16)(5)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(4)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	6356	1

Signal:

RAM_MEMORY(16)(3)

	From	To	Count	Threshold
Bin	0	1	212	1
Bin	1	0	6356	1

Signal:

RAM_MEMORY(16)(2)

	From	To	Count	Threshold
Bin	0	1	203	1
Bin	1	0	6352	1

Signal:

RAM_MEMORY(16)(1)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	6364	1

Signal:

RAM_MEMORY(16)(0)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	6360	1

Signal:

RAM_MEMORY(17)(31)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(30)

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	5746	1

Signal:

RAM_MEMORY(17)(29)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(28)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(27)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(26)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(25)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(24)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(23)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	5755	1

Signal:

RAM_MEMORY(17)(22)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	5746	1

Signal:

RAM_MEMORY(17)(21)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	5746	1

Signal:

RAM_MEMORY(17)(20)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(19)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(18)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	5746	1

Signal:

RAM_MEMORY(17)(17)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(16)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(15)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(14)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(13)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(12)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(11)

	From	To	Count	Threshold
Bin	0	1	222	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(10)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(9)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(8)

	From	To	Count	Threshold
Bin	0	1	191	1
Bin	1	0	5743	1

Signal:

RAM_MEMORY(17)(7)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(6)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(5)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	5755	1

Signal:

RAM_MEMORY(17)(4)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(3)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	5749	1

Signal:

RAM_MEMORY(17)(2)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	5746	1

Signal:

RAM_MEMORY(17)(1)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(17)(0)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	5752	1

Signal:

RAM_MEMORY(18)(31)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(30)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	5136	1

Signal:

RAM_MEMORY(18)(29)

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	5136	1

Signal:

RAM_MEMORY(18)(28)

	From	To	Count	Threshold
Bin	0	1	226	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(27)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(26)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(25)

	From	To	Count	Threshold
Bin	0	1	226	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(24)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	5142	1

Signal:

RAM_MEMORY(18)(23)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	5136	1

Signal:

RAM_MEMORY(18)(22)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(21)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(20)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	5136	1

Signal:

RAM_MEMORY(18)(19)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(18)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(17)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	5136	1

Signal:

RAM_MEMORY(18)(16)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(15)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	5134	1

Signal:

RAM_MEMORY(18)(14)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(13)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(12)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(11)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(10)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(9)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	5136	1

Signal:

RAM_MEMORY(18)(8)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(7)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	5142	1

Signal:

RAM_MEMORY(18)(6)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(5)

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	5142	1

Signal:

RAM_MEMORY(18)(4)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	5142	1

Signal:

RAM_MEMORY(18)(3)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(2)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(18)(1)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	5140	1

Signal:

RAM_MEMORY(18)(0)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	5138	1

Signal:

RAM_MEMORY(19)(31)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(30)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(29)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(28)

	From	To	Count	Threshold
Bin	0	1	232	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(27)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(26)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(25)

	From	To	Count	Threshold
Bin	0	1	278	1
Bin	1	0	4529	1

Signal:

RAM_MEMORY(19)(24)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(23)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(22)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	4529	1

Signal:

RAM_MEMORY(19)(21)

	From	To	Count	Threshold
Bin	0	1	250	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(20)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	4529	1

Signal:

RAM_MEMORY(19)(19)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(18)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(17)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(16)

	From	To	Count	Threshold
Bin	0	1	196	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(15)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(14)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(13)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(12)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(11)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(10)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(9)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	4525	1

Signal:

RAM_MEMORY(19)(8)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	4528	1

Signal:

RAM_MEMORY(19)(7)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(19)(6)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(5)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(4)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(3)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(2)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	4529	1

Signal:

RAM_MEMORY(19)(1)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	4526	1

Signal:

RAM_MEMORY(19)(0)

	From	To	Count	Threshold
Bin	0	1	232	1
Bin	1	0	4527	1

Signal:

RAM_MEMORY(20)(31)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	4107	1

Signal:

RAM_MEMORY(20)(30)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	3943	1

Signal:

RAM_MEMORY(20)(29)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3985	1

Signal:

RAM_MEMORY(20)(28)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3964	1

Signal:

RAM_MEMORY(20)(27)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3985	1

Signal:

RAM_MEMORY(20)(26)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	4006	1

Signal:

RAM_MEMORY(20)(25)

	From	To	Count	Threshold
Bin	0	1	370	1
Bin	1	0	4107	1

Signal:

RAM_MEMORY(20)(24)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	3943	1

Signal:

RAM_MEMORY(20)(23)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	4107	1

Signal:

RAM_MEMORY(20)(22)

	From	To	Count	Threshold
Bin	0	1	185	1
Bin	1	0	3943	1

Signal:

RAM_MEMORY(20)(21)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3985	1

Signal:

RAM_MEMORY(20)(20)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3985	1

Signal:

RAM_MEMORY(20)(19)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	4006	1

Signal:

RAM_MEMORY(20)(18)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3985	1

Signal:

RAM_MEMORY(20)(17)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	4107	1

Signal:

RAM_MEMORY(20)(16)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3943	1

Signal:

RAM_MEMORY(20)(15)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	3433	1

Signal:

RAM_MEMORY(20)(14)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3269	1

Signal:

RAM_MEMORY(20)(13)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3311	1

Signal:

RAM_MEMORY(20)(12)

	From	To	Count	Threshold
Bin	0	1	343	1
Bin	1	0	3323	1

Signal:

RAM_MEMORY(20)(11)

	From	To	Count	Threshold
Bin	0	1	431	1
Bin	1	0	3439	1

Signal:

RAM_MEMORY(20)(10)

	From	To	Count	Threshold
Bin	0	1	436	1
Bin	1	0	3441	1

Signal:

RAM_MEMORY(20)(9)

	From	To	Count	Threshold
Bin	0	1	483	1
Bin	1	0	3585	1

Signal:

RAM_MEMORY(20)(8)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	3509	1

Signal:

RAM_MEMORY(20)(7)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	3424	1

Signal:

RAM_MEMORY(20)(6)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	3260	1

Signal:

RAM_MEMORY(20)(5)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3344	1

Signal:

RAM_MEMORY(20)(4)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3323	1

Signal:

RAM_MEMORY(20)(3)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3281	1

Signal:

RAM_MEMORY(20)(2)

	From	To	Count	Threshold
Bin	0	1	492	1
Bin	1	0	3479	1

Signal:

RAM_MEMORY(20)(1)

	From	To	Count	Threshold
Bin	0	1	473	1
Bin	1	0	3453	1

Signal:

RAM_MEMORY(20)(0)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	3413	1

Signal:

INT_READ_DATA(31)

	From	To	Count	Threshold
Bin	0	1	809	1
Bin	1	0	1429	1

Signal:

INT_READ_DATA(30)

	From	To	Count	Threshold
Bin	0	1	830	1
Bin	1	0	1450	1

Signal:

INT_READ_DATA(29)

	From	To	Count	Threshold
Bin	0	1	898	1
Bin	1	0	1518	1

Signal:

INT_READ_DATA(28)

	From	To	Count	Threshold
Bin	0	1	3196	1
Bin	1	0	3816	1

Signal:

INT_READ_DATA(27)

	From	To	Count	Threshold
Bin	0	1	3165	1
Bin	1	0	3785	1

Signal:

INT_READ_DATA(26)

	From	To	Count	Threshold
Bin	0	1	3076	1
Bin	1	0	3696	1

Signal:

INT_READ_DATA(25)

	From	To	Count	Threshold
Bin	0	1	3135	1
Bin	1	0	3755	1

Signal:

INT_READ_DATA(24)

	From	To	Count	Threshold
Bin	0	1	2946	1
Bin	1	0	3566	1

Signal:

INT_READ_DATA(23)

	From	To	Count	Threshold
Bin	0	1	3526	1
Bin	1	0	4146	1

Signal:

INT_READ_DATA(22)

	From	To	Count	Threshold
Bin	0	1	3409	1
Bin	1	0	4029	1

Signal:

INT_READ_DATA(21)

	From	To	Count	Threshold
Bin	0	1	3751	1
Bin	1	0	4371	1

Signal:

INT_READ_DATA(20)

	From	To	Count	Threshold
Bin	0	1	3320	1
Bin	1	0	3938	1

Signal:

INT_READ_DATA(19)

	From	To	Count	Threshold
Bin	0	1	3147	1
Bin	1	0	3767	1

Signal:

INT_READ_DATA(18)

	From	To	Count	Threshold
Bin	0	1	3366	1
Bin	1	0	3986	1

Signal:

INT_READ_DATA(17)

	From	To	Count	Threshold
Bin	0	1	1817	1
Bin	1	0	2437	1

Signal:

INT_READ_DATA(16)

	From	To	Count	Threshold
Bin	0	1	1960	1
Bin	1	0	2580	1

Signal:

INT_READ_DATA(15)

	From	To	Count	Threshold
Bin	0	1	1895	1
Bin	1	0	2515	1

Signal:

INT_READ_DATA(14)

	From	To	Count	Threshold
Bin	0	1	1970	1
Bin	1	0	2590	1

Signal:

INT_READ_DATA(13)

	From	To	Count	Threshold
Bin	0	1	1882	1
Bin	1	0	2501	1

Signal:

INT_READ_DATA(12)

	From	To	Count	Threshold
Bin	0	1	2074	1
Bin	1	0	2694	1

Signal:

INT_READ_DATA(11)

	From	To	Count	Threshold
Bin	0	1	2070	1
Bin	1	0	2690	1

Signal:

INT_READ_DATA(10)

	From	To	Count	Threshold
Bin	0	1	2051	1
Bin	1	0	2671	1

Signal:

INT_READ_DATA(9)

	From	To	Count	Threshold
Bin	0	1	3086	1
Bin	1	0	3706	1

Signal:

INT_READ_DATA(8)

	From	To	Count	Threshold
Bin	0	1	1972	1
Bin	1	0	2592	1

Signal:

INT_READ_DATA(7)

	From	To	Count	Threshold
Bin	0	1	3687	1
Bin	1	0	4307	1

Signal:

INT_READ_DATA(6)

	From	To	Count	Threshold
Bin	0	1	2722	1
Bin	1	0	3341	1

Signal:

INT_READ_DATA(5)

	From	To	Count	Threshold
Bin	0	1	2976	1
Bin	1	0	3595	1

Signal:

INT_READ_DATA(4)

	From	To	Count	Threshold
Bin	0	1	2120	1
Bin	1	0	2739	1

Signal:

INT_READ_DATA(3)

	From	To	Count	Threshold
Bin	0	1	2213	1
Bin	1	0	2833	1

Signal:

INT_READ_DATA(2)

	From	To	Count	Threshold
Bin	0	1	2820	1
Bin	1	0	3440	1

Signal:

INT_READ_DATA(1)

	From	To	Count	Threshold
Bin	0	1	2577	1
Bin	1	0	3196	1

Signal:

INT_READ_DATA(0)

	From	To	Count	Threshold
Bin	0	1	3397	1
Bin	1	0	4017	1

Signal:

BYTE_WE(3)

	From	To	Count	Threshold
Bin	0	1	45992	1
Bin	1	0	46652	1

Signal:

BYTE_WE(2)

	From	To	Count	Threshold
Bin	0	1	45992	1
Bin	1	0	46652	1

Signal:

BYTE_WE(1)

	From	To	Count	Threshold
Bin	0	1	45992	1
Bin	1	0	46652	1

Signal:

BYTE_WE(0)

	From	To	Count	Threshold
Bin	0	1	45992	1
Bin	1	0	46652	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: