NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.PRIORITY_DECODER_INST

File:  /__w/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/priority_decoder.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average
L0_GEN(0) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(1) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(2) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(3) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(4) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(5) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(6) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
L0_GEN(7) N.A. N.A. N.A. N.A. N.A. N.A. N.A.
FILL_ZEROES_GEN 100.0 % (2/2) N.A. N.A. N.A. N.A. N.A. 100.0 % (2/2)

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.PRIORITY_DECODER_INST 100.0 % (64/64) 100.0 % (36/36) 100.0 % (194/194) 100.0 % (19/19) N.A. N.A. 100.0 % (313/313)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

202:        tmp := (others => (others => '0')); 
Count: 58806
Threshold: 1

Loop statement:

203:        for i in 0 to 3 loop 
204:            tmp(i) := l0_valid(2 * i + 1 downto 2 * i); 
...
231:            end case; 
232:        end loop; 
Count: 58806
Threshold: 1

Variable assignment statement:

204:            tmp(i) := l0_valid(2 * i + 1 downto 2 * i); 
Count: 235224
Threshold: 1

Sequential statement:

205:            case tmp(i) is 
206:            when "01" => 
...
230: 
231:            end case; 
Count: 235224
Threshold: 1

Signal assignment statement:

207:                l1_prio(i)      <= l0_prio(2 * i); 
Count: 15545
Threshold: 1

Signal assignment statement:

208:                l1_valid(i)     <= '1'; 
Count: 15545
Threshold: 1

Signal assignment statement:

209:                l1_winner(i)    <= LOWER_TREE; 
Count: 15545
Threshold: 1

Signal assignment statement:

212:                l1_prio(i)      <= l0_prio(2 * i + 1); 
Count: 10279
Threshold: 1

Signal assignment statement:

213:                l1_valid(i)     <= '1'; 
Count: 10279
Threshold: 1

Signal assignment statement:

214:                l1_winner(i)    <= UPPER_TREE; 
Count: 10279
Threshold: 1

If statement:

217:                if (unsigned(l0_prio(2 * i + 1)) > unsigned(l0_prio(2 * i))) then 
218:                    l1_prio(i)    <= l0_prio(2 * i + 1); 
...
222:                    l1_winner(i)  <= LOWER_TREE; 
223:                end if; 
Count: 1158
Threshold: 1

Signal assignment statement:

218:                    l1_prio(i)    <= l0_prio(2 * i + 1); 
Count: 140
Threshold: 1

Signal assignment statement:

219:                    l1_winner(i)  <= UPPER_TREE; 
Count: 140
Threshold: 1

Signal assignment statement:

221:                    l1_prio(i)    <= l0_prio(2 * i); 
Count: 1018
Threshold: 1

Signal assignment statement:

222:                    l1_winner(i)  <= LOWER_TREE; 
Count: 1018
Threshold: 1

Signal assignment statement:

224:                l1_valid(i)     <= '1'; 
Count: 1158
Threshold: 1

Signal assignment statement:

227:                l1_valid(i)     <= '0'; 
Count: 208242
Threshold: 1

Signal assignment statement:

228:                l1_prio(i)      <= l0_prio(2 * i + 1); 
Count: 208242
Threshold: 1

Signal assignment statement:

229:                l1_winner(i)    <= UPPER_TREE; 
Count: 208242
Threshold: 1

Variable assignment statement:

242:        tmp := (others => (others => '0')); 
Count: 57945
Threshold: 1

Loop statement:

243:        for i in 0 to 1 loop 
244:            tmp(i) := l1_valid(2 * i + 1 downto 2 * i); 
...
272:            end case; 
273:        end loop; 
Count: 57945
Threshold: 1

Variable assignment statement:

244:            tmp(i) := l1_valid(2 * i + 1 downto 2 * i); 
Count: 115890
Threshold: 1

Sequential statement:

246:            case tmp(i) is 
247:            when "01" => 
...
271: 
272:            end case; 
Count: 115890
Threshold: 1

Signal assignment statement:

248:                l2_prio(i)      <= l1_prio(2 * i); 
Count: 23313
Threshold: 1

Signal assignment statement:

249:                l2_valid(i)     <= '1'; 
Count: 23313
Threshold: 1

Signal assignment statement:

250:                l2_winner(i)    <= LOWER_TREE; 
Count: 23313
Threshold: 1

Signal assignment statement:

253:                l2_prio(i)      <= l1_prio(2 * i + 1); 
Count: 2407
Threshold: 1

Signal assignment statement:

254:                l2_valid(i)     <= '1'; 
Count: 2407
Threshold: 1

Signal assignment statement:

255:                l2_winner(i)    <= UPPER_TREE; 
Count: 2407
Threshold: 1

If statement:

258:                if (unsigned(l1_prio(2 * i + 1)) > unsigned(l1_prio(2 * i))) then 
259:                    l2_prio(i)    <= l1_prio(2 * i + 1); 
...
263:                    l2_winner(i)  <= LOWER_TREE; 
264:                end if; 
Count: 315
Threshold: 1

Signal assignment statement:

259:                    l2_prio(i)    <= l1_prio(2 * i + 1); 
Count: 100
Threshold: 1

Signal assignment statement:

260:                    l2_winner(i)  <= UPPER_TREE; 
Count: 100
Threshold: 1

Signal assignment statement:

262:                    l2_prio(i)    <= l1_prio(2 * i); 
Count: 215
Threshold: 1

Signal assignment statement:

263:                    l2_winner(i)  <= LOWER_TREE; 
Count: 215
Threshold: 1

Signal assignment statement:

265:                l2_valid(i)     <= '1'; 
Count: 315
Threshold: 1

Signal assignment statement:

268:                l2_valid(i)     <= '0'; 
Count: 89855
Threshold: 1

Signal assignment statement:

269:                l2_prio(i)      <= l1_prio(2 * i + 1); 
Count: 89855
Threshold: 1

Signal assignment statement:

270:                l2_winner(i)    <= UPPER_TREE; 
Count: 89855
Threshold: 1

If statement:

285:    l3_valid  <= '0' when l2_valid(1 downto 0) = "00" 
286:                     else 
287:                '1'; 
Count: 53106
Threshold: 1

Signal assignment statement:

285:    l3_valid  <= '0' when l2_valid(1 downto 0) = "00" 
Count: 26539
Threshold: 1

Signal assignment statement:

287:                '1'; 
Count: 26567
Threshold: 1

If statement:

288:    output_valid <= '1' when l3_valid = '1' else '0'; 
Count: 54678
Threshold: 1

Signal assignment statement:

288:    output_valid <= '1' when l3_valid = '1' else '0'; 
Count: 26539
Threshold: 1

Signal assignment statement:

288:    output_valid <= '1' when l3_valid = '1' else '0'; 
Count: 28139
Threshold: 1

If statement:

291:    l3_winner  <= LOWER_TREE when l2_valid(1 downto 0) = "01" else 
292:                  UPPER_TREE when l2_valid(1 downto 0) = "10" else 
293:                  UPPER_TREE when (l2_valid(1 downto 0) = "11" and 
294:                                 unsigned(l2_prio(1)) > unsigned(l2_prio(0))) 
295:                             else 
296:                  LOWER_TREE; 
Count: 56496
Threshold: 1

Signal assignment statement:

291:    l3_winner  <= LOWER_TREE when l2_valid(1 downto 0) = "01" else 
Count: 24888
Threshold: 1

Signal assignment statement:

292:                  UPPER_TREE when l2_valid(1 downto 0) = "10" else 
Count: 894
Threshold: 1

Signal assignment statement:

293:                  UPPER_TREE when (l2_valid(1 downto 0) = "11" and 
Count: 41
Threshold: 1

Signal assignment statement:

296:                  LOWER_TREE; 
Count: 30673
Threshold: 1

If statement:

310:        if (l3_winner = LOWER_TREE) then 
311:            if (l2_winner(0) = LOWER_TREE) then 
...
337:            end if; 
338:        end if; 
Count: 82268
Threshold: 1

If statement:

311:            if (l2_winner(0) = LOWER_TREE) then 
312:                if (l1_winner(0) = LOWER_TREE) then 
...
322:                end if; 
323:            end if; 
Count: 78766
Threshold: 1

If statement:

312:                if (l1_winner(0) = LOWER_TREE) then 
313:                    output_index <= 0; 
314:                else 
315:                    output_index <= 1; 
316:                end if; 
Count: 36877
Threshold: 1

Signal assignment statement:

313:                    output_index <= 0; 
Count: 14399
Threshold: 1

Signal assignment statement:

315:                    output_index <= 1; 
Count: 22478
Threshold: 1

If statement:

318:                if (l1_winner(1) = LOWER_TREE) then 
319:                    output_index <= 2 mod G_TXT_BUFFER_COUNT; 
320:                else 
321:                    output_index <= 3 mod G_TXT_BUFFER_COUNT; 
322:                end if; 
Count: 41889
Threshold: 1

Signal assignment statement:

319:                    output_index <= 2 mod G_TXT_BUFFER_COUNT; 
Count: 1135
Threshold: 1

Signal assignment statement:

321:                    output_index <= 3 mod G_TXT_BUFFER_COUNT; 
Count: 40754
Threshold: 1

If statement:

325:            if (l2_winner(1) = LOWER_TREE) then 
326:                if (l1_winner(2) = LOWER_TREE) then 
...
336:                end if; 
337:            end if; 
Count: 3502
Threshold: 1

If statement:

326:                if (l1_winner(2) = LOWER_TREE) then 
327:                    output_index <= 4 mod G_TXT_BUFFER_COUNT; 
328:                else 
329:                    output_index <= 5 mod G_TXT_BUFFER_COUNT; 
330:                end if; 
Count: 744
Threshold: 1

Signal assignment statement:

327:                    output_index <= 4 mod G_TXT_BUFFER_COUNT; 
Count: 263
Threshold: 1

Signal assignment statement:

329:                    output_index <= 5 mod G_TXT_BUFFER_COUNT; 
Count: 481
Threshold: 1

If statement:

332:                if (l1_winner(3) = LOWER_TREE) then 
333:                    output_index <= 6 mod G_TXT_BUFFER_COUNT; 
334:                else 
335:                    output_index <= 7 mod G_TXT_BUFFER_COUNT; 
336:                end if; 
Count: 2758
Threshold: 1

Signal assignment statement:

333:                    output_index <= 6 mod G_TXT_BUFFER_COUNT; 
Count: 249
Threshold: 1

Signal assignment statement:

335:                    output_index <= 7 mod G_TXT_BUFFER_COUNT; 
Count: 2509
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

206:            when "01" => 
Choice ofCountThreshold
Bin"01"155451

"case" / "with" / "select" choice:

211:            when "10" => 
Choice ofCountThreshold
Bin"10"102791

"case" / "with" / "select" choice:

216:            when "11" => 
Choice ofCountThreshold
Bin"11"11581

"if" / "when" / "else" condition:

217:                if (unsigned(l0_prio(2 * i + 1)) > unsigned(l0_prio(2 * i))) then 
Evaluated toCountThreshold
BinTrue1401
BinFalse10181

"case" / "with" / "select" choice:

226:            when others => 
Choice ofCountThreshold
Binothers2082421

"case" / "with" / "select" choice:

247:            when "01" => 
Choice ofCountThreshold
Bin"01"233131

"case" / "with" / "select" choice:

252:            when "10" => 
Choice ofCountThreshold
Bin"10"24071

"case" / "with" / "select" choice:

257:            when "11" => 
Choice ofCountThreshold
Bin"11"3151

"if" / "when" / "else" condition:

258:                if (unsigned(l1_prio(2 * i + 1)) > unsigned(l1_prio(2 * i))) then 
Evaluated toCountThreshold
BinTrue1001
BinFalse2151

"case" / "with" / "select" choice:

267:            when others => 
Choice ofCountThreshold
Binothers898551

"if" / "when" / "else" condition:

285:    l3_valid  <= '0' when l2_valid(1 downto 0) = "00" 
Evaluated toCountThreshold
BinTrue265391
BinFalse265671

"if" / "when" / "else" condition:

288:    output_valid <= '1' when l3_valid = '1' else '0'; 
Evaluated toCountThreshold
BinTrue265391
BinFalse281391

"if" / "when" / "else" condition:

291:    l3_winner  <= LOWER_TREE when l2_valid(1 downto 0) = "01" else 
Evaluated toCountThreshold
BinTrue248881
BinFalse316081

"if" / "when" / "else" condition:

292:                  UPPER_TREE when l2_valid(1 downto 0) = "10" else 
Evaluated toCountThreshold
BinTrue8941
BinFalse307141

"if" / "when" / "else" condition:

293:                  UPPER_TREE when (l2_valid(1 downto 0) = "11" and 
294:                                 unsigned(l2_prio(1)) > unsigned(l2_prio(0))) 
Evaluated toCountThreshold
BinTrue411
BinFalse306731

"if" / "when" / "else" condition:

310:        if (l3_winner = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue787661
BinFalse35021

"if" / "when" / "else" condition:

311:            if (l2_winner(0) = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue368771
BinFalse418891

"if" / "when" / "else" condition:

312:                if (l1_winner(0) = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue143991
BinFalse224781

"if" / "when" / "else" condition:

318:                if (l1_winner(1) = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue11351
BinFalse407541

"if" / "when" / "else" condition:

325:            if (l2_winner(1) = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue7441
BinFalse27581

"if" / "when" / "else" condition:

326:                if (l1_winner(2) = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue2631
BinFalse4811

"if" / "when" / "else" condition:

332:                if (l1_winner(3) = LOWER_TREE) then 
Evaluated toCountThreshold
BinTrue2491
BinFalse25091

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 PRIO(7)(2)
FromToCountThreshold
Bin01531
Bin103071

Port:

 PRIO(7)(1)
FromToCountThreshold
Bin01681
Bin103041

Port:

 PRIO(7)(0)
FromToCountThreshold
Bin01611
Bin103671

Port:

 PRIO(6)(2)
FromToCountThreshold
Bin01671
Bin103081

Port:

 PRIO(6)(1)
FromToCountThreshold
Bin01791
Bin103211

Port:

 PRIO(6)(0)
FromToCountThreshold
Bin01631
Bin103041

Port:

 PRIO(5)(2)
FromToCountThreshold
Bin01671
Bin102851

Port:

 PRIO(5)(1)
FromToCountThreshold
Bin01711
Bin103031

Port:

 PRIO(5)(0)
FromToCountThreshold
Bin01971
Bin103261

Port:

 PRIO(4)(2)
FromToCountThreshold
Bin01921
Bin103001

Port:

 PRIO(4)(1)
FromToCountThreshold
Bin01841
Bin102741

Port:

 PRIO(4)(0)
FromToCountThreshold
Bin011011
Bin103071

Port:

 PRIO(3)(2)
FromToCountThreshold
Bin011651
Bin109841

Port:

 PRIO(3)(1)
FromToCountThreshold
Bin011801
Bin1010371

Port:

 PRIO(3)(0)
FromToCountThreshold
Bin012291
Bin1010691

Port:

 PRIO(2)(2)
FromToCountThreshold
Bin011961
Bin109451

Port:

 PRIO(2)(1)
FromToCountThreshold
Bin011991
Bin1010081

Port:

 PRIO(2)(0)
FromToCountThreshold
Bin012821
Bin1010191

Port:

 PRIO(1)(2)
FromToCountThreshold
Bin012681
Bin1018681

Port:

 PRIO(1)(1)
FromToCountThreshold
Bin012571
Bin1019021

Port:

 PRIO(1)(0)
FromToCountThreshold
Bin013251
Bin1019271

Port:

 PRIO(0)(2)
FromToCountThreshold
Bin013331
Bin1018631

Port:

 PRIO(0)(1)
FromToCountThreshold
Bin013201
Bin1019621

Port:

 PRIO(0)(0)
FromToCountThreshold
Bin0119841
Bin103431

Port:

 PRIO_VALID(7)
FromToCountThreshold
Bin013291
Bin1063361

Port:

 PRIO_VALID(6)
FromToCountThreshold
Bin013021
Bin1063631

Port:

 PRIO_VALID(5)
FromToCountThreshold
Bin013431
Bin1063221

Port:

 PRIO_VALID(4)
FromToCountThreshold
Bin013041
Bin1063611

Port:

 PRIO_VALID(3)
FromToCountThreshold
Bin0112721
Bin10205351

Port:

 PRIO_VALID(2)
FromToCountThreshold
Bin0112241
Bin10205831

Port:

 PRIO_VALID(1)
FromToCountThreshold
Bin0194491
Bin10436101

Port:

 PRIO_VALID(0)
FromToCountThreshold
Bin01148291
Bin10382301

Port:

 OUTPUT_VALID
FromToCountThreshold
Bin01265391
Bin10281391

Signal:

 L0_PRIO(7)(2)
FromToCountThreshold
Bin01531
Bin1039071

Signal:

 L0_PRIO(7)(1)
FromToCountThreshold
Bin01681
Bin1039041

Signal:

 L0_PRIO(7)(0)
FromToCountThreshold
Bin01611
Bin1039671

Signal:

 L0_PRIO(6)(2)
FromToCountThreshold
Bin01671
Bin1039081

Signal:

 L0_PRIO(6)(1)
FromToCountThreshold
Bin01791
Bin1039211

Signal:

 L0_PRIO(6)(0)
FromToCountThreshold
Bin01631
Bin1039041

Signal:

 L0_PRIO(5)(2)
FromToCountThreshold
Bin01671
Bin1038851

Signal:

 L0_PRIO(5)(1)
FromToCountThreshold
Bin01711
Bin1039031

Signal:

 L0_PRIO(5)(0)
FromToCountThreshold
Bin01971
Bin1039261

Signal:

 L0_PRIO(4)(2)
FromToCountThreshold
Bin01921
Bin1039001

Signal:

 L0_PRIO(4)(1)
FromToCountThreshold
Bin01841
Bin1038741

Signal:

 L0_PRIO(4)(0)
FromToCountThreshold
Bin011011
Bin1039071

Signal:

 L0_PRIO(3)(2)
FromToCountThreshold
Bin011651
Bin1029741

Signal:

 L0_PRIO(3)(1)
FromToCountThreshold
Bin011801
Bin1030271

Signal:

 L0_PRIO(3)(0)
FromToCountThreshold
Bin012291
Bin1030591

Signal:

 L0_PRIO(2)(2)
FromToCountThreshold
Bin011961
Bin1029351

Signal:

 L0_PRIO(2)(1)
FromToCountThreshold
Bin011991
Bin1029981

Signal:

 L0_PRIO(2)(0)
FromToCountThreshold
Bin012821
Bin1030091

Signal:

 L0_PRIO(1)(2)
FromToCountThreshold
Bin012681
Bin1018681

Signal:

 L0_PRIO(1)(1)
FromToCountThreshold
Bin012571
Bin1019021

Signal:

 L0_PRIO(1)(0)
FromToCountThreshold
Bin013251
Bin1019271

Signal:

 L0_PRIO(0)(2)
FromToCountThreshold
Bin013331
Bin1018631

Signal:

 L0_PRIO(0)(1)
FromToCountThreshold
Bin013201
Bin1019621

Signal:

 L0_PRIO(0)(0)
FromToCountThreshold
Bin0119841
Bin103431

Signal:

 L0_VALID(7)
FromToCountThreshold
Bin013291
Bin10541651

Signal:

 L0_VALID(6)
FromToCountThreshold
Bin013021
Bin10541921

Signal:

 L0_VALID(5)
FromToCountThreshold
Bin013431
Bin10541511

Signal:

 L0_VALID(4)
FromToCountThreshold
Bin013041
Bin10541901

Signal:

 L0_VALID(3)
FromToCountThreshold
Bin0112721
Bin10527271

Signal:

 L0_VALID(2)
FromToCountThreshold
Bin0112241
Bin10527751

Signal:

 L0_VALID(1)
FromToCountThreshold
Bin0194491
Bin10436101

Signal:

 L0_VALID(0)
FromToCountThreshold
Bin01148291
Bin10382301

Signal:

 L1_PRIO(3)(2)
FromToCountThreshold
Bin01821
Bin10322351

Signal:

 L1_PRIO(3)(1)
FromToCountThreshold
Bin01911
Bin10322511

Signal:

 L1_PRIO(3)(0)
FromToCountThreshold
Bin011041
Bin10322791

Signal:

 L1_PRIO(2)(2)
FromToCountThreshold
Bin01931
Bin10322201

Signal:

 L1_PRIO(2)(1)
FromToCountThreshold
Bin01951
Bin10322251

Signal:

 L1_PRIO(2)(0)
FromToCountThreshold
Bin011111
Bin10322631

Signal:

 L1_PRIO(1)(2)
FromToCountThreshold
Bin012021
Bin10310931

Signal:

 L1_PRIO(1)(1)
FromToCountThreshold
Bin012671
Bin10312141

Signal:

 L1_PRIO(1)(0)
FromToCountThreshold
Bin013281
Bin10312531

Signal:

 L1_PRIO(0)(2)
FromToCountThreshold
Bin015501
Bin1021101

Signal:

 L1_PRIO(0)(1)
FromToCountThreshold
Bin017081
Bin1022761

Signal:

 L1_PRIO(0)(0)
FromToCountThreshold
Bin01142511
Bin10158191

Signal:

 L1_VALID(3)
FromToCountThreshold
Bin014921
Bin10511411

Signal:

 L1_VALID(2)
FromToCountThreshold
Bin014991
Bin10511341

Signal:

 L1_VALID(1)
FromToCountThreshold
Bin0120481
Bin10495851

Signal:

 L1_VALID(0)
FromToCountThreshold
Bin01222591
Bin10293741

Signal:

 L1_WINNER(3)
FromToCountThreshold
Bin01331721
Bin102861

Signal:

 L1_WINNER(2)
FromToCountThreshold
Bin01331691
Bin102891

Signal:

 L1_WINNER(1)
FromToCountThreshold
Bin01323071
Bin1011511

Signal:

 L1_WINNER(0)
FromToCountThreshold
Bin01190161
Bin10144421

Signal:

 L2_PRIO(1)(2)
FromToCountThreshold
Bin01901
Bin10317311

Signal:

 L2_PRIO(1)(1)
FromToCountThreshold
Bin01841
Bin10317541

Signal:

 L2_PRIO(1)(0)
FromToCountThreshold
Bin011111
Bin10317861

Signal:

 L2_PRIO(0)(2)
FromToCountThreshold
Bin015141
Bin1021141

Signal:

 L2_PRIO(0)(1)
FromToCountThreshold
Bin018051
Bin1024061

Signal:

 L2_PRIO(0)(0)
FromToCountThreshold
Bin01145771
Bin10161521

Signal:

 L2_VALID(1)
FromToCountThreshold
Bin019171
Bin10505891

Signal:

 L2_VALID(0)
FromToCountThreshold
Bin01240801
Bin10274261

Signal:

 L2_WINNER(1)
FromToCountThreshold
Bin01464961
Bin104981

Signal:

 L2_WINNER(0)
FromToCountThreshold
Bin01247471
Bin10222471

Signal:

 L3_VALID
FromToCountThreshold
Bin01265391
Bin10265391

Signal:

 L3_WINNER
FromToCountThreshold
Bin019161
Bin1025161

Uncovered expressions:

Excluded expressions:

"and" expression

293:                  UPPER_TREE when (l2_valid(1 downto 0) = "11" and 
294:                                 unsigned(l2_prio(1)) > unsigned(l2_prio(0))) 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

Covered expressions:

"=" expression

288:    output_valid <= '1' when l3_valid = '1' else '0'; 
Evaluated toCountThreshold
BinFalse281391
BinTrue265391

"and" expression

293:                  UPPER_TREE when (l2_valid(1 downto 0) = "11" and 
294:                                 unsigned(l2_prio(1)) > unsigned(l2_prio(0))) 
LHSRHSCountThreshold
BinTrueFalse531
BinTrueTrue411

"=" expression

310:        if (l3_winner = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse35021
BinTrue787661

"=" expression

311:            if (l2_winner(0) = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse418891
BinTrue368771

"=" expression

312:                if (l1_winner(0) = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse224781
BinTrue143991

"=" expression

318:                if (l1_winner(1) = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse407541
BinTrue11351

"=" expression

325:            if (l2_winner(1) = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse27581
BinTrue7441

"=" expression

326:                if (l1_winner(2) = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse4811
BinTrue2631

"=" expression

332:                if (l1_winner(3) = LOWER_TREE) then 
Evaluated toCountThreshold
BinFalse25091
BinTrue2491

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: