NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_agent.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.G_EACH_BUF(0).TXT_BUF_EVEN_GEN.FUNC_COV_TXT_BUFFER_EVEN_INST	N.A.	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (16/16)	100.0 % (18/18)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.G_EACH_BUF(0).TXT_BUF_EVEN_GEN.FUNC_COV_TXT_BUFFER_EVEN_INST

N.A.

100.0 % (2/2)

N.A.

100.0 % (16/16)

100.0 % (18/18)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on line 148:

148: -- psl txtb_set_ready_cov : cover {mr_tx_command_txcr = '1' and mr_tx_command_txbi = '1'};
Count: 14079
Threshold: 1

PSL cover point on line 149:

149: -- psl txtb_set_empty_cov : cover {mr_tx_command_txce = '1' and mr_tx_command_txbi = '1'};
Count: 227
Threshold: 1

PSL cover point on line 150:

150: -- psl txtb_set_abort_cov : cover {mr_tx_command_txca = '1' and mr_tx_command_txbi = '1'};
Count: 1257
Threshold: 1

PSL cover point on line 156:

156: -- psl txtb_hw_lock : cover {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1'};
Count: 15623
Threshold: 1

PSL cover point on line 157:

157: -- psl txtb_hw_valid : cover {txtb_hw_cmd.valid = '1' and txtb_hw_cmd_cs = '1'};
Count: 6055
Threshold: 1

PSL cover point on line 158:

158:    -- psl txtb_hw_err      : cover {txtb_hw_cmd.err = '1'      and txtb_hw_cmd_cs = '1'};

Count: 2096
Threshold: 1

PSL cover point on line 159:

159: -- psl txtb_hw_arbl : cover {txtb_hw_cmd.arbl = '1' and txtb_hw_cmd_cs = '1'};
Count: 242
Threshold: 1

PSL cover point on line 160:

160: -- psl txtb_hw_failed : cover {txtb_hw_cmd.failed = '1' and txtb_hw_cmd_cs = '1'};
Count: 7225
Threshold: 1

PSL cover point on lines 166 to 167:

166:    -- psl txtb_perr_txt_ready_cov : cover 
167:    --      {curr_state = s_txt_ready and txtb_parity_error_valid = '1'};

Count: 161
Threshold: 1

PSL cover point on lines 169 to 170:

169:    -- psl txtb_perr_txt_tx_prog_cov : cover 
170:    --      {curr_state = s_txt_tx_prog and txtb_parity_error_valid = '1'};

Count: 84
Threshold: 1

PSL cover point on lines 172 to 173:

172:    -- psl txtb_perr_txt_ab_prog_cov : cover 
173:    --      {curr_state = s_txt_ab_prog and txtb_parity_error_valid = '1'};

Count: 30
Threshold: 1

PSL cover point on lines 179 to 181:

179:    -- psl txtb_hw_sw_cmd_txt_ready_hazard_cov : cover 
180:    --  {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1' and abort_applied = '1' and 
181:    --   curr_state = s_txt_ready};

Count: 13
Threshold: 1

PSL cover point on lines 183 to 186:

183:    -- psl txtb_hw_sw_cmd_txt_tx_prog_hazard_cov : cover 
184:    --  {((txtb_hw_cmd_i.valid = '1' or txtb_hw_cmd_i.err = '1' or 
185:    --     txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.failed = '1') and 
186:    --    abort_applied = '1' and curr_state = s_txt_tx_prog)};

Count: 11
Threshold: 1

PSL cover point on lines 192 to 193:

192:    -- psl txtb_ready_to_abt_in_progress_cov : cover 
193:    --  {curr_state = s_txt_ready and next_state = s_txt_ab_prog and txt_fsm_ce = '1'};