NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RST_SYNC_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_sync.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RST_SYNC_INST	100.0 % (5/5)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (19/19)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

104:        if (arst = G_RESET_POLARITY) then 
105:            rff <= G_RESET_POLARITY; 
...
109:            rst <= rff; 
110:        end if;

Count: 1055176879
Threshold: 1

Signal assignment statement:

105: rff <= G_RESET_POLARITY;
Count: 22278
Threshold: 1

Signal assignment statement:

106: rst <= G_RESET_POLARITY;
Count: 22278
Threshold: 1

Signal assignment statement:

108: rff <= not (G_RESET_POLARITY);
Count: 527571384
Threshold: 1

Signal assignment statement:

109: rst <= rff;
Count: 527571384
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

104: if (arst = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	22278	1
Bin	False	1055154601	1

"if" / "when" / "else" condition:

107: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	527571384	1
Bin	False	527583217	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

ARST

	From	To	Count	Threshold
Bin	0	1	8775	1
Bin	1	0	7175	1

Port:

RST

	From	To	Count	Threshold
Bin	0	1	7175	1
Bin	1	0	7175	1

Signal:

RFF

	From	To	Count	Threshold
Bin	0	1	8775	1
Bin	1	0	7175	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

104: if (arst = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	False	1055154601	1
Bin	True	22278	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RST_SYNC_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_sync.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: