Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| ADDR_DEC_GEN(0) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(1) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(2) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(3) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(4) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(5) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(6) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(7) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(8) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(9) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(10) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(11) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(12) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(13) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(14) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(15) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(16) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(17) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(18) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(19) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(20) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(21) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(22) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(23) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(24) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(25) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(26) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(27) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(28) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(29) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(30) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(31) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(32) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(33) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(34) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(35) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(36) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(37) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_GEN(38) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (5/5) |
| ADDR_DEC_REG_FALSE_GEN |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
154: (OTHERS => '0'); Count: 55592866
Threshold: 1
Signal assignment statement:
153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else Count: 19665575
Threshold: 1
Signal assignment statement:
154: (OTHERS => '0'); Count: 35927291
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 19665575 | 1 |
| Bin | False | 35927291 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31028760 | 1 |
| Bin | 1 | 0 | 31030360 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9642 | 1 |
| Bin | 1 | 0 | 8042 | 1 |
Port:
ADDRESS(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16744778 | 1 |
| Bin | 1 | 0 | 11049255 | 1 |
Port:
ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328560 | 1 |
| Bin | 1 | 0 | 27465473 | 1 |
Port:
ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576099 | 1 |
| Bin | 1 | 0 | 27217934 | 1 |
Port:
ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436079 | 1 |
| Bin | 1 | 0 | 27357954 | 1 |
Port:
ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27015237 | 1 |
| Bin | 1 | 0 | 778796 | 1 |
Port:
ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17655249 | 1 |
| Bin | 1 | 0 | 10138784 | 1 |
Port:
ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19665575 | 1 |
| Bin | 1 | 0 | 19667175 | 1 |
Port:
ADDR_DEC(38) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 5777977 | 1 |
Port:
ADDR_DEC(37) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 5774035 | 1 |
Port:
ADDR_DEC(36) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 5770325 | 1 |
Port:
ADDR_DEC(35) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10219898 | 1 |
| Bin | 1 | 0 | 28993992 | 1 |
Port:
ADDR_DEC(34) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 5853392 | 1 |
Port:
ADDR_DEC(33) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 5783472 | 1 |
Port:
ADDR_DEC(32) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3458 | 1 |
| Bin | 1 | 0 | 39329292 | 1 |
Port:
ADDR_DEC(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 537 | 1 |
| Bin | 1 | 0 | 39332213 | 1 |
Port:
ADDR_DEC(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4066 | 1 |
| Bin | 1 | 0 | 39328684 | 1 |
Port:
ADDR_DEC(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27527 | 1 |
| Bin | 1 | 0 | 39305223 | 1 |
Port:
ADDR_DEC(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8805 | 1 |
| Bin | 1 | 0 | 39323945 | 1 |
Port:
ADDR_DEC(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51733 | 1 |
| Bin | 1 | 0 | 39281017 | 1 |
Port:
ADDR_DEC(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13223 | 1 |
| Bin | 1 | 0 | 39319527 | 1 |
Port:
ADDR_DEC(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12418 | 1 |
| Bin | 1 | 0 | 39295496 | 1 |
Port:
ADDR_DEC(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12418 | 1 |
| Bin | 1 | 0 | 24036342 | 1 |
Port:
ADDR_DEC(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20068 | 1 |
| Bin | 1 | 0 | 39312682 | 1 |
Port:
ADDR_DEC(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 35485410 | 1 |
Port:
ADDR_DEC(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 35438380 | 1 |
Port:
ADDR_DEC(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 39270543 | 1 |
Port:
ADDR_DEC(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 35437941 | 1 |
Port:
ADDR_DEC(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 35442769 | 1 |
Port:
ADDR_DEC(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 35437941 | 1 |
Port:
ADDR_DEC(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4082 | 1 |
| Bin | 1 | 0 | 39327326 | 1 |
Port:
ADDR_DEC(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4082 | 1 |
| Bin | 1 | 0 | 39327322 | 1 |
Port:
ADDR_DEC(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 41481 | 1 |
| Bin | 1 | 0 | 39291269 | 1 |
Port:
ADDR_DEC(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2192 | 1 |
| Bin | 1 | 0 | 39268302 | 1 |
Port:
ADDR_DEC(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14068 | 1 |
| Bin | 1 | 0 | 37086924 | 1 |
Port:
ADDR_DEC(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111952 | 1 |
| Bin | 1 | 0 | 39220798 | 1 |
Port:
ADDR_DEC(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6713 | 1 |
| Bin | 1 | 0 | 39326037 | 1 |
Port:
ADDR_DEC(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6623 | 1 |
| Bin | 1 | 0 | 39326127 | 1 |
Port:
ADDR_DEC(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 485 | 1 |
| Bin | 1 | 0 | 39332265 | 1 |
Port:
ADDR_DEC(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 565 | 1 |
| Bin | 1 | 0 | 39332185 | 1 |
Port:
ADDR_DEC(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 552 | 1 |
| Bin | 1 | 0 | 39332198 | 1 |
Port:
ADDR_DEC(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 39332118 | 1 |
Port:
ADDR_DEC(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2154 | 1 |
| Bin | 1 | 0 | 39330596 | 1 |
Port:
ADDR_DEC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1480 | 1 |
| Bin | 1 | 0 | 39331270 | 1 |
Port:
ADDR_DEC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8997186 | 1 |
| Bin | 1 | 0 | 30335564 | 1 |
Port:
ADDR_DEC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75513 | 1 |
| Bin | 1 | 0 | 39257237 | 1 |
Port:
ADDR_DEC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 39332725 | 1 |
Signal:
ADDR_DEC_I(38) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 55587331 | 1 |
Signal:
ADDR_DEC_I(37) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 55587331 | 1 |
Signal:
ADDR_DEC_I(36) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 55591221 | 1 |
Signal:
ADDR_DEC_I(35) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16728663 | 1 |
| Bin | 1 | 0 | 38862603 | 1 |
Signal:
ADDR_DEC_I(34) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1134 | 1 |
| Bin | 1 | 0 | 55590132 | 1 |
Signal:
ADDR_DEC_I(33) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1134 | 1 |
| Bin | 1 | 0 | 55590132 | 1 |
Signal:
ADDR_DEC_I(32) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5932 | 1 |
| Bin | 1 | 0 | 55585334 | 1 |
Signal:
ADDR_DEC_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1782 | 1 |
| Bin | 1 | 0 | 55589484 | 1 |
Signal:
ADDR_DEC_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4066 | 1 |
| Bin | 1 | 0 | 55587200 | 1 |
Signal:
ADDR_DEC_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42600 | 1 |
| Bin | 1 | 0 | 55548666 | 1 |
Signal:
ADDR_DEC_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18065 | 1 |
| Bin | 1 | 0 | 55573201 | 1 |
Signal:
ADDR_DEC_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62940 | 1 |
| Bin | 1 | 0 | 55528326 | 1 |
Signal:
ADDR_DEC_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13425 | 1 |
| Bin | 1 | 0 | 55577841 | 1 |
Signal:
ADDR_DEC_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12620 | 1 |
| Bin | 1 | 0 | 55578646 | 1 |
Signal:
ADDR_DEC_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12620 | 1 |
| Bin | 1 | 0 | 55578646 | 1 |
Signal:
ADDR_DEC_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20068 | 1 |
| Bin | 1 | 0 | 55571198 | 1 |
Signal:
ADDR_DEC_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 55591196 | 1 |
Signal:
ADDR_DEC_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 55591196 | 1 |
Signal:
ADDR_DEC_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26811 | 1 |
| Bin | 1 | 0 | 55564455 | 1 |
Signal:
ADDR_DEC_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28044 | 1 |
| Bin | 1 | 0 | 55563222 | 1 |
Signal:
ADDR_DEC_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28044 | 1 |
| Bin | 1 | 0 | 55563222 | 1 |
Signal:
ADDR_DEC_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28044 | 1 |
| Bin | 1 | 0 | 55563222 | 1 |
Signal:
ADDR_DEC_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29291 | 1 |
| Bin | 1 | 0 | 55561975 | 1 |
Signal:
ADDR_DEC_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29597 | 1 |
| Bin | 1 | 0 | 55561669 | 1 |
Signal:
ADDR_DEC_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70084 | 1 |
| Bin | 1 | 0 | 55521182 | 1 |
Signal:
ADDR_DEC_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28507 | 1 |
| Bin | 1 | 0 | 55562759 | 1 |
Signal:
ADDR_DEC_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40383 | 1 |
| Bin | 1 | 0 | 55550883 | 1 |
Signal:
ADDR_DEC_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141758 | 1 |
| Bin | 1 | 0 | 55449508 | 1 |
Signal:
ADDR_DEC_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34994 | 1 |
| Bin | 1 | 0 | 55556272 | 1 |
Signal:
ADDR_DEC_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35465 | 1 |
| Bin | 1 | 0 | 55555801 | 1 |
Signal:
ADDR_DEC_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27193 | 1 |
| Bin | 1 | 0 | 55564073 | 1 |
Signal:
ADDR_DEC_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27620 | 1 |
| Bin | 1 | 0 | 55563646 | 1 |
Signal:
ADDR_DEC_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28099 | 1 |
| Bin | 1 | 0 | 55563167 | 1 |
Signal:
ADDR_DEC_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34321 | 1 |
| Bin | 1 | 0 | 55556945 | 1 |
Signal:
ADDR_DEC_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56021 | 1 |
| Bin | 1 | 0 | 55535245 | 1 |
Signal:
ADDR_DEC_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 149084 | 1 |
| Bin | 1 | 0 | 55442182 | 1 |
Signal:
ADDR_DEC_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9641830 | 1 |
| Bin | 1 | 0 | 45949436 | 1 |
Signal:
ADDR_DEC_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 278997 | 1 |
| Bin | 1 | 0 | 55312269 | 1 |
Signal:
ADDR_DEC_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98342 | 1 |
| Bin | 1 | 0 | 55492924 | 1 |
Signal:
ADDR_DEC_ENABLED_I(38) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 5535 | 1 |
Signal:
ADDR_DEC_ENABLED_I(37) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 5535 | 1 |
Signal:
ADDR_DEC_ENABLED_I(36) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
Signal:
ADDR_DEC_ENABLED_I(35) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10219898 | 1 |
| Bin | 1 | 0 | 10221498 | 1 |
Signal:
ADDR_DEC_ENABLED_I(34) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 2722 | 1 |
Signal:
ADDR_DEC_ENABLED_I(33) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 2722 | 1 |
Signal:
ADDR_DEC_ENABLED_I(32) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3458 | 1 |
| Bin | 1 | 0 | 5058 | 1 |
Signal:
ADDR_DEC_ENABLED_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 537 | 1 |
| Bin | 1 | 0 | 2137 | 1 |
Signal:
ADDR_DEC_ENABLED_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4066 | 1 |
| Bin | 1 | 0 | 5666 | 1 |
Signal:
ADDR_DEC_ENABLED_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27527 | 1 |
| Bin | 1 | 0 | 29127 | 1 |
Signal:
ADDR_DEC_ENABLED_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8805 | 1 |
| Bin | 1 | 0 | 10405 | 1 |
Signal:
ADDR_DEC_ENABLED_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51733 | 1 |
| Bin | 1 | 0 | 53333 | 1 |
Signal:
ADDR_DEC_ENABLED_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13223 | 1 |
| Bin | 1 | 0 | 14823 | 1 |
Signal:
ADDR_DEC_ENABLED_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12418 | 1 |
| Bin | 1 | 0 | 14018 | 1 |
Signal:
ADDR_DEC_ENABLED_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12418 | 1 |
| Bin | 1 | 0 | 14018 | 1 |
Signal:
ADDR_DEC_ENABLED_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20068 | 1 |
| Bin | 1 | 0 | 21668 | 1 |
Signal:
ADDR_DEC_ENABLED_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Signal:
ADDR_DEC_ENABLED_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Signal:
ADDR_DEC_ENABLED_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 4435 | 1 |
Signal:
ADDR_DEC_ENABLED_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 4435 | 1 |
Signal:
ADDR_DEC_ENABLED_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 4435 | 1 |
Signal:
ADDR_DEC_ENABLED_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 4435 | 1 |
Signal:
ADDR_DEC_ENABLED_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4082 | 1 |
| Bin | 1 | 0 | 5682 | 1 |
Signal:
ADDR_DEC_ENABLED_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4082 | 1 |
| Bin | 1 | 0 | 5682 | 1 |
Signal:
ADDR_DEC_ENABLED_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 41481 | 1 |
| Bin | 1 | 0 | 43081 | 1 |
Signal:
ADDR_DEC_ENABLED_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2192 | 1 |
| Bin | 1 | 0 | 3792 | 1 |
Signal:
ADDR_DEC_ENABLED_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14068 | 1 |
| Bin | 1 | 0 | 15668 | 1 |
Signal:
ADDR_DEC_ENABLED_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111952 | 1 |
| Bin | 1 | 0 | 113552 | 1 |
Signal:
ADDR_DEC_ENABLED_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6713 | 1 |
| Bin | 1 | 0 | 8313 | 1 |
Signal:
ADDR_DEC_ENABLED_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6623 | 1 |
| Bin | 1 | 0 | 8223 | 1 |
Signal:
ADDR_DEC_ENABLED_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 485 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Signal:
ADDR_DEC_ENABLED_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 565 | 1 |
| Bin | 1 | 0 | 2165 | 1 |
Signal:
ADDR_DEC_ENABLED_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 552 | 1 |
| Bin | 1 | 0 | 2152 | 1 |
Signal:
ADDR_DEC_ENABLED_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 2232 | 1 |
Signal:
ADDR_DEC_ENABLED_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2154 | 1 |
| Bin | 1 | 0 | 3754 | 1 |
Signal:
ADDR_DEC_ENABLED_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1480 | 1 |
| Bin | 1 | 0 | 3080 | 1 |
Signal:
ADDR_DEC_ENABLED_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8997186 | 1 |
| Bin | 1 | 0 | 8998786 | 1 |
Signal:
ADDR_DEC_ENABLED_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75513 | 1 |
| Bin | 1 | 0 | 77113 | 1 |
Signal:
ADDR_DEC_ENABLED_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
Covered expressions:
"=" expression
153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 35927291 | 1 |
| Bin | True | 19665575 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: