NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ADDR_DEC_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(4)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(5)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(6)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(7)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(8)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(9)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(10)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(11)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(12)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(13)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(14)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(15)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(16)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(17)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(18)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(19)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(20)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(21)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(22)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(23)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(24)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(25)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(26)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(27)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(28)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(29)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(30)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(31)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(32)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(33)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(34)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(35)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(36)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(37)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(38)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_REG_FALSE_GEN	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

ADDR_DEC_GEN(0)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(1)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(2)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(3)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(4)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(5)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(6)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(7)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(8)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(9)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(10)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(11)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(12)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(13)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(14)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(15)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(16)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(17)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(18)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(19)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(20)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(21)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(22)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(23)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(24)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(25)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(26)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(27)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(28)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(29)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(30)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(31)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(32)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(33)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(34)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(35)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(36)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(37)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(38)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_REG_FALSE_GEN

100.0 % (1/1)

N.A.

100.0 % (1/1)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (252/252)	100.0 % (2/2)	N.A.	N.A.	100.0 % (259/259)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (252/252)

100.0 % (2/2)

N.A.

100.0 % (259/259)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 153 to 154:

153:    addr_dec_enabled_i <= addr_dec_i when (enable = '1') else 
154:                          (OTHERS => '0');

Count: 55055827
Threshold: 1

Signal assignment statement on line 153:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
Count: 19215496
Threshold: 1

Signal assignment statement on line 154:

154: (OTHERS => '0');
Count: 35840331
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 153:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	19215496	1
Bin	False	35840331	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

ADDR_DEC

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	4326930	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	4322988	1
Bin	(36)	0	1	45	1
Bin	(36)	1	0	4319278	1
Bin	(35)	0	1	9995742	1
Bin	(35)	1	0	28318027	1
Bin	(34)	0	1	1122	1
Bin	(34)	1	0	4402309	1
Bin	(33)	0	1	1122	1
Bin	(33)	1	0	4332425	1
Bin	(32)	0	1	3459	1
Bin	(32)	1	0	38429134	1
Bin	(31)	0	1	537	1
Bin	(31)	1	0	38432056	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	38428527	1
Bin	(29)	0	1	27961	1
Bin	(29)	1	0	38404632	1
Bin	(28)	0	1	8416	1
Bin	(28)	1	0	38424177	1
Bin	(27)	0	1	51790	1
Bin	(27)	1	0	38380803	1
Bin	(26)	0	1	13208	1
Bin	(26)	1	0	38419385	1
Bin	(25)	0	1	12403	1
Bin	(25)	1	0	38395384	1
Bin	(24)	0	1	12403	1
Bin	(24)	1	0	23753874	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	38412525	1
Bin	(22)	0	1	70	1
Bin	(22)	1	0	34800289	1
Bin	(21)	0	1	70	1
Bin	(21)	1	0	34770917	1
Bin	(20)	0	1	2835	1
Bin	(20)	1	0	38388044	1
Bin	(19)	0	1	2835	1
Bin	(19)	1	0	34770478	1
Bin	(18)	0	1	2835	1
Bin	(18)	1	0	34775306	1
Bin	(17)	0	1	2835	1
Bin	(17)	1	0	34770478	1
Bin	(16)	0	1	4082	1
Bin	(16)	1	0	38427169	1
Bin	(15)	0	1	4082	1
Bin	(15)	1	0	38427165	1
Bin	(14)	0	1	43199	1
Bin	(14)	1	0	38389394	1
Bin	(13)	0	1	2192	1
Bin	(13)	1	0	38368451	1
Bin	(12)	0	1	14080	1
Bin	(12)	1	0	36193291	1
Bin	(11)	0	1	112340	1
Bin	(11)	1	0	38320253	1
Bin	(10)	0	1	6712	1
Bin	(10)	1	0	38425881	1
Bin	(9)	0	1	6622	1
Bin	(9)	1	0	38425971	1
Bin	(8)	0	1	485	1
Bin	(8)	1	0	38432108	1
Bin	(7)	0	1	565	1
Bin	(7)	1	0	38432028	1
Bin	(6)	0	1	552	1
Bin	(6)	1	0	38432041	1
Bin	(5)	0	1	632	1
Bin	(5)	1	0	38431961	1
Bin	(4)	0	1	2154	1
Bin	(4)	1	0	38430439	1
Bin	(3)	0	1	1477	1
Bin	(3)	1	0	38431116	1
Bin	(2)	0	1	8769066	1
Bin	(2)	1	0	29663527	1
Bin	(1)	0	1	75539	1
Bin	(1)	1	0	38357054	1
Bin	(0)	0	1	25	1
Bin	(0)	1	0	38432568	1

Signal:

ADDR_DEC_I

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	55050291	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	55050291	1
Bin	(36)	0	1	45	1
Bin	(36)	1	0	55054181	1
Bin	(35)	0	1	16656870	1
Bin	(35)	1	0	38397356	1
Bin	(34)	0	1	1134	1
Bin	(34)	1	0	55053092	1
Bin	(33)	0	1	1134	1
Bin	(33)	1	0	55053092	1
Bin	(32)	0	1	5933	1
Bin	(32)	1	0	55048293	1
Bin	(31)	0	1	1786	1
Bin	(31)	1	0	55052440	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	55050160	1
Bin	(29)	0	1	43035	1
Bin	(29)	1	0	55011191	1
Bin	(28)	0	1	17686	1
Bin	(28)	1	0	55036540	1
Bin	(27)	0	1	63161	1
Bin	(27)	1	0	54991065	1
Bin	(26)	0	1	13402	1
Bin	(26)	1	0	55040824	1
Bin	(25)	0	1	12597	1
Bin	(25)	1	0	55041629	1
Bin	(24)	0	1	12597	1
Bin	(24)	1	0	55041629	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	55034158	1
Bin	(22)	0	1	70	1
Bin	(22)	1	0	55054156	1
Bin	(21)	0	1	70	1
Bin	(21)	1	0	55054156	1
Bin	(20)	0	1	26817	1
Bin	(20)	1	0	55027409	1
Bin	(19)	0	1	28016	1
Bin	(19)	1	0	55026210	1
Bin	(18)	0	1	28016	1
Bin	(18)	1	0	55026210	1
Bin	(17)	0	1	28016	1
Bin	(17)	1	0	55026210	1
Bin	(16)	0	1	29263	1
Bin	(16)	1	0	55024963	1
Bin	(15)	0	1	30705	1
Bin	(15)	1	0	55023521	1
Bin	(14)	0	1	72910	1
Bin	(14)	1	0	54981316	1
Bin	(13)	0	1	29615	1
Bin	(13)	1	0	55024611	1
Bin	(12)	0	1	41503	1
Bin	(12)	1	0	55012723	1
Bin	(11)	0	1	143539	1
Bin	(11)	1	0	54910687	1
Bin	(10)	0	1	36386	1
Bin	(10)	1	0	55017840	1
Bin	(9)	0	1	36804	1
Bin	(9)	1	0	55017422	1
Bin	(8)	0	1	28415	1
Bin	(8)	1	0	55025811	1
Bin	(7)	0	1	28881	1
Bin	(7)	1	0	55025345	1
Bin	(6)	0	1	29482	1
Bin	(6)	1	0	55024744	1
Bin	(5)	0	1	34764	1
Bin	(5)	1	0	55019462	1
Bin	(4)	0	1	56477	1
Bin	(4)	1	0	54997749	1
Bin	(3)	0	1	149571	1
Bin	(3)	1	0	54904655	1
Bin	(2)	0	1	9428029	1
Bin	(2)	1	0	45626197	1
Bin	(1)	0	1	279547	1
Bin	(1)	1	0	54774679	1
Bin	(0)	0	1	98833	1
Bin	(0)	1	0	54955393	1

Signal:

ADDR_DEC_ENABLED_I

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	5536	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	5536	1
Bin	(36)	0	1	45	1
Bin	(36)	1	0	1646	1
Bin	(35)	0	1	9995742	1
Bin	(35)	1	0	9997343	1
Bin	(34)	0	1	1122	1
Bin	(34)	1	0	2723	1
Bin	(33)	0	1	1122	1
Bin	(33)	1	0	2723	1
Bin	(32)	0	1	3459	1
Bin	(32)	1	0	5060	1
Bin	(31)	0	1	537	1
Bin	(31)	1	0	2138	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	5667	1
Bin	(29)	0	1	27961	1
Bin	(29)	1	0	29562	1
Bin	(28)	0	1	8416	1
Bin	(28)	1	0	10017	1
Bin	(27)	0	1	51790	1
Bin	(27)	1	0	53391	1
Bin	(26)	0	1	13208	1
Bin	(26)	1	0	14809	1
Bin	(25)	0	1	12403	1
Bin	(25)	1	0	14004	1
Bin	(24)	0	1	12403	1
Bin	(24)	1	0	14004	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	21669	1
Bin	(22)	0	1	70	1
Bin	(22)	1	0	1671	1
Bin	(21)	0	1	70	1
Bin	(21)	1	0	1671	1
Bin	(20)	0	1	2835	1
Bin	(20)	1	0	4436	1
Bin	(19)	0	1	2835	1
Bin	(19)	1	0	4436	1
Bin	(18)	0	1	2835	1
Bin	(18)	1	0	4436	1
Bin	(17)	0	1	2835	1
Bin	(17)	1	0	4436	1
Bin	(16)	0	1	4082	1
Bin	(16)	1	0	5683	1
Bin	(15)	0	1	4082	1
Bin	(15)	1	0	5683	1
Bin	(14)	0	1	43199	1
Bin	(14)	1	0	44800	1
Bin	(13)	0	1	2192	1
Bin	(13)	1	0	3793	1
Bin	(12)	0	1	14080	1
Bin	(12)	1	0	15681	1
Bin	(11)	0	1	112340	1
Bin	(11)	1	0	113941	1
Bin	(10)	0	1	6712	1
Bin	(10)	1	0	8313	1
Bin	(9)	0	1	6622	1
Bin	(9)	1	0	8223	1
Bin	(8)	0	1	485	1
Bin	(8)	1	0	2086	1
Bin	(7)	0	1	565	1
Bin	(7)	1	0	2166	1
Bin	(6)	0	1	552	1
Bin	(6)	1	0	2153	1
Bin	(5)	0	1	632	1
Bin	(5)	1	0	2233	1
Bin	(4)	0	1	2154	1
Bin	(4)	1	0	3755	1
Bin	(3)	0	1	1477	1
Bin	(3)	1	0	3078	1
Bin	(2)	0	1	8769066	1
Bin	(2)	1	0	8770667	1
Bin	(1)	0	1	75539	1
Bin	(1)	1	0	77140	1
Bin	(0)	0	1	25	1
Bin	(0)	1	0	1626	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 153:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	35840331	1
Bin	True	19215496	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 153 to 154:

Signal assignment statement on line 153:

Signal assignment statement on line 154:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 153:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 153:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: