NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
RX_BUFFER_FSM_INST	100.0 % (69/69)	100.0 % (50/50)	100.0 % (48/48)	100.0 % (29/29)	100.0 % (24/24)	100.0 % (3/3)	100.0 % (223/223)
RX_BUFFER_POINTERS_INST	100.0 % (59/59)	100.0 % (60/60)	100.0 % (468/468)	100.0 % (55/55)	N.A.	N.A.	100.0 % (642/642)
CLK_GATE_RX_BUFFER_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
RX_BUFFER_RAM_INST	100.0 % (49/49)	100.0 % (30/30)	100.0 % (271288/271288)	100.0 % (25/25)	N.A.	N.A.	100.0 % (271392/271392)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST	100.0 % (146/146)	100.0 % (126/126)	100.0 % (1276/1276)	100.0 % (166/166)	N.A.	N.A.	100.0 % (1714/1714)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 436 to 438:

436:    rx_buf_res_n_d <= '0' when (mr_command_rrb = '1' or res_n = '0') 
437:                          else 
438:                      '1';

Count: 22752
Threshold: 1

Signal assignment statement on line 436:

436: rx_buf_res_n_d <= '0' when (mr_command_rrb = '1' or res_n = '0')
Count: 8532
Threshold: 1

Signal assignment statement on line 438:

438: '1';
Count: 14220
Threshold: 1

Sequential statement on lines 517 to 523:

517:    with data_selector select rxb_port_a_data_in <= 
518:        "0000" & frame_form_w            when "00001", 
...
522:        timestamp_capture(63 downto 32)  when "10000", 
523:        (others => '0')                  when others;

Count: 6438372
Threshold: 1

Signal assignment statement on line 518:

518: "0000" & frame_form_w when "00001",
Count: 27093
Threshold: 1

Signal assignment statement on line 519:

519: "000" & rec_ident when "00010",
Count: 27085
Threshold: 1

Signal assignment statement on line 520:

520: store_data_word when "00100",
Count: 3014534
Threshold: 1

Signal assignment statement on line 521:

521: timestamp_capture(31 downto 0) when "01000",
Count: 13399
Threshold: 1

Signal assignment statement on line 522:

522: timestamp_capture(63 downto 32) when "10000",
Count: 13399
Threshold: 1

Signal assignment statement on line 523:

523: (others => '0') when others;
Count: 3342862
Threshold: 1

If statement on lines 528 to 530:

528:    read_attempt <= mr_rx_data_read when (mr_mode_rxbam = RXBAM_ENABLED) 
529:                                    else 
530:                    mr_command_rxrpmv;

Count: 164993
Threshold: 1

Signal assignment statement on line 528:

528: read_attempt <= mr_rx_data_read when (mr_mode_rxbam = RXBAM_ENABLED)
Count: 159641
Threshold: 1

Signal assignment statement on line 530:

530: mr_command_rxrpmv;
Count: 5352
Threshold: 1

If statement on lines 532 to 534:

532:    read_increment <= '1' when (read_attempt = '1' and rx_empty_i = '0') 
533:                          else 
534:                      '0';

Count: 176391
Threshold: 1

Signal assignment statement on line 532:

532: read_increment <= '1' when (read_attempt = '1' and rx_empty_i = '0')
Count: 51685
Threshold: 1

Signal assignment statement on line 534:

534: '0';
Count: 124706
Threshold: 1

If statement on lines 540 to 543:

540:    write_raw_OK <= '1' when (write_raw_intent = '1' and overrun_condition = '0' and 
541:                              data_overrun_i = '0') 
542:                        else 
543:                    '0';

Count: 231589
Threshold: 1

Signal assignment statement on line 540:

540: write_raw_OK <= '1' when (write_raw_intent = '1' and overrun_condition = '0' and
Count: 112843
Threshold: 1

Signal assignment statement on line 543:

543: '0';
Count: 118746
Threshold: 1

If statement on lines 552 to 554:

552:    is_free_word <= '0' when (read_pointer = write_pointer_raw and frame_count > 0) 
553:                        else 
554:                    '1';

Count: 286989
Threshold: 1

Signal assignment statement on line 552:

552: is_free_word <= '0' when (read_pointer = write_pointer_raw and frame_count > 0)
Count: 49
Threshold: 1

Signal assignment statement on line 554:

554: '1';
Count: 286940
Threshold: 1

If statement on lines 563 to 565:

563:    overrun_condition <= '1' when (write_raw_intent = '1' and is_free_word = '0') 
564:                             else 
565:                         '0';

Count: 228965
Threshold: 1

Signal assignment statement on line 563:

563: overrun_condition <= '1' when (write_raw_intent = '1' and is_free_word = '0')
Count: 43
Threshold: 1

Signal assignment statement on line 565:

565: '0';
Count: 228922
Threshold: 1

If statement on lines 573 to 575:

573:    rxb_port_b_data_out <= rxb_port_b_data_out_i when (rx_empty_i = '0') 
574:                                                 else 
575:                                 (others => '0');

Count: 126369
Threshold: 1

Signal assignment statement on line 573:

573: rxb_port_b_data_out <= rxb_port_b_data_out_i when (rx_empty_i = '0')
Count: 50990
Threshold: 1

Signal assignment statement on line 575:

575: (others => '0');
Count: 75379
Threshold: 1

Sequential statement on lines 581 to 597:

581:    with rec_dlc select rwcnt_com <= 
582:        3 when "0000", --Zero bits 
...
596:        15 when "1110", --48 bytes 
597:        19 when others; --64 bytes

Count: 82451
Threshold: 1

Signal assignment statement on line 582:

582: 3 when "0000", --Zero bits
Count: 41222
Threshold: 1

Signal assignment statement on line 583:

583: 4 when "0001", --1 byte
Count: 9427
Threshold: 1

Signal assignment statement on line 584:

584: 4 when "0010", --2 bytes
Count: 1587
Threshold: 1

Signal assignment statement on line 585:

585: 4 when "0011", --3 bytes
Count: 1668
Threshold: 1

Signal assignment statement on line 586:

586: 4 when "0100", --4 bytes
Count: 2049
Threshold: 1

Signal assignment statement on line 587:

587: 5 when "0101", --5 bytes
Count: 1068
Threshold: 1

Signal assignment statement on line 588:

588: 5 when "0110", --6 bytes
Count: 1448
Threshold: 1

Signal assignment statement on line 589:

589: 5 when "0111", --7 bytes
Count: 1039
Threshold: 1

Signal assignment statement on line 590:

590: 5 when "1000", --8 bytes
Count: 2872
Threshold: 1

Signal assignment statement on line 591:

591: 6 when "1001", --12 bytes
Count: 906
Threshold: 1

Signal assignment statement on line 592:

592: 7 when "1010", --16 bytes
Count: 610
Threshold: 1

Signal assignment statement on line 593:

593: 8 when "1011", --20 bytes
Count: 450
Threshold: 1

Signal assignment statement on line 594:

594: 9 when "1100", --24 bytes
Count: 803
Threshold: 1

Signal assignment statement on line 595:

595: 11 when "1101", --32 bytes
Count: 706
Threshold: 1

Signal assignment statement on line 596:

596: 15 when "1110", --48 bytes
Count: 1717
Threshold: 1

Signal assignment statement on line 597:

597: 19 when others; --64 bytes
Count: 14879
Threshold: 1

Signal assignment statement on line 603:

603: frame_form_w(DLC_H downto DLC_L) <= rec_dlc;
Count: 82451
Threshold: 1

Signal assignment statement on line 604:

604: frame_form_w(ERF_IND) <= rec_erf;
Count: 3876
Threshold: 1

Signal assignment statement on line 605:

605: frame_form_w(RTR_IND) <= rec_is_rtr;
Count: 46874
Threshold: 1

Signal assignment statement on line 606:

606: frame_form_w(IDE_IND) <= rec_ident_type;
Count: 38455
Threshold: 1

Signal assignment statement on line 607:

607: frame_form_w(FDF_IND) <= rec_frame_type;
Count: 60965
Threshold: 1

Signal assignment statement on line 608:

608: frame_form_w(LBPF_IND) <= rec_lbpf;
Count: 3562
Threshold: 1

Signal assignment statement on line 609:

609: frame_form_w(BRS_IND) <= rec_brs;
Count: 43995
Threshold: 1

Signal assignment statement on line 610:

610: frame_form_w(ESI_RSV_IND) <= rec_esi;
Count: 8248
Threshold: 1

Signal assignment statement on line 611:

611: frame_form_w(IVLD_IND) <= rec_ivld;
Count: 105045
Threshold: 1

If statement on lines 619 to 622:

619:    frame_form_w(RWCNT_H downto RWCNT_L)  <= 
620:        "00011" when (rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED) else 
621:        "00101" when ((rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1')) else 
622:         std_logic_vector(to_unsigned(rwcnt_com, (RWCNT_H - RWCNT_L + 1)));

Count: 203971
Threshold: 1

Signal assignment statement on line 620:

620: "00011" when (rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED) else
Count: 27648
Threshold: 1

Signal assignment statement on line 621:

621: "00101" when ((rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1')) else
Count: 6350
Threshold: 1

Signal assignment statement on line 622:

622: std_logic_vector(to_unsigned(rwcnt_com, (RWCNT_H - RWCNT_L + 1)));
Count: 169973
Threshold: 1

If statement on lines 625 to 627:

625:    frame_form_w(ERF_POS_H downto ERF_POS_L) <= err_capt_err_pos when (rec_erf = '1') 
626:                                                                 else 
627:                                                (others => '0');

Count: 14313
Threshold: 1

Signal assignment statement on line 625:

625: frame_form_w(ERF_POS_H downto ERF_POS_L) <= err_capt_err_pos when (rec_erf = '1')
Count: 337
Threshold: 1

Signal assignment statement on line 627:

627: (others => '0');
Count: 13976
Threshold: 1

If statement on lines 629 to 631:

629:    frame_form_w(ERF_TYPE_H downto ERF_TYPE_L) <= err_capt_err_type when (rec_erf = '1') 
630:                                                                    else 
631:                                                  (others => '0');

Count: 9603
Threshold: 1

Signal assignment statement on line 629:

629: frame_form_w(ERF_TYPE_H downto ERF_TYPE_L) <= err_capt_err_type when (rec_erf = '1')
Count: 337
Threshold: 1

Signal assignment statement on line 631:

631:                                                  (others => '0');

Count: 9266
Threshold: 1

If statement on lines 633 to 635:

633:    frame_form_w(ERF_ERP_IND) <= err_capt_err_erp when (rec_erf = '1') 
634:                                                  else 
635:                                              '0';

Count: 6057
Threshold: 1

Signal assignment statement on line 633:

633: frame_form_w(ERF_ERP_IND) <= err_capt_err_erp when (rec_erf = '1')
Count: 337
Threshold: 1

Signal assignment statement on line 635:

635: '0';
Count: 5720
Threshold: 1

If statement on lines 638 to 640:

638:    frame_form_w(LBTBI_H downto LBTBI_L) <= curr_txtb_index when (rec_lbpf = LBPF_LOOPBACK) 
639:                                                            else 
640:                                            (others => '0');

Count: 17485
Threshold: 1

Signal assignment statement on line 638:

638: frame_form_w(LBTBI_H downto LBTBI_L) <= curr_txtb_index when (rec_lbpf = LBPF_LOOPBACK)
Count: 350
Threshold: 1

Signal assignment statement on line 640:

640: (others => '0');
Count: 17135
Threshold: 1

If statement on lines 648 to 654:

648:    timestamp_capture_ce <= '1' when (mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1') 
649:                                else 
...
653:                                else 
654:                            '0';

Count: 255211
Threshold: 1

Signal assignment statement on line 648:

648: timestamp_capture_ce <= '1' when (mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1')
Count: 13052
Threshold: 1

Signal assignment statement on line 650:

650:                            '1' when (mr_rx_settings_rtsop = RTS_BEG and sof_pulse = '1')

Count: 15
Threshold: 1

Signal assignment statement on line 652:

652:                            '1' when (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1')

Count: 337
Threshold: 1

Signal assignment statement on line 654:

654: '0';
Count: 241807
Threshold: 1

If statement on lines 658 to 664:

658:        if (res_n = '0') then 
659:            timestamp_capture <= (others => '0'); 
...
663:            end if; 
664:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 659:

659: timestamp_capture <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 661 to 663:

661:            if (timestamp_capture_ce = '1') then 
662:                timestamp_capture   <= timestamp; 
663:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 662:

662: timestamp_capture <= timestamp;
Count: 13399
Threshold: 1

If statement on lines 679 to 681:

679:    read_counter_d <= read_counter_q - 1 when (read_counter_q > "00000") 
680:                                         else 
681:                      unsigned(rxb_port_b_data_out_i(RWCNT_H downto RWCNT_L));

Count: 157150
Threshold: 1

Signal assignment statement on line 679:

679: read_counter_d <= read_counter_q - 1 when (read_counter_q > "00000")
Count: 79350
Threshold: 1

Signal assignment statement on line 681:

681: unsigned(rxb_port_b_data_out_i(RWCNT_H downto RWCNT_L));
Count: 77800
Threshold: 1

If statement on lines 685 to 693:

685:        if (rx_buf_res_n_q_scan = '0') then 
686:            read_counter_q <= (others => '0'); 
...
692:            end if; 
693:        end if;

Count: 1090018917
Threshold: 1

Signal assignment statement on line 686:

686: read_counter_q <= (others => '0');
Count: 2438917
Threshold: 1

If statement on lines 690 to 692:

690:            if (read_increment = '1') then 
691:                read_counter_q <= read_counter_d; 
692:            end if;

Count: 543784839
Threshold: 1

Signal assignment statement on line 691:

691: read_counter_q <= read_counter_d;
Count: 51685
Threshold: 1

If statement on lines 704 to 719:

704:        if (rx_buf_res_n_q_scan = '0') then 
705:            frame_count <= (others => '0'); 
...
718: 
719:        end if;

Count: 1090018917
Threshold: 1

Signal assignment statement on line 705:

705: frame_count <= (others => '0');
Count: 2438917
Threshold: 1

If statement on lines 709 to 717:

709:            if ((read_increment = '1') and (read_counter_q = "00001")) then 
710:                if (commit_rx_frame = '0') then 
...
716:                frame_count <= frame_count + 1; 
717:            end if;

Count: 543784839
Threshold: 1

If statement on lines 710 to 712:

710:                if (commit_rx_frame = '0') then 
711:                    frame_count <= frame_count - 1; 
712:                end if;

Count: 9334
Threshold: 1

Signal assignment statement on line 711:

711: frame_count <= frame_count - 1;
Count: 9329
Threshold: 1

Signal assignment statement on line 716:

716: frame_count <= frame_count + 1;
Count: 13353
Threshold: 1

If statement on lines 729 to 746:

729:        if (rx_buf_res_n_q_scan = '0') then 
730:            commit_rx_frame       <= '0'; 
...
745: 
746:        end if;

Count: 1090018917
Threshold: 1

Signal assignment statement on line 730:

730: commit_rx_frame <= '0';
Count: 2438917
Threshold: 1

Signal assignment statement on line 731:

731: commit_overrun_abort <= '0';
Count: 2438917
Threshold: 1

If statement on lines 735 to 744:

735:            if (commit_intent = '1') then 
736:                if (data_overrun_i = '0') then 
...
743:                commit_overrun_abort <= '0'; 
744:            end if;

Count: 543784839
Threshold: 1

If statement on lines 736 to 740:

736:                if (data_overrun_i = '0') then 
737:                    commit_rx_frame <= '1'; 
738:                else 
739:                    commit_overrun_abort <= '1'; 
740:                end if;

Count: 13399
Threshold: 1

Signal assignment statement on line 737:

737: commit_rx_frame <= '1';
Count: 13358
Threshold: 1

Signal assignment statement on line 739:

739: commit_overrun_abort <= '1';
Count: 41
Threshold: 1

Signal assignment statement on line 742:

742: commit_rx_frame <= '0';
Count: 543771440
Threshold: 1

Signal assignment statement on line 743:

743: commit_overrun_abort <= '0';
Count: 543771440
Threshold: 1

If statement on lines 757 to 770:

757:        if (rx_buf_res_n_q_scan = '0') then 
758:            data_overrun_flg <= '0'; 
...
769: 
770:        end if;

Count: 1090018917
Threshold: 1

Signal assignment statement on line 758:

758: data_overrun_flg <= '0';
Count: 2438917
Threshold: 1

If statement on lines 762 to 768:

762:            if (mr_command_cdo = '1') then 
763:                data_overrun_flg <= '0'; 
...
767:                data_overrun_flg <= data_overrun_flg; 
768:            end if;

Count: 543784839
Threshold: 1

Signal assignment statement on line 763:

763: data_overrun_flg <= '0';
Count: 20
Threshold: 1

Signal assignment statement on line 765:

765: data_overrun_flg <= '1';
Count: 139
Threshold: 1

Signal assignment statement on line 767:

767: data_overrun_flg <= data_overrun_flg;
Count: 543784680
Threshold: 1

If statement on lines 789 to 799:

789:        if (res_n = '0') then 
790:            data_overrun_i <= '0'; 
...
798:            end if; 
799:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 790:

790: data_overrun_i <= '0';
Count: 2424883
Threshold: 1

If statement on lines 792 to 798:

792:            if (overrun_condition = '1' or mr_command_rrb = '1') then 
793:                data_overrun_i <= '1'; 
...
797:                data_overrun_i <= data_overrun_i; 
798:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 793:

793: data_overrun_i <= '1';
Count: 599
Threshold: 1

Signal assignment statement on line 795:

795: data_overrun_i <= '0';
Count: 435727113
Threshold: 1

Signal assignment statement on line 797:

797: data_overrun_i <= data_overrun_i;
Count: 108063966
Threshold: 1

If statement on lines 808 to 812:

808:    rx_buf_ram_clk_en <= '1' when (rxb_port_a_write = '1' or read_attempt = '1') 
809:                             else 
810:                         '1' when (mr_tst_control_tmaena = '1') 
811:                             else 
812:                         '0';

Count: 414617
Threshold: 1

Signal assignment statement on line 808:

808: rx_buf_ram_clk_en <= '1' when (rxb_port_a_write = '1' or read_attempt = '1')
Count: 177858
Threshold: 1

Signal assignment statement on line 810:

810: '1' when (mr_tst_control_tmaena = '1')
Count: 648
Threshold: 1

Signal assignment statement on line 812:

812: '0';
Count: 236111
Threshold: 1

If statement on lines 864 to 867:

864:    rxb_port_a_write  <= '1' when (write_raw_OK = '1' or 
865:                                  (select_ts_wptr = '1' and data_overrun_i = '0')) 
866:                             else 
867:                         '0';

Count: 257607
Threshold: 1

Signal assignment statement on line 864:

864: rxb_port_a_write <= '1' when (write_raw_OK = '1' or
Count: 125864
Threshold: 1

Signal assignment statement on line 867:

867: '0';
Count: 131743
Threshold: 1

If statement on lines 873 to 875:

873:    rxb_port_a_address   <= write_pointer_ts when (select_ts_wptr = '1') 
874:                                             else 
875:                           write_pointer_raw;

Count: 251714
Threshold: 1

Signal assignment statement on line 873:

873: rxb_port_a_address <= write_pointer_ts when (select_ts_wptr = '1')
Count: 26124
Threshold: 1

Signal assignment statement on line 875:

875: write_pointer_raw;
Count: 225590
Threshold: 1

If statement on lines 882 to 884:

882:    rxb_port_b_address <= read_pointer_inc_1 when (read_increment = '1') 
883:                                             else 
884:                                read_pointer;

Count: 209410
Threshold: 1

Signal assignment statement on line 882:

882: rxb_port_b_address <= read_pointer_inc_1 when (read_increment = '1')
Count: 148086
Threshold: 1

Signal assignment statement on line 884:

884: read_pointer;
Count: 61324
Threshold: 1

If statement on lines 890 to 892:

890:    rx_mof <= '0' when (read_counter_q = "00000") 
891:                  else 
892:              '1';

Count: 54889
Threshold: 1

Signal assignment statement on line 890:

890: rx_mof <= '0' when (read_counter_q = "00000")
Count: 10937
Threshold: 1

Signal assignment statement on line 892:

892: '1';
Count: 43952
Threshold: 1

If statement on lines 901 to 910:

901:        if (res_n = '0') then 
902:            rx_parity_error <= '0'; 
...
909:            end if; 
910:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 902:

902: rx_parity_error <= '0';
Count: 2424883
Threshold: 1

If statement on lines 904 to 909:

904:            if (read_attempt = '1' and rx_parity_mismatch_comb = '1' and mr_settings_pchke = '1') 
905:            then 
906:                rx_parity_error <= '1'; 
907:            elsif (mr_command_crxpe = '1') then 
908:                rx_parity_error <= '0'; 
909:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 906:

906: rx_parity_error <= '1';
Count: 9
Threshold: 1

Signal assignment statement on line 908:

908: rx_parity_error <= '0';
Count: 40
Threshold: 1

Signal assignment statement on line 917:

917: rx_read_pointer <= read_pointer;
Count: 55704
Threshold: 1

Signal assignment statement on line 918:

918: rx_write_pointer <= write_pointer;
Count: 17729
Threshold: 1

Signal assignment statement on line 919:

919: rx_data_overrun <= data_overrun_flg;
Count: 3264
Threshold: 1

If statement on lines 921 to 923:

921:    rx_empty_i       <= '1' when (frame_count = 0) 
922:                            else 
923:                        '0';

Count: 26313
Threshold: 1

Signal assignment statement on line 921:

921: rx_empty_i <= '1' when (frame_count = 0)
Count: 8999
Threshold: 1

Signal assignment statement on line 923:

923: '0';
Count: 17314
Threshold: 1

If statement on lines 925 to 927:

925:    rx_full          <= '1' when (rx_mem_free_i = C_RX_BUF_MEM_FREE_ZEROES) 
926:                            else 
927:                        '0';

Count: 68645
Threshold: 1

Signal assignment statement on line 925:

925: rx_full <= '1' when (rx_mem_free_i = C_RX_BUF_MEM_FREE_ZEROES)
Count: 20
Threshold: 1

Signal assignment statement on line 927:

927: '0';
Count: 68625
Threshold: 1

Signal assignment statement on line 929:

929: rx_frame_count <= std_logic_vector(frame_count);
Count: 26313
Threshold: 1

Signal assignment statement on line 930:

930: rx_mem_free <= rx_mem_free_i;
Count: 68645
Threshold: 1

Signal assignment statement on line 931:

931: rx_empty <= rx_empty_i;
Count: 19601
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 436:

436: rx_buf_res_n_d <= '0' when (mr_command_rrb = '1' or res_n = '0')

	Evaluated to	Count	Threshold
Bin	True	8532	1
Bin	False	14220	1

"case" / "with" / "select" choice on line 518:

518: "0000" & frame_form_w when "00001",

	Choice of	Count	Threshold
Bin	`"00001"`	27093	1

"case" / "with" / "select" choice on line 519:

519: "000" & rec_ident when "00010",

	Choice of	Count	Threshold
Bin	`"00010"`	27085	1

"case" / "with" / "select" choice on line 520:

520: store_data_word when "00100",

	Choice of	Count	Threshold
Bin	`"00100"`	3014534	1

"case" / "with" / "select" choice on line 521:

521: timestamp_capture(31 downto 0) when "01000",

	Choice of	Count	Threshold
Bin	`"01000"`	13399	1

"case" / "with" / "select" choice on line 522:

522: timestamp_capture(63 downto 32) when "10000",

	Choice of	Count	Threshold
Bin	`"10000"`	13399	1

"case" / "with" / "select" choice on line 523:

523: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	3342862	1

"if" / "when" / "else" condition on line 528:

528: read_attempt <= mr_rx_data_read when (mr_mode_rxbam = RXBAM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	159641	1
Bin	False	5352	1

"if" / "when" / "else" condition on line 532:

532: read_increment <= '1' when (read_attempt = '1' and rx_empty_i = '0')

	Evaluated to	Count	Threshold
Bin	True	51685	1
Bin	False	124706	1

"if" / "when" / "else" condition on lines 540 to 541:

540:    write_raw_OK <= '1' when (write_raw_intent = '1' and overrun_condition = '0' and 
541:                              data_overrun_i = '0')

	Evaluated to	Count	Threshold
Bin	True	112843	1
Bin	False	118746	1

"if" / "when" / "else" condition on line 552:

552: is_free_word <= '0' when (read_pointer = write_pointer_raw and frame_count > 0)

	Evaluated to	Count	Threshold
Bin	True	49	1
Bin	False	286940	1

"if" / "when" / "else" condition on line 563:

563: overrun_condition <= '1' when (write_raw_intent = '1' and is_free_word = '0')

	Evaluated to	Count	Threshold
Bin	True	43	1
Bin	False	228922	1

"if" / "when" / "else" condition on line 573:

573: rxb_port_b_data_out <= rxb_port_b_data_out_i when (rx_empty_i = '0')

	Evaluated to	Count	Threshold
Bin	True	50990	1
Bin	False	75379	1

"case" / "with" / "select" choice on line 582:

582: 3 when "0000", --Zero bits

	Choice of	Count	Threshold
Bin	`"0000"`	41222	1

"case" / "with" / "select" choice on line 583:

583: 4 when "0001", --1 byte

	Choice of	Count	Threshold
Bin	`"0001"`	9427	1

"case" / "with" / "select" choice on line 584:

584: 4 when "0010", --2 bytes

	Choice of	Count	Threshold
Bin	`"0010"`	1587	1

"case" / "with" / "select" choice on line 585:

585: 4 when "0011", --3 bytes

	Choice of	Count	Threshold
Bin	`"0011"`	1668	1

"case" / "with" / "select" choice on line 586:

586: 4 when "0100", --4 bytes

	Choice of	Count	Threshold
Bin	`"0100"`	2049	1

"case" / "with" / "select" choice on line 587:

587: 5 when "0101", --5 bytes

	Choice of	Count	Threshold
Bin	`"0101"`	1068	1

"case" / "with" / "select" choice on line 588:

588: 5 when "0110", --6 bytes

	Choice of	Count	Threshold
Bin	`"0110"`	1448	1

"case" / "with" / "select" choice on line 589:

589: 5 when "0111", --7 bytes

	Choice of	Count	Threshold
Bin	`"0111"`	1039	1

"case" / "with" / "select" choice on line 590:

590: 5 when "1000", --8 bytes

	Choice of	Count	Threshold
Bin	`"1000"`	2872	1

"case" / "with" / "select" choice on line 591:

591: 6 when "1001", --12 bytes

	Choice of	Count	Threshold
Bin	`"1001"`	906	1

"case" / "with" / "select" choice on line 592:

592: 7 when "1010", --16 bytes

	Choice of	Count	Threshold
Bin	`"1010"`	610	1

"case" / "with" / "select" choice on line 593:

593: 8 when "1011", --20 bytes

	Choice of	Count	Threshold
Bin	`"1011"`	450	1

"case" / "with" / "select" choice on line 594:

594: 9 when "1100", --24 bytes

	Choice of	Count	Threshold
Bin	`"1100"`	803	1

"case" / "with" / "select" choice on line 595:

595: 11 when "1101", --32 bytes

	Choice of	Count	Threshold
Bin	`"1101"`	706	1

"case" / "with" / "select" choice on line 596:

596: 15 when "1110", --48 bytes

	Choice of	Count	Threshold
Bin	`"1110"`	1717	1

"case" / "with" / "select" choice on line 597:

597: 19 when others; --64 bytes

	Choice of	Count	Threshold
Bin	`others`	14879	1

"if" / "when" / "else" condition on line 620:

620: "00011" when (rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED) else

	Evaluated to	Count	Threshold
Bin	True	27648	1
Bin	False	176323	1

"if" / "when" / "else" condition on line 621:

621: "00101" when ((rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1')) else

	Evaluated to	Count	Threshold
Bin	True	6350	1
Bin	False	169973	1

"if" / "when" / "else" condition on line 625:

625: frame_form_w(ERF_POS_H downto ERF_POS_L) <= err_capt_err_pos when (rec_erf = '1')

	Evaluated to	Count	Threshold
Bin	True	337	1
Bin	False	13976	1

"if" / "when" / "else" condition on line 629:

629: frame_form_w(ERF_TYPE_H downto ERF_TYPE_L) <= err_capt_err_type when (rec_erf = '1')

	Evaluated to	Count	Threshold
Bin	True	337	1
Bin	False	9266	1

"if" / "when" / "else" condition on line 633:

633: frame_form_w(ERF_ERP_IND) <= err_capt_err_erp when (rec_erf = '1')

	Evaluated to	Count	Threshold
Bin	True	337	1
Bin	False	5720	1

"if" / "when" / "else" condition on line 638:

638: frame_form_w(LBTBI_H downto LBTBI_L) <= curr_txtb_index when (rec_lbpf = LBPF_LOOPBACK)

	Evaluated to	Count	Threshold
Bin	True	350	1
Bin	False	17135	1

"if" / "when" / "else" condition on line 648:

648: timestamp_capture_ce <= '1' when (mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1')

	Evaluated to	Count	Threshold
Bin	True	13052	1
Bin	False	242159	1

"if" / "when" / "else" condition on line 650:

650:                            '1' when (mr_rx_settings_rtsop = RTS_BEG and sof_pulse = '1')

	Evaluated to	Count	Threshold
Bin	True	15	1
Bin	False	242144	1

"if" / "when" / "else" condition on line 652:

652:                            '1' when (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1')

	Evaluated to	Count	Threshold
Bin	True	337	1
Bin	False	241807	1

"if" / "when" / "else" condition on line 658:

658: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 660:

660: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 661:

661: if (timestamp_capture_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	13399	1
Bin	False	543778279	1

"if" / "when" / "else" condition on line 679:

679: read_counter_d <= read_counter_q - 1 when (read_counter_q > "00000")

	Evaluated to	Count	Threshold
Bin	True	79350	1
Bin	False	77800	1

"if" / "when" / "else" condition on line 685:

685: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2438917	1
Bin	False	1087580000	1

"if" / "when" / "else" condition on line 687:

687: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543784839	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 690:

690: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	True	51685	1
Bin	False	543733154	1

"if" / "when" / "else" condition on line 704:

704: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2438917	1
Bin	False	1087580000	1

"if" / "when" / "else" condition on line 706:

706: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543784839	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 709:

709: if ((read_increment = '1') and (read_counter_q = "00001")) then

	Evaluated to	Count	Threshold
Bin	True	9334	1
Bin	False	543775505	1

"if" / "when" / "else" condition on line 710:

710: if (commit_rx_frame = '0') then

	Evaluated to	Count	Threshold
Bin	True	9329	1
Bin	False	5	1

"if" / "when" / "else" condition on line 715:

715: elsif (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	True	13353	1
Bin	False	543762152	1

"if" / "when" / "else" condition on line 729:

729: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2438917	1
Bin	False	1087580000	1

"if" / "when" / "else" condition on line 733:

733: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543784839	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 735:

735: if (commit_intent = '1') then

	Evaluated to	Count	Threshold
Bin	True	13399	1
Bin	False	543771440	1

"if" / "when" / "else" condition on line 736:

736: if (data_overrun_i = '0') then

	Evaluated to	Count	Threshold
Bin	True	13358	1
Bin	False	41	1

"if" / "when" / "else" condition on line 757:

757: if (rx_buf_res_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2438917	1
Bin	False	1087580000	1

"if" / "when" / "else" condition on line 759:

759: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543784839	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 762:

762: if (mr_command_cdo = '1') then

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	543784819	1

"if" / "when" / "else" condition on line 764:

764: elsif (overrun_condition = '1') then

	Evaluated to	Count	Threshold
Bin	True	139	1
Bin	False	543784680	1

"if" / "when" / "else" condition on line 789:

789: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 791:

791: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 792:

792: if (overrun_condition = '1' or mr_command_rrb = '1') then

	Evaluated to	Count	Threshold
Bin	True	599	1
Bin	False	543791079	1

"if" / "when" / "else" condition on line 794:

794: elsif (reset_overrun_flag = '1') then

	Evaluated to	Count	Threshold
Bin	True	435727113	1
Bin	False	108063966	1

"if" / "when" / "else" condition on line 808:

808: rx_buf_ram_clk_en <= '1' when (rxb_port_a_write = '1' or read_attempt = '1')

	Evaluated to	Count	Threshold
Bin	True	177858	1
Bin	False	236759	1

"if" / "when" / "else" condition on line 810:

810: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	648	1
Bin	False	236111	1

"if" / "when" / "else" condition on lines 864 to 865:

864:    rxb_port_a_write  <= '1' when (write_raw_OK = '1' or 
865:                                  (select_ts_wptr = '1' and data_overrun_i = '0'))

	Evaluated to	Count	Threshold
Bin	True	125864	1
Bin	False	131743	1

"if" / "when" / "else" condition on line 873:

873: rxb_port_a_address <= write_pointer_ts when (select_ts_wptr = '1')

	Evaluated to	Count	Threshold
Bin	True	26124	1
Bin	False	225590	1

"if" / "when" / "else" condition on line 882:

882: rxb_port_b_address <= read_pointer_inc_1 when (read_increment = '1')

	Evaluated to	Count	Threshold
Bin	True	148086	1
Bin	False	61324	1

"if" / "when" / "else" condition on line 890:

890: rx_mof <= '0' when (read_counter_q = "00000")

	Evaluated to	Count	Threshold
Bin	True	10937	1
Bin	False	43952	1

"if" / "when" / "else" condition on line 901:

901: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 903:

903: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 904:

904:            if (read_attempt = '1' and rx_parity_mismatch_comb = '1' and mr_settings_pchke = '1')

	Evaluated to	Count	Threshold
Bin	True	9	1
Bin	False	543791669	1

"if" / "when" / "else" condition on line 907:

907: elsif (mr_command_crxpe = '1') then

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	543791629	1

"if" / "when" / "else" condition on line 921:

921: rx_empty_i <= '1' when (frame_count = 0)

	Evaluated to	Count	Threshold
Bin	True	8999	1
Bin	False	17314	1

"if" / "when" / "else" condition on line 925:

925: rx_full <= '1' when (rx_mem_free_i = C_RX_BUF_MEM_FREE_ZEROES)

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	68625	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_IDENT

	Element	From	To	Threshold	Excluded due to
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

REC_DLC

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

REC_IDENT_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_FRAME_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_LBPF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_IS_RTR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_BRS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_ESI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_IVLD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_METADATA_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_DATA_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_DATA_WORD

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

REC_VALID_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_ABORT_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SOF_PULSE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_CAPT_ERR_TYPE

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ERR_CAPT_ERR_POS

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ERR_CAPT_ERR_ERP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TIMESTAMP

	Element	From	To	Threshold	Excluded due to
Bin	(63)	0	1	1	Exclude file
Bin	(63)	1	0	1	Exclude file
Bin	(62)	0	1	1	Exclude file
Bin	(62)	1	0	1	Exclude file
Bin	(61)	0	1	1	Exclude file
Bin	(61)	1	0	1	Exclude file
Bin	(60)	0	1	1	Exclude file
Bin	(60)	1	0	1	Exclude file
Bin	(59)	0	1	1	Exclude file
Bin	(59)	1	0	1	Exclude file
Bin	(58)	0	1	1	Exclude file
Bin	(58)	1	0	1	Exclude file
Bin	(57)	0	1	1	Exclude file
Bin	(57)	1	0	1	Exclude file
Bin	(56)	0	1	1	Exclude file
Bin	(56)	1	0	1	Exclude file
Bin	(55)	0	1	1	Exclude file
Bin	(55)	1	0	1	Exclude file
Bin	(54)	0	1	1	Exclude file
Bin	(54)	1	0	1	Exclude file
Bin	(53)	0	1	1	Exclude file
Bin	(53)	1	0	1	Exclude file
Bin	(52)	0	1	1	Exclude file
Bin	(52)	1	0	1	Exclude file
Bin	(51)	0	1	1	Exclude file
Bin	(51)	1	0	1	Exclude file
Bin	(50)	0	1	1	Exclude file
Bin	(50)	1	0	1	Exclude file
Bin	(49)	0	1	1	Exclude file
Bin	(49)	1	0	1	Exclude file
Bin	(48)	0	1	1	Exclude file
Bin	(48)	1	0	1	Exclude file
Bin	(47)	0	1	1	Exclude file
Bin	(47)	1	0	1	Exclude file
Bin	(46)	0	1	1	Exclude file
Bin	(46)	1	0	1	Exclude file
Bin	(45)	0	1	1	Exclude file
Bin	(45)	1	0	1	Exclude file
Bin	(44)	0	1	1	Exclude file
Bin	(44)	1	0	1	Exclude file
Bin	(43)	0	1	1	Exclude file
Bin	(43)	1	0	1	Exclude file
Bin	(42)	0	1	1	Exclude file
Bin	(42)	1	0	1	Exclude file
Bin	(41)	0	1	1	Exclude file
Bin	(41)	1	0	1	Exclude file
Bin	(40)	0	1	1	Exclude file
Bin	(40)	1	0	1	Exclude file
Bin	(39)	0	1	1	Exclude file
Bin	(39)	1	0	1	Exclude file
Bin	(38)	0	1	1	Exclude file
Bin	(38)	1	0	1	Exclude file
Bin	(37)	0	1	1	Exclude file
Bin	(37)	1	0	1	Exclude file
Bin	(36)	0	1	1	Exclude file
Bin	(36)	1	0	1	Exclude file
Bin	(35)	0	1	1	Exclude file
Bin	(35)	1	0	1	Exclude file
Bin	(34)	0	1	1	Exclude file
Bin	(34)	1	0	1	Exclude file
Bin	(33)	0	1	1	Exclude file
Bin	(33)	1	0	1	Exclude file
Bin	(32)	0	1	1	Exclude file
Bin	(32)	1	0	1	Exclude file
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CURR_TXTB_INDEX

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_MODE_RXBAM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_CDO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_CRXPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_RRB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_RXRPMV

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_RX_DATA_READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_RX_SETTINGS_RTSOP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ERFM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

RX_FULL

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1621	1

Port:

RX_EMPTY

	From	To	Count	Threshold
Bin	0	1	8999	1
Bin	1	0	9001	1

Port:

RX_FRAME_COUNT

	Element	From	To	Count	Threshold
Bin	(10)	0	1	4	1
Bin	(10)	1	0	169	1
Bin	(9)	0	1	5	1
Bin	(9)	1	0	170	1
Bin	(8)	0	1	10	1
Bin	(8)	1	0	175	1
Bin	(7)	0	1	21	1
Bin	(7)	1	0	186	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	208	1
Bin	(5)	0	1	98	1
Bin	(5)	1	0	758	1
Bin	(4)	0	1	195	1
Bin	(4)	1	0	855	1
Bin	(3)	0	1	404	1
Bin	(3)	1	0	2005	1
Bin	(2)	0	1	846	1
Bin	(2)	1	0	2447	1
Bin	(1)	0	1	2538	1
Bin	(1)	1	0	4139	1
Bin	(0)	0	1	11478	1
Bin	(0)	1	0	13077	1

Port:

RX_MEM_FREE

	Element	From	To	Count	Threshold
Bin	(12)	0	1	1239	1
Bin	(12)	1	0	1074	1
Bin	(11)	0	1	1076	1
Bin	(11)	1	0	1241	1
Bin	(10)	0	1	1083	1
Bin	(10)	1	0	1248	1
Bin	(9)	0	1	1097	1
Bin	(9)	1	0	1262	1
Bin	(8)	0	1	1125	1
Bin	(8)	1	0	1290	1
Bin	(7)	0	1	4532	1
Bin	(7)	1	0	4202	1
Bin	(6)	0	1	4159	1
Bin	(6)	1	0	4819	1
Bin	(5)	0	1	8826	1
Bin	(5)	1	0	8547	1
Bin	(4)	0	1	8414	1
Bin	(4)	1	0	10013	1
Bin	(3)	0	1	10005	1
Bin	(3)	1	0	11604	1
Bin	(2)	0	1	12209	1
Bin	(2)	1	0	13808	1
Bin	(1)	0	1	16073	1
Bin	(1)	1	0	17674	1
Bin	(0)	0	1	27447	1
Bin	(0)	1	0	29048	1

Port:

RX_READ_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	2	1
Bin	(11)	1	0	167	1
Bin	(10)	0	1	5	1
Bin	(10)	1	0	170	1
Bin	(9)	0	1	11	1
Bin	(9)	1	0	176	1
Bin	(8)	0	1	21	1
Bin	(8)	1	0	186	1
Bin	(7)	0	1	41	1
Bin	(7)	1	0	206	1
Bin	(6)	0	1	205	1
Bin	(6)	1	0	865	1
Bin	(5)	0	1	443	1
Bin	(5)	1	0	1103	1
Bin	(4)	0	1	1578	1
Bin	(4)	1	0	3179	1
Bin	(3)	0	1	3184	1
Bin	(3)	1	0	4785	1
Bin	(2)	0	1	6633	1
Bin	(2)	1	0	8234	1
Bin	(1)	0	1	13003	1
Bin	(1)	1	0	14604	1
Bin	(0)	0	1	25973	1
Bin	(0)	1	0	27574	1

Port:

RX_WRITE_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	5	1
Bin	(11)	1	0	170	1
Bin	(10)	0	1	11	1
Bin	(10)	1	0	176	1
Bin	(9)	0	1	23	1
Bin	(9)	1	0	188	1
Bin	(8)	0	1	45	1
Bin	(8)	1	0	210	1
Bin	(7)	0	1	89	1
Bin	(7)	1	0	254	1
Bin	(6)	0	1	311	1
Bin	(6)	1	0	971	1
Bin	(5)	0	1	669	1
Bin	(5)	1	0	1329	1
Bin	(4)	0	1	1971	1
Bin	(4)	1	0	3572	1
Bin	(3)	0	1	3777	1
Bin	(3)	1	0	5378	1
Bin	(2)	0	1	6171	1
Bin	(2)	1	0	7770	1
Bin	(1)	0	1	1881	1
Bin	(1)	1	0	3482	1
Bin	(0)	0	1	1735	1
Bin	(0)	1	0	3336	1

Port:

RX_DATA_OVERRUN

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	1632	1

Port:

RX_MOF

	From	To	Count	Threshold
Bin	0	1	10937	1
Bin	1	0	10937	1

Port:

RX_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	9	1
Bin	1	0	1610	1

Port:

RXB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	3622	1
Bin	(31)	1	0	6824	1
Bin	(30)	0	1	3306	1
Bin	(30)	1	0	6508	1
Bin	(29)	0	1	3453	1
Bin	(29)	1	0	6655	1
Bin	(28)	0	1	7017	1
Bin	(28)	1	0	10219	1
Bin	(27)	0	1	6562	1
Bin	(27)	1	0	9764	1
Bin	(26)	0	1	7325	1
Bin	(26)	1	0	10527	1
Bin	(25)	0	1	7564	1
Bin	(25)	1	0	10766	1
Bin	(24)	0	1	12948	1
Bin	(24)	1	0	16148	1
Bin	(23)	0	1	7608	1
Bin	(23)	1	0	10810	1
Bin	(22)	0	1	7278	1
Bin	(22)	1	0	10480	1
Bin	(21)	0	1	7292	1
Bin	(21)	1	0	10494	1
Bin	(20)	0	1	6896	1
Bin	(20)	1	0	10098	1
Bin	(19)	0	1	8986	1
Bin	(19)	1	0	12188	1
Bin	(18)	0	1	9864	1
Bin	(18)	1	0	13066	1
Bin	(17)	0	1	8008	1
Bin	(17)	1	0	11210	1
Bin	(16)	0	1	8013	1
Bin	(16)	1	0	11215	1
Bin	(15)	0	1	8684	1
Bin	(15)	1	0	11886	1
Bin	(14)	0	1	9472	1
Bin	(14)	1	0	12674	1
Bin	(13)	0	1	13026	1
Bin	(13)	1	0	16228	1
Bin	(12)	0	1	13730	1
Bin	(12)	1	0	16930	1
Bin	(11)	0	1	15194	1
Bin	(11)	1	0	18394	1
Bin	(10)	0	1	10533	1
Bin	(10)	1	0	13735	1
Bin	(9)	0	1	12104	1
Bin	(9)	1	0	15306	1
Bin	(8)	0	1	9815	1
Bin	(8)	1	0	13017	1
Bin	(7)	0	1	13100	1
Bin	(7)	1	0	16302	1
Bin	(6)	0	1	11654	1
Bin	(6)	1	0	14856	1
Bin	(5)	0	1	11411	1
Bin	(5)	1	0	14613	1
Bin	(4)	0	1	10162	1
Bin	(4)	1	0	13364	1
Bin	(3)	0	1	11069	1
Bin	(3)	1	0	14271	1
Bin	(2)	0	1	11737	1
Bin	(2)	1	0	14939	1
Bin	(1)	0	1	12343	1
Bin	(1)	1	0	15545	1
Bin	(0)	0	1	12286	1
Bin	(0)	1	0	15488	1

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	21367	1
Bin	(31)	1	0	18461	1
Bin	(30)	0	1	12412	1
Bin	(30)	1	0	18525	1
Bin	(29)	0	1	16815	1
Bin	(29)	1	0	13909	1
Bin	(28)	0	1	16940	1
Bin	(28)	1	0	23053	1
Bin	(27)	0	1	17060	1
Bin	(27)	1	0	14154	1
Bin	(26)	0	1	16978	1
Bin	(26)	1	0	23091	1
Bin	(25)	0	1	21620	1
Bin	(25)	1	0	18714	1
Bin	(24)	0	1	12671	1
Bin	(24)	1	0	18784	1
Bin	(23)	0	1	21389	1
Bin	(23)	1	0	18483	1
Bin	(22)	0	1	12434	1
Bin	(22)	1	0	18547	1
Bin	(21)	0	1	16860	1
Bin	(21)	1	0	13954	1
Bin	(20)	0	1	16980	1
Bin	(20)	1	0	23093	1
Bin	(19)	0	1	17095	1
Bin	(19)	1	0	14189	1
Bin	(18)	0	1	17033	1
Bin	(18)	1	0	23146	1
Bin	(17)	0	1	21613	1
Bin	(17)	1	0	18707	1
Bin	(16)	0	1	12579	1
Bin	(16)	1	0	18692	1
Bin	(15)	0	1	21406	1
Bin	(15)	1	0	18500	1
Bin	(14)	0	1	12438	1
Bin	(14)	1	0	18551	1
Bin	(13)	0	1	16915	1
Bin	(13)	1	0	14009	1
Bin	(12)	0	1	17003	1
Bin	(12)	1	0	23116	1
Bin	(11)	0	1	17136	1
Bin	(11)	1	0	14230	1
Bin	(10)	0	1	17017	1
Bin	(10)	1	0	23130	1
Bin	(9)	0	1	21690	1
Bin	(9)	1	0	18784	1
Bin	(8)	0	1	12630	1
Bin	(8)	1	0	18743	1
Bin	(7)	0	1	21426	1
Bin	(7)	1	0	18520	1
Bin	(6)	0	1	12456	1
Bin	(6)	1	0	18569	1
Bin	(5)	0	1	16872	1
Bin	(5)	1	0	13966	1
Bin	(4)	0	1	16991	1
Bin	(4)	1	0	23104	1
Bin	(3)	0	1	17100	1
Bin	(3)	1	0	14194	1
Bin	(2)	0	1	17032	1
Bin	(2)	1	0	23145	1
Bin	(1)	0	1	21693	1
Bin	(1)	1	0	18787	1
Bin	(0)	0	1	12639	1
Bin	(0)	1	0	18752	1

Signal:

READ_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	2	1
Bin	(11)	1	0	167	1
Bin	(10)	0	1	5	1
Bin	(10)	1	0	170	1
Bin	(9)	0	1	11	1
Bin	(9)	1	0	176	1
Bin	(8)	0	1	21	1
Bin	(8)	1	0	186	1
Bin	(7)	0	1	41	1
Bin	(7)	1	0	206	1
Bin	(6)	0	1	205	1
Bin	(6)	1	0	865	1
Bin	(5)	0	1	443	1
Bin	(5)	1	0	1103	1
Bin	(4)	0	1	1578	1
Bin	(4)	1	0	3179	1
Bin	(3)	0	1	3184	1
Bin	(3)	1	0	4785	1
Bin	(2)	0	1	6633	1
Bin	(2)	1	0	8234	1
Bin	(1)	0	1	13003	1
Bin	(1)	1	0	14604	1
Bin	(0)	0	1	25973	1
Bin	(0)	1	0	27574	1

Signal:

READ_POINTER_INC_1

	Element	From	To	Count	Threshold
Bin	(11)	0	1	2	1
Bin	(11)	1	0	167	1
Bin	(10)	0	1	5	1
Bin	(10)	1	0	170	1
Bin	(9)	0	1	11	1
Bin	(9)	1	0	176	1
Bin	(8)	0	1	21	1
Bin	(8)	1	0	186	1
Bin	(7)	0	1	41	1
Bin	(7)	1	0	206	1
Bin	(6)	0	1	206	1
Bin	(6)	1	0	866	1
Bin	(5)	0	1	451	1
Bin	(5)	1	0	1111	1
Bin	(4)	0	1	1592	1
Bin	(4)	1	0	3193	1
Bin	(3)	0	1	3194	1
Bin	(3)	1	0	4795	1
Bin	(2)	0	1	6687	1
Bin	(2)	1	0	8288	1
Bin	(1)	0	1	13173	1
Bin	(1)	1	0	14774	1
Bin	(0)	0	1	27574	1
Bin	(0)	1	0	25973	1

Signal:

WRITE_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	5	1
Bin	(11)	1	0	170	1
Bin	(10)	0	1	11	1
Bin	(10)	1	0	176	1
Bin	(9)	0	1	23	1
Bin	(9)	1	0	188	1
Bin	(8)	0	1	45	1
Bin	(8)	1	0	210	1
Bin	(7)	0	1	89	1
Bin	(7)	1	0	254	1
Bin	(6)	0	1	311	1
Bin	(6)	1	0	971	1
Bin	(5)	0	1	669	1
Bin	(5)	1	0	1329	1
Bin	(4)	0	1	1971	1
Bin	(4)	1	0	3572	1
Bin	(3)	0	1	3777	1
Bin	(3)	1	0	5378	1
Bin	(2)	0	1	6171	1
Bin	(2)	1	0	7770	1
Bin	(1)	0	1	1881	1
Bin	(1)	1	0	3482	1
Bin	(0)	0	1	1735	1
Bin	(0)	1	0	3336	1

Signal:

WRITE_POINTER_RAW

	Element	From	To	Count	Threshold
Bin	(11)	0	1	6	1
Bin	(11)	1	0	171	1
Bin	(10)	0	1	12	1
Bin	(10)	1	0	177	1
Bin	(9)	0	1	25	1
Bin	(9)	1	0	190	1
Bin	(8)	0	1	48	1
Bin	(8)	1	0	213	1
Bin	(7)	0	1	94	1
Bin	(7)	1	0	259	1
Bin	(6)	0	1	354	1
Bin	(6)	1	0	1014	1
Bin	(5)	0	1	756	1
Bin	(5)	1	0	1416	1
Bin	(4)	0	1	4607	1
Bin	(4)	1	0	6208	1
Bin	(3)	0	1	11777	1
Bin	(3)	1	0	13378	1
Bin	(2)	0	1	26847	1
Bin	(2)	1	0	28446	1
Bin	(1)	0	1	49435	1
Bin	(1)	1	0	51036	1
Bin	(0)	0	1	99314	1
Bin	(0)	1	0	100915	1

Signal:

WRITE_POINTER_TS

	Element	From	To	Count	Threshold
Bin	(11)	0	1	5	1
Bin	(11)	1	0	170	1
Bin	(10)	0	1	11	1
Bin	(10)	1	0	176	1
Bin	(9)	0	1	23	1
Bin	(9)	1	0	188	1
Bin	(8)	0	1	45	1
Bin	(8)	1	0	210	1
Bin	(7)	0	1	89	1
Bin	(7)	1	0	254	1
Bin	(6)	0	1	297	1
Bin	(6)	1	0	957	1
Bin	(5)	0	1	653	1
Bin	(5)	1	0	1313	1
Bin	(4)	0	1	1888	1
Bin	(4)	1	0	3489	1
Bin	(3)	0	1	3616	1
Bin	(3)	1	0	5217	1
Bin	(2)	0	1	6203	1
Bin	(2)	1	0	7804	1
Bin	(1)	0	1	3532	1
Bin	(1)	1	0	5126	1
Bin	(0)	0	1	11595	1
Bin	(0)	1	0	13194	1

Signal:

RX_MEM_FREE_I

	Element	From	To	Count	Threshold
Bin	(12)	0	1	1239	1
Bin	(12)	1	0	1074	1
Bin	(11)	0	1	1076	1
Bin	(11)	1	0	1241	1
Bin	(10)	0	1	1083	1
Bin	(10)	1	0	1248	1
Bin	(9)	0	1	1097	1
Bin	(9)	1	0	1262	1
Bin	(8)	0	1	1125	1
Bin	(8)	1	0	1290	1
Bin	(7)	0	1	4532	1
Bin	(7)	1	0	4202	1
Bin	(6)	0	1	4159	1
Bin	(6)	1	0	4819	1
Bin	(5)	0	1	8826	1
Bin	(5)	1	0	8547	1
Bin	(4)	0	1	8414	1
Bin	(4)	1	0	10013	1
Bin	(3)	0	1	10005	1
Bin	(3)	1	0	11604	1
Bin	(2)	0	1	12209	1
Bin	(2)	1	0	13808	1
Bin	(1)	0	1	16073	1
Bin	(1)	1	0	17674	1
Bin	(0)	0	1	27447	1
Bin	(0)	1	0	29048	1

Signal:

DATA_OVERRUN_FLG

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	1632	1

Signal:

DATA_OVERRUN_I

	From	To	Count	Threshold
Bin	0	1	497	1
Bin	1	0	2098	1

Signal:

OVERRUN_CONDITION

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1644	1

Signal:

RX_EMPTY_I

	From	To	Count	Threshold
Bin	0	1	8999	1
Bin	1	0	9001	1

Signal:

IS_FREE_WORD

	From	To	Count	Threshold
Bin	0	1	1630	1
Bin	1	0	29	1

Signal:

FRAME_COUNT

	Element	From	To	Count	Threshold
Bin	(10)	0	1	4	1
Bin	(10)	1	0	169	1
Bin	(9)	0	1	5	1
Bin	(9)	1	0	170	1
Bin	(8)	0	1	10	1
Bin	(8)	1	0	175	1
Bin	(7)	0	1	21	1
Bin	(7)	1	0	186	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	208	1
Bin	(5)	0	1	98	1
Bin	(5)	1	0	758	1
Bin	(4)	0	1	195	1
Bin	(4)	1	0	855	1
Bin	(3)	0	1	404	1
Bin	(3)	1	0	2005	1
Bin	(2)	0	1	846	1
Bin	(2)	1	0	2447	1
Bin	(1)	0	1	2538	1
Bin	(1)	1	0	4139	1
Bin	(0)	0	1	11478	1
Bin	(0)	1	0	13077	1

Signal:

READ_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(4)	0	1	24636	1
Bin	(4)	1	0	22171	1
Bin	(3)	0	1	16203	1
Bin	(3)	1	0	22636	1
Bin	(2)	0	1	25203	1
Bin	(2)	1	0	20898	1
Bin	(1)	0	1	31474	1
Bin	(1)	1	0	36571	1
Bin	(0)	0	1	44200	1
Bin	(0)	1	0	39655	1

Signal:

READ_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(4)	0	1	289	1
Bin	(4)	1	0	1890	1
Bin	(3)	0	1	640	1
Bin	(3)	1	0	2241	1
Bin	(2)	0	1	5674	1
Bin	(2)	1	0	7275	1
Bin	(1)	0	1	11326	1
Bin	(1)	1	0	12927	1
Bin	(0)	0	1	24422	1
Bin	(0)	1	0	26023	1

Signal:

COMMIT_RX_FRAME

	From	To	Count	Threshold
Bin	0	1	13358	1
Bin	1	0	14959	1

Signal:

COMMIT_OVERRUN_ABORT

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	1642	1

Signal:

READ_INCREMENT

	From	To	Count	Threshold
Bin	0	1	51685	1
Bin	1	0	53286	1

Signal:

WRITE_RAW_OK

	From	To	Count	Threshold
Bin	0	1	112843	1
Bin	1	0	114444	1

Signal:

WRITE_RAW_INTENT

	From	To	Count	Threshold
Bin	0	1	112853	1
Bin	1	0	114454	1

Signal:

SELECT_TS_WPTR

	From	To	Count	Threshold
Bin	0	1	13062	1
Bin	1	0	14663	1

Signal:

COMMIT_INTENT

	From	To	Count	Threshold
Bin	0	1	13399	1
Bin	1	0	15000	1

Signal:

DATA_SELECTOR

	Element	From	To	Count	Threshold
Bin	(4)	0	1	13399	1
Bin	(4)	1	0	15000	1
Bin	(3)	0	1	13399	1
Bin	(3)	1	0	15000	1
Bin	(2)	0	1	26411	1
Bin	(2)	1	0	28012	1
Bin	(1)	0	1	26748	1
Bin	(1)	1	0	28349	1
Bin	(0)	0	1	26751	1
Bin	(0)	1	0	28352	1

Signal:

STORE_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	26411	1
Bin	1	0	28012	1

Signal:

INC_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	13062	1
Bin	1	0	14663	1

Signal:

RESET_OVERRUN_FLAG

	From	To	Count	Threshold
Bin	0	1	28337	1
Bin	1	0	26736	1

Signal:

READ_ATTEMPT

	From	To	Count	Threshold
Bin	0	1	51715	1
Bin	1	0	53338	1

Signal:

REC_ERF

	From	To	Count	Threshold
Bin	0	1	337	1
Bin	1	0	1938	1

Signal:

FRAME_FORM_W

	Element	From	To	Count	Threshold
Bin	(27)	0	1	90	1
Bin	(27)	1	0	410320	1
Bin	(26)	0	1	548	1
Bin	(26)	1	0	414069	1
Bin	(25)	0	1	1411	1
Bin	(25)	1	0	414836	1
Bin	(24)	0	1	232737	1
Bin	(24)	1	0	178707	1
Bin	(23)	0	1	12	1
Bin	(23)	1	0	414795	1
Bin	(22)	0	1	117	1
Bin	(22)	1	0	415976	1
Bin	(21)	0	1	79	1
Bin	(21)	1	0	415318	1
Bin	(20)	0	1	34	1
Bin	(20)	1	0	416213	1
Bin	(19)	0	1	5	1
Bin	(19)	1	0	414044	1
Bin	(18)	0	1	206	1
Bin	(18)	1	0	415138	1
Bin	(17)	0	1	149	1
Bin	(17)	1	0	414725	1
Bin	(16)	0	1	272	1
Bin	(16)	1	0	415543	1
Bin	(15)	0	1	56271	1
Bin	(15)	1	0	121224	1
Bin	(14)	0	1	6677	1
Bin	(14)	1	0	19445	1
Bin	(13)	0	1	69378	1
Bin	(13)	1	0	153730	1
Bin	(12)	0	1	153478	1
Bin	(12)	1	0	68273	1
Bin	(11)	0	1	107396	1
Bin	(11)	1	0	45995	1
Bin	(10)	0	1	8326	1
Bin	(10)	1	0	401517	1
Bin	(9)	0	1	73474	1
Bin	(9)	1	0	336369	1
Bin	(8)	0	1	2632	1
Bin	(8)	1	0	408812	1
Bin	(7)	0	1	171150	1
Bin	(7)	1	0	235491	1
Bin	(6)	0	1	85662	1
Bin	(6)	1	0	324181	1
Bin	(5)	0	1	76945	1
Bin	(5)	1	0	336100	1
Bin	(4)	0	1	337	1
Bin	(4)	1	0	414309	1
Bin	(3)	0	1	70489	1
Bin	(3)	1	0	158803	1
Bin	(2)	0	1	75457	1
Bin	(2)	1	0	167014	1
Bin	(1)	0	1	74201	1
Bin	(1)	1	0	166217	1
Bin	(0)	0	1	94779	1
Bin	(0)	1	0	201297	1

Signal:

TIMESTAMP_CAPTURE

	Element	From	To	Count	Threshold
Bin	(63)	0	1	5	1
Bin	(63)	1	0	15707	1
Bin	(62)	0	1	59	1
Bin	(62)	1	0	15757	1
Bin	(61)	0	1	66	1
Bin	(61)	1	0	15762	1
Bin	(60)	0	1	50	1
Bin	(60)	1	0	15744	1
Bin	(59)	0	1	71	1
Bin	(59)	1	0	15767	1
Bin	(58)	0	1	68	1
Bin	(58)	1	0	15762	1
Bin	(57)	0	1	57	1
Bin	(57)	1	0	15757	1
Bin	(56)	0	1	74	1
Bin	(56)	1	0	15768	1
Bin	(55)	0	1	61	1
Bin	(55)	1	0	15757	1
Bin	(54)	0	1	58	1
Bin	(54)	1	0	15756	1
Bin	(53)	0	1	59	1
Bin	(53)	1	0	15757	1
Bin	(52)	0	1	52	1
Bin	(52)	1	0	15750	1
Bin	(51)	0	1	71	1
Bin	(51)	1	0	15767	1
Bin	(50)	0	1	62	1
Bin	(50)	1	0	15756	1
Bin	(49)	0	1	62	1
Bin	(49)	1	0	15762	1
Bin	(48)	0	1	67	1
Bin	(48)	1	0	15765	1
Bin	(47)	0	1	70	1
Bin	(47)	1	0	15766	1
Bin	(46)	0	1	69	1
Bin	(46)	1	0	15763	1
Bin	(45)	0	1	60	1
Bin	(45)	1	0	15756	1
Bin	(44)	0	1	66	1
Bin	(44)	1	0	15762	1
Bin	(43)	0	1	64	1
Bin	(43)	1	0	15762	1
Bin	(42)	0	1	74	1
Bin	(42)	1	0	15772	1
Bin	(41)	0	1	70	1
Bin	(41)	1	0	15770	1
Bin	(40)	0	1	71	1
Bin	(40)	1	0	15763	1
Bin	(39)	0	1	74	1
Bin	(39)	1	0	15768	1
Bin	(38)	0	1	61	1
Bin	(38)	1	0	15759	1
Bin	(37)	0	1	68	1
Bin	(37)	1	0	15764	1
Bin	(36)	0	1	63	1
Bin	(36)	1	0	15763	1
Bin	(35)	0	1	85	1
Bin	(35)	1	0	15779	1
Bin	(34)	0	1	48	1
Bin	(34)	1	0	15746	1
Bin	(33)	0	1	59	1
Bin	(33)	1	0	15757	1
Bin	(32)	0	1	57	1
Bin	(32)	1	0	15755	1
Bin	(31)	0	1	51	1
Bin	(31)	1	0	1652	1
Bin	(30)	0	1	57	1
Bin	(30)	1	0	1658	1
Bin	(29)	0	1	58	1
Bin	(29)	1	0	1659	1
Bin	(28)	0	1	39	1
Bin	(28)	1	0	1640	1
Bin	(27)	0	1	63	1
Bin	(27)	1	0	1664	1
Bin	(26)	0	1	58	1
Bin	(26)	1	0	1659	1
Bin	(25)	0	1	57	1
Bin	(25)	1	0	1658	1
Bin	(24)	0	1	64	1
Bin	(24)	1	0	1665	1
Bin	(23)	0	1	55	1
Bin	(23)	1	0	1656	1
Bin	(22)	0	1	57	1
Bin	(22)	1	0	1658	1
Bin	(21)	0	1	64	1
Bin	(21)	1	0	1665	1
Bin	(20)	0	1	68	1
Bin	(20)	1	0	1669	1
Bin	(19)	0	1	182	1
Bin	(19)	1	0	1783	1
Bin	(18)	0	1	243	1
Bin	(18)	1	0	1844	1
Bin	(17)	0	1	510	1
Bin	(17)	1	0	2111	1
Bin	(16)	0	1	836	1
Bin	(16)	1	0	2437	1
Bin	(15)	0	1	1021	1
Bin	(15)	1	0	2622	1
Bin	(14)	0	1	1423	1
Bin	(14)	1	0	3023	1
Bin	(13)	0	1	1735	1
Bin	(13)	1	0	3336	1
Bin	(12)	0	1	2251	1
Bin	(12)	1	0	3852	1
Bin	(11)	0	1	2939	1
Bin	(11)	1	0	4539	1
Bin	(10)	0	1	3790	1
Bin	(10)	1	0	5391	1
Bin	(9)	0	1	4526	1
Bin	(9)	1	0	6125	1
Bin	(8)	0	1	3205	1
Bin	(8)	1	0	4804	1
Bin	(7)	0	1	3958	1
Bin	(7)	1	0	5557	1
Bin	(6)	0	1	3736	1
Bin	(6)	1	0	5336	1
Bin	(5)	0	1	3376	1
Bin	(5)	1	0	4976	1
Bin	(4)	0	1	3591	1
Bin	(4)	1	0	5192	1
Bin	(3)	0	1	3242	1
Bin	(3)	1	0	4842	1
Bin	(2)	0	1	3984	1
Bin	(2)	1	0	5584	1
Bin	(1)	0	1	3223	1
Bin	(1)	1	0	4823	1
Bin	(0)	0	1	4956	1
Bin	(0)	1	0	6557	1

Signal:

TIMESTAMP_CAPTURE_CE

	From	To	Count	Threshold
Bin	0	1	13404	1
Bin	1	0	15005	1

Signal:

RXB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	125864	1
Bin	1	0	127465	1

Signal:

RXB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold
Bin	(11)	0	1	16	1
Bin	(11)	1	0	181	1
Bin	(10)	0	1	33	1
Bin	(10)	1	0	198	1
Bin	(9)	0	1	68	1
Bin	(9)	1	0	233	1
Bin	(8)	0	1	135	1
Bin	(8)	1	0	300	1
Bin	(7)	0	1	266	1
Bin	(7)	1	0	431	1
Bin	(6)	0	1	859	1
Bin	(6)	1	0	1519	1
Bin	(5)	0	1	1814	1
Bin	(5)	1	0	2474	1
Bin	(4)	0	1	7463	1
Bin	(4)	1	0	9064	1
Bin	(3)	0	1	17395	1
Bin	(3)	1	0	18996	1
Bin	(2)	0	1	38140	1
Bin	(2)	1	0	39739	1
Bin	(1)	0	1	60987	1
Bin	(1)	1	0	62588	1
Bin	(0)	0	1	112376	1
Bin	(0)	1	0	113977	1

Signal:

RXB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold
Bin	(31)	0	1	117043	1
Bin	(31)	1	0	118644	1
Bin	(30)	0	1	118596	1
Bin	(30)	1	0	120197	1
Bin	(29)	0	1	123131	1
Bin	(29)	1	0	124732	1
Bin	(28)	0	1	141936	1
Bin	(28)	1	0	143537	1
Bin	(27)	0	1	136510	1
Bin	(27)	1	0	138111	1
Bin	(26)	0	1	148456	1
Bin	(26)	1	0	150057	1
Bin	(25)	0	1	140566	1
Bin	(25)	1	0	142167	1
Bin	(24)	0	1	163384	1
Bin	(24)	1	0	164985	1
Bin	(23)	0	1	138824	1
Bin	(23)	1	0	140425	1
Bin	(22)	0	1	148674	1
Bin	(22)	1	0	150275	1
Bin	(21)	0	1	143263	1
Bin	(21)	1	0	144864	1
Bin	(20)	0	1	152239	1
Bin	(20)	1	0	153840	1
Bin	(19)	0	1	150200	1
Bin	(19)	1	0	151801	1
Bin	(18)	0	1	163472	1
Bin	(18)	1	0	165073	1
Bin	(17)	0	1	149647	1
Bin	(17)	1	0	151248	1
Bin	(16)	0	1	153295	1
Bin	(16)	1	0	154896	1
Bin	(15)	0	1	192751	1
Bin	(15)	1	0	194352	1
Bin	(14)	0	1	188105	1
Bin	(14)	1	0	189706	1
Bin	(13)	0	1	184943	1
Bin	(13)	1	0	186544	1
Bin	(12)	0	1	199162	1
Bin	(12)	1	0	200763	1
Bin	(11)	0	1	196248	1
Bin	(11)	1	0	197849	1
Bin	(10)	0	1	178493	1
Bin	(10)	1	0	180094	1
Bin	(9)	0	1	183273	1
Bin	(9)	1	0	184874	1
Bin	(8)	0	1	175224	1
Bin	(8)	1	0	176825	1
Bin	(7)	0	1	204849	1
Bin	(7)	1	0	206450	1
Bin	(6)	0	1	195083	1
Bin	(6)	1	0	196684	1
Bin	(5)	0	1	188347	1
Bin	(5)	1	0	189948	1
Bin	(4)	0	1	185246	1
Bin	(4)	1	0	186847	1
Bin	(3)	0	1	197633	1
Bin	(3)	1	0	199234	1
Bin	(2)	0	1	202170	1
Bin	(2)	1	0	203771	1
Bin	(1)	0	1	204135	1
Bin	(1)	1	0	205736	1
Bin	(0)	0	1	206441	1
Bin	(0)	1	0	208042	1

Signal:

RXB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold
Bin	(11)	0	1	5	1
Bin	(11)	1	0	170	1
Bin	(10)	0	1	13	1
Bin	(10)	1	0	178	1
Bin	(9)	0	1	29	1
Bin	(9)	1	0	194	1
Bin	(8)	0	1	60	1
Bin	(8)	1	0	225	1
Bin	(7)	0	1	119	1
Bin	(7)	1	0	284	1
Bin	(6)	0	1	546	1
Bin	(6)	1	0	1206	1
Bin	(5)	0	1	1196	1
Bin	(5)	1	0	1856	1
Bin	(4)	0	1	4206	1
Bin	(4)	1	0	5807	1
Bin	(3)	0	1	8749	1
Bin	(3)	1	0	10350	1
Bin	(2)	0	1	18276	1
Bin	(2)	1	0	19877	1
Bin	(1)	0	1	36474	1
Bin	(1)	1	0	38075	1
Bin	(0)	0	1	70689	1
Bin	(0)	1	0	72290	1

Signal:

RXB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	25817	1
Bin	(31)	1	0	24122	1
Bin	(30)	0	1	16353	1
Bin	(30)	1	0	23732	1
Bin	(29)	0	1	20855	1
Bin	(29)	1	0	19263	1
Bin	(28)	0	1	24892	1
Bin	(28)	1	0	33563	1
Bin	(27)	0	1	24358	1
Bin	(27)	1	0	24035	1
Bin	(26)	0	1	25316	1
Bin	(26)	1	0	34114	1
Bin	(25)	0	1	30097	1
Bin	(25)	1	0	29888	1
Bin	(24)	0	1	27611	1
Bin	(24)	1	0	30303	1
Bin	(23)	0	1	29908	1
Bin	(23)	1	0	29705	1
Bin	(22)	0	1	20669	1
Bin	(22)	1	0	29159	1
Bin	(21)	0	1	24882	1
Bin	(21)	1	0	24879	1
Bin	(20)	0	1	24601	1
Bin	(20)	1	0	33463	1
Bin	(19)	0	1	26874	1
Bin	(19)	1	0	27301	1
Bin	(18)	0	1	28053	1
Bin	(18)	1	0	37160	1
Bin	(17)	0	1	30661	1
Bin	(17)	1	0	29728	1
Bin	(16)	0	1	21629	1
Bin	(16)	1	0	29715	1
Bin	(15)	0	1	30902	1
Bin	(15)	1	0	29377	1
Bin	(14)	0	1	22740	1
Bin	(14)	1	0	30069	1
Bin	(13)	0	1	30781	1
Bin	(13)	1	0	26835	1
Bin	(12)	0	1	32702	1
Bin	(12)	1	0	37840	1
Bin	(11)	0	1	33991	1
Bin	(11)	1	0	29427	1
Bin	(10)	0	1	28019	1
Bin	(10)	1	0	34660	1
Bin	(9)	0	1	34142	1
Bin	(9)	1	0	31297	1
Bin	(8)	0	1	22846	1
Bin	(8)	1	0	29704	1
Bin	(7)	0	1	34701	1
Bin	(7)	1	0	31230	1
Bin	(6)	0	1	24368	1
Bin	(6)	1	0	30098	1
Bin	(5)	0	1	28791	1
Bin	(5)	1	0	26127	1
Bin	(4)	0	1	27674	1
Bin	(4)	1	0	34417	1
Bin	(3)	0	1	28523	1
Bin	(3)	1	0	25959	1
Bin	(2)	0	1	29059	1
Bin	(2)	1	0	35349	1
Bin	(1)	0	1	34291	1
Bin	(1)	1	0	31545	1
Bin	(0)	0	1	25368	1
Bin	(0)	1	0	31095	1

Signal:

RX_BUF_RES_N_D

	From	To	Count	Threshold
Bin	0	1	8544	1
Bin	1	0	8532	1

Signal:

RX_BUF_RES_N_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	8439	1
Bin	1	0	8428	1

Signal:

RX_BUF_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	178070	1
Bin	1	0	179671	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	14749136	1
Bin	1	0	14750737	1

Signal:

RX_PARITY_MISMATCH_COMB

	From	To	Count	Threshold
Bin	0	1	18805	1
Bin	1	0	19819	1

Uncovered expressions:

Excluded expressions:

"and" expression on line 552:

 read_pointer = write_pointer_raw and frame_count > 0 
 <-------------LHS-------------->     <-----RHS----->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"and" expression on line 621:

 (rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1') 
  <-----------LHS----------->       <-----RHS------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"and" expression on line 709:

 (read_increment = '1') and (read_counter_q = "00001") 
  <-------LHS-------->       <---------RHS---------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"or" expression on line 436:

 mr_command_rrb = '1' or res_n = '0' 
 <-------LHS-------->    <---RHS--->

	LHS	RHS	Count	Threshold
Bin	False	False	14220	1
Bin	False	True	8072	1
Bin	True	False	460	1

"=" expression on line 436:

mr_command_rrb = '1'

	Evaluated to	Count	Threshold
Bin	False	22292	1
Bin	True	460	1

"=" expression on line 436:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	14680	1
Bin	True	8072	1

"=" expression on line 528:

mr_mode_rxbam = RXBAM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	5352	1
Bin	True	159641	1

"and" expression on line 532:

 read_attempt = '1' and rx_empty_i = '0' 
 <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	100034	1
Bin	True	False	6999	1
Bin	True	True	51685	1

"=" expression on line 532:

read_attempt = '1'

	Evaluated to	Count	Threshold
Bin	False	117707	1
Bin	True	58684	1

"=" expression on line 532:

rx_empty_i = '0'

	Evaluated to	Count	Threshold
Bin	False	24672	1
Bin	True	151719	1

"and" expression on lines 540 to 541:

 write_raw_intent = '1' and overrun_condition = '0' and data_overrun_i = '0' 
 <----------------------LHS----------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	114941	1
Bin	True	False	10	1
Bin	True	True	112843	1

"and" expression on line 540:

 write_raw_intent = '1' and overrun_condition = '0' 
 <--------LHS--------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	117012	1
Bin	True	False	80	1
Bin	True	True	112853	1

"=" expression on line 540:

write_raw_intent = '1'

	Evaluated to	Count	Threshold
Bin	False	118656	1
Bin	True	112933	1

"=" expression on line 540:

overrun_condition = '0'

	Evaluated to	Count	Threshold
Bin	False	1724	1
Bin	True	229865	1

"=" expression on line 541:

data_overrun_i = '0'

	Evaluated to	Count	Threshold
Bin	False	3805	1
Bin	True	227784	1

"and" expression on line 552:

 read_pointer = write_pointer_raw and frame_count > 0 
 <-------------LHS-------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	True	False	25099	1
Bin	True	True	49	1

"and" expression on line 563:

 write_raw_intent = '1' and is_free_word = '0' 
 <--------LHS--------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	67	1
Bin	True	False	112815	1
Bin	True	True	43	1

"=" expression on line 563:

write_raw_intent = '1'

	Evaluated to	Count	Threshold
Bin	False	116107	1
Bin	True	112858	1

"=" expression on line 563:

is_free_word = '0'

	Evaluated to	Count	Threshold
Bin	False	228855	1
Bin	True	110	1

"=" expression on line 573:

rx_empty_i = '0'

	Evaluated to	Count	Threshold
Bin	False	75379	1
Bin	True	50990	1

"or" expression on line 620:

 rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED 
 <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	176323	1
Bin	False	True	280	1
Bin	True	False	27311	1

"=" expression on line 620:

rec_is_rtr = RTR_FRAME

	Evaluated to	Count	Threshold
Bin	False	176603	1
Bin	True	27368	1

"=" expression on line 620:

rec_erf = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	203634	1
Bin	True	337	1

"and" expression on line 621:

 (rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1') 
  <-----------LHS----------->       <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	True	False	75615	1
Bin	True	True	6350	1

"=" expression on line 621:

rec_frame_type = NORMAL_CAN

	Evaluated to	Count	Threshold
Bin	False	94358	1
Bin	True	81965	1

"=" expression on line 621:

rec_dlc(3) = '1'

	Evaluated to	Count	Threshold
Bin	False	75615	1
Bin	True	6350	1

"=" expression on line 625:

rec_erf = '1'

	Evaluated to	Count	Threshold
Bin	False	13976	1
Bin	True	337	1

"=" expression on line 629:

rec_erf = '1'

	Evaluated to	Count	Threshold
Bin	False	9266	1
Bin	True	337	1

"=" expression on line 633:

rec_erf = '1'

	Evaluated to	Count	Threshold
Bin	False	5720	1
Bin	True	337	1

"=" expression on line 638:

rec_lbpf = LBPF_LOOPBACK

	Evaluated to	Count	Threshold
Bin	False	17135	1
Bin	True	350	1

"and" expression on line 648:

 mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1' 
 <------------LHS------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	10	1
Bin	True	False	238902	1
Bin	True	True	13052	1

"=" expression on line 648:

mr_rx_settings_rtsop = RTS_END

	Evaluated to	Count	Threshold
Bin	False	3257	1
Bin	True	251954	1

"=" expression on line 648:

rec_valid_f = '1'

	Evaluated to	Count	Threshold
Bin	False	242149	1
Bin	True	13062	1

"and" expression on line 650:

 mr_rx_settings_rtsop = RTS_BEG and sof_pulse = '1' 
 <------------LHS------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	80671	1
Bin	True	False	40	1
Bin	True	True	15	1

"=" expression on line 650:

mr_rx_settings_rtsop = RTS_BEG

	Evaluated to	Count	Threshold
Bin	False	242104	1
Bin	True	55	1

"=" expression on line 650:

sof_pulse = '1'

	Evaluated to	Count	Threshold
Bin	False	161473	1
Bin	True	80686	1

"and" expression on line 652:

 mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1' 
 <-----------LHS----------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	30961	1
Bin	True	False	1602	1
Bin	True	True	337	1

"=" expression on line 652:

mr_mode_erfm = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	240205	1
Bin	True	1939	1

"=" expression on line 652:

rec_abort_f = '1'

	Evaluated to	Count	Threshold
Bin	False	210846	1
Bin	True	31298	1

"=" expression on line 658:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 661:

timestamp_capture_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543778279	1
Bin	True	13399	1

"=" expression on line 685:

rx_buf_res_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087580000	1
Bin	True	2438917	1

"=" expression on line 690:

read_increment = '1'

	Evaluated to	Count	Threshold
Bin	False	543733154	1
Bin	True	51685	1

"=" expression on line 704:

rx_buf_res_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087580000	1
Bin	True	2438917	1

"and" expression on line 709:

 (read_increment = '1') and (read_counter_q = "00001") 
  <-------LHS-------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	True	False	42351	1
Bin	True	True	9334	1

"=" expression on line 709:

read_increment = '1'

	Evaluated to	Count	Threshold
Bin	False	543733154	1
Bin	True	51685	1

"=" expression on line 710:

commit_rx_frame = '0'

	Evaluated to	Count	Threshold
Bin	False	5	1
Bin	True	9329	1

"=" expression on line 715:

commit_rx_frame = '1'

	Evaluated to	Count	Threshold
Bin	False	543762152	1
Bin	True	13353	1

"=" expression on line 729:

rx_buf_res_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087580000	1
Bin	True	2438917	1

"=" expression on line 735:

commit_intent = '1'

	Evaluated to	Count	Threshold
Bin	False	543771440	1
Bin	True	13399	1

"=" expression on line 736:

data_overrun_i = '0'

	Evaluated to	Count	Threshold
Bin	False	41	1
Bin	True	13358	1

"=" expression on line 757:

rx_buf_res_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087580000	1
Bin	True	2438917	1

"=" expression on line 762:

mr_command_cdo = '1'

	Evaluated to	Count	Threshold
Bin	False	543784819	1
Bin	True	20	1

"=" expression on line 764:

overrun_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	543784680	1
Bin	True	139	1

"=" expression on line 789:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"or" expression on line 792:

 overrun_condition = '1' or mr_command_rrb = '1' 
 <---------LHS--------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	543791079	1
Bin	False	True	460	1
Bin	True	False	139	1

"=" expression on line 792:

overrun_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	543791539	1
Bin	True	139	1

"=" expression on line 792:

mr_command_rrb = '1'

	Evaluated to	Count	Threshold
Bin	False	543791218	1
Bin	True	460	1

"=" expression on line 794:

reset_overrun_flag = '1'

	Evaluated to	Count	Threshold
Bin	False	108063966	1
Bin	True	435727113	1

"or" expression on line 808:

 rxb_port_a_write = '1' or read_attempt = '1' 
 <--------LHS--------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	236759	1
Bin	False	True	51642	1
Bin	True	False	126059	1

"=" expression on line 808:

rxb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	288401	1
Bin	True	126216	1

"=" expression on line 808:

read_attempt = '1'

	Evaluated to	Count	Threshold
Bin	False	362818	1
Bin	True	51799	1

"=" expression on line 810:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	236111	1
Bin	True	648	1

"or" expression on lines 864 to 865:

 write_raw_OK = '1' or (select_ts_wptr = '1' and data_overrun_i = '0') 
 <------LHS------->     <--------------------RHS-------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	131743	1
Bin	False	True	13021	1
Bin	True	False	112843	1

"=" expression on line 864:

write_raw_OK = '1'

	Evaluated to	Count	Threshold
Bin	False	144764	1
Bin	True	112843	1

"and" expression on line 865:

 select_ts_wptr = '1' and data_overrun_i = '0' 
 <-------LHS-------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	240805	1
Bin	True	False	41	1
Bin	True	True	13021	1

"=" expression on line 865:

select_ts_wptr = '1'

	Evaluated to	Count	Threshold
Bin	False	244545	1
Bin	True	13062	1

"=" expression on line 865:

data_overrun_i = '0'

	Evaluated to	Count	Threshold
Bin	False	3781	1
Bin	True	253826	1

"=" expression on line 873:

select_ts_wptr = '1'

	Evaluated to	Count	Threshold
Bin	False	225590	1
Bin	True	26124	1

"=" expression on line 882:

read_increment = '1'

	Evaluated to	Count	Threshold
Bin	False	61324	1
Bin	True	148086	1

"=" expression on line 901:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"and" expression on line 904:

 read_attempt = '1' and rx_parity_mismatch_comb = '1' and mr_settings_pchke = '1' 
 <-----------------------LHS------------------------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	1136059	1
Bin	True	False	35	1
Bin	True	True	9	1

"and" expression on line 904:

 read_attempt = '1' and rx_parity_mismatch_comb = '1' 
 <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	44317272	1
Bin	True	False	51661	1
Bin	True	True	44	1

"=" expression on line 904:

read_attempt = '1'

	Evaluated to	Count	Threshold
Bin	False	543739973	1
Bin	True	51705	1

"=" expression on line 904:

rx_parity_mismatch_comb = '1'

	Evaluated to	Count	Threshold
Bin	False	499474362	1
Bin	True	44317316	1

"=" expression on line 904:

mr_settings_pchke = '1'

	Evaluated to	Count	Threshold
Bin	False	542655610	1
Bin	True	1136068	1

"=" expression on line 907:

mr_command_crxpe = '1'

	Evaluated to	Count	Threshold
Bin	False	543791629	1
Bin	True	40	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

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