NVC code coverage report

NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)
SYNC_READ_GEN	100.0 % (2/2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST	100.0 % (1/1)	N.A.	100.0 % (1578/1578)	N.A.	N.A.	N.A.	100.0 % (1579/1579)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

191: int_read_data <= ram_memory(to_integer(unsigned(addr_B)));
Count: 32957
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	327637	1
Bin	1	0	327802	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	723	1
Bin	1	0	723	1

Port:

ADDR_A(4)

	From	To	Count	Threshold
Bin	0	1	101815	1
Bin	1	0	4952782	1

Port:

ADDR_A(3)

	From	To	Count	Threshold
Bin	0	1	128238	1
Bin	1	0	4926349	1

Port:

ADDR_A(2)

	From	To	Count	Threshold
Bin	0	1	109945	1
Bin	1	0	4944788	1

Port:

ADDR_A(1)

	From	To	Count	Threshold
Bin	0	1	4814575	1
Bin	1	0	240456	1

Port:

ADDR_A(0)

	From	To	Count	Threshold
Bin	0	1	3622573	1
Bin	1	0	1433078	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	11472	1
Bin	1	0	11676	1

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	16686	1
Bin	1	0	317904	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	18736	1
Bin	1	0	315848	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	16346	1
Bin	1	0	318240	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	24929	1
Bin	1	0	309671	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	19042	1
Bin	1	0	315558	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	21389	1
Bin	1	0	313223	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	26306	1
Bin	1	0	308306	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	21225	1
Bin	1	0	313383	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	20292	1
Bin	1	0	314306	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	23796	1
Bin	1	0	310814	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	22532	1
Bin	1	0	312060	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	20878	1
Bin	1	0	313726	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	34817	1
Bin	1	0	299793	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	41558	1
Bin	1	0	293053	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	38797	1
Bin	1	0	295829	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	83591	1
Bin	1	0	250999	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	18388	1
Bin	1	0	316216	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	21806	1
Bin	1	0	312796	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	19088	1
Bin	1	0	315522	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	22218	1
Bin	1	0	312382	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	40264	1
Bin	1	0	294340	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	41589	1
Bin	1	0	293013	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	49596	1
Bin	1	0	285002	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	50759	1
Bin	1	0	283845	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	44515	1
Bin	1	0	290085	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	42466	1
Bin	1	0	292154	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	44871	1
Bin	1	0	289735	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	48989	1
Bin	1	0	285591	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	52090	1
Bin	1	0	282510	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	54942	1
Bin	1	0	279656	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	94865	1
Bin	1	0	239738	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	81917	1
Bin	1	0	252713	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	5053365	1
Bin	1	0	7925	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	5053445	1
Bin	1	0	7845	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	5039204	1
Bin	1	0	22086	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	5039488	1
Bin	1	0	21802	1

Port:

ADDR_B(4)

	From	To	Count	Threshold
Bin	0	1	3249	1
Bin	1	0	3414	1

Port:

ADDR_B(3)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	329	1

Port:

ADDR_B(2)

	From	To	Count	Threshold
Bin	0	1	5050	1
Bin	1	0	5215	1

Port:

ADDR_B(1)

	From	To	Count	Threshold
Bin	0	1	4017	1
Bin	1	0	4017	1

Port:

ADDR_B(0)

	From	To	Count	Threshold
Bin	0	1	11151	1
Bin	1	0	11316	1

Port:

DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	382	1

Port:

DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	331	1
Bin	1	0	486	1

Port:

DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	303	1
Bin	1	0	458	1

Port:

DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	599	1
Bin	1	0	748	1

Port:

DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	775	1
Bin	1	0	925	1

Port:

DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	786	1
Bin	1	0	936	1

Port:

DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	749	1
Bin	1	0	900	1

Port:

DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	950	1

Port:

DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	925	1
Bin	1	0	1072	1

Port:

DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	925	1
Bin	1	0	1075	1

Port:

DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	802	1
Bin	1	0	951	1

Port:

DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	732	1
Bin	1	0	884	1

Port:

DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	905	1
Bin	1	0	1056	1

Port:

DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	765	1
Bin	1	0	915	1

Port:

DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	506	1
Bin	1	0	660	1

Port:

DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	545	1
Bin	1	0	700	1

Port:

DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	513	1
Bin	1	0	667	1

Port:

DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	656	1
Bin	1	0	809	1

Port:

DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	653	1
Bin	1	0	806	1

Port:

DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	666	1

Port:

DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	576	1
Bin	1	0	729	1

Port:

DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	479	1
Bin	1	0	633	1

Port:

DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	1027	1
Bin	1	0	1175	1

Port:

DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	716	1
Bin	1	0	870	1

Port:

DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	1322	1
Bin	1	0	1467	1

Port:

DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	998	1
Bin	1	0	1144	1

Port:

DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	936	1
Bin	1	0	1086	1

Port:

DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	824	1

Port:

DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	701	1
Bin	1	0	851	1

Port:

DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	945	1
Bin	1	0	1093	1

Port:

DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	882	1
Bin	1	0	1032	1

Port:

DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	1119	1
Bin	1	0	1264	1

Signal:

RAM_MEMORY(0)(31)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(30)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4051	1

Signal:

RAM_MEMORY(0)(29)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(28)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(27)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	4010	1

Signal:

RAM_MEMORY(0)(26)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4051	1

Signal:

RAM_MEMORY(0)(25)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(24)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	4030	1

Signal:

RAM_MEMORY(0)(23)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(22)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4051	1

Signal:

RAM_MEMORY(0)(21)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4030	1

Signal:

RAM_MEMORY(0)(20)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4031	1

Signal:

RAM_MEMORY(0)(19)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4031	1

Signal:

RAM_MEMORY(0)(18)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(17)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	4031	1

Signal:

RAM_MEMORY(0)(16)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	4030	1

Signal:

RAM_MEMORY(0)(15)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	3606	1

Signal:

RAM_MEMORY(0)(14)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	3625	1

Signal:

RAM_MEMORY(0)(13)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	3605	1

Signal:

RAM_MEMORY(0)(12)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3606	1

Signal:

RAM_MEMORY(0)(11)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	3605	1

Signal:

RAM_MEMORY(0)(10)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3606	1

Signal:

RAM_MEMORY(0)(9)

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	3855	1

Signal:

RAM_MEMORY(0)(8)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3646	1

Signal:

RAM_MEMORY(0)(7)

	From	To	Count	Threshold
Bin	0	1	291	1
Bin	1	0	3474	1

Signal:

RAM_MEMORY(0)(6)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	3444	1

Signal:

RAM_MEMORY(0)(5)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	3407	1

Signal:

RAM_MEMORY(0)(4)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3324	1

Signal:

RAM_MEMORY(0)(3)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	3417	1

Signal:

RAM_MEMORY(0)(2)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	3451	1

Signal:

RAM_MEMORY(0)(1)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	3384	1

Signal:

RAM_MEMORY(0)(0)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	3433	1

Signal:

RAM_MEMORY(1)(31)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3195	1

Signal:

RAM_MEMORY(1)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3214	1

Signal:

RAM_MEMORY(1)(29)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3214	1

Signal:

RAM_MEMORY(1)(28)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	3333	1

Signal:

RAM_MEMORY(1)(27)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	3367	1

Signal:

RAM_MEMORY(1)(26)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	3336	1

Signal:

RAM_MEMORY(1)(25)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	3352	1

Signal:

RAM_MEMORY(1)(24)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	3338	1

Signal:

RAM_MEMORY(1)(23)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	3354	1

Signal:

RAM_MEMORY(1)(22)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	3332	1

Signal:

RAM_MEMORY(1)(21)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	3342	1

Signal:

RAM_MEMORY(1)(20)

	From	To	Count	Threshold
Bin	0	1	278	1
Bin	1	0	3379	1

Signal:

RAM_MEMORY(1)(19)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	3340	1

Signal:

RAM_MEMORY(1)(18)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	3366	1

Signal:

RAM_MEMORY(1)(17)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	3269	1

Signal:

RAM_MEMORY(1)(16)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	3247	1

Signal:

RAM_MEMORY(1)(15)

	From	To	Count	Threshold
Bin	0	1	157	1
Bin	1	0	3623	1

Signal:

RAM_MEMORY(1)(14)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	3578	1

Signal:

RAM_MEMORY(1)(13)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	3604	1

Signal:

RAM_MEMORY(1)(12)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	3630	1

Signal:

RAM_MEMORY(1)(11)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	3541	1

Signal:

RAM_MEMORY(1)(10)

	From	To	Count	Threshold
Bin	0	1	142	1
Bin	1	0	3597	1

Signal:

RAM_MEMORY(1)(9)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	3581	1

Signal:

RAM_MEMORY(1)(8)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	3618	1

Signal:

RAM_MEMORY(1)(7)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	3613	1

Signal:

RAM_MEMORY(1)(6)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	3606	1

Signal:

RAM_MEMORY(1)(5)

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	3621	1

Signal:

RAM_MEMORY(1)(4)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	3629	1

Signal:

RAM_MEMORY(1)(3)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	3585	1

Signal:

RAM_MEMORY(1)(2)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	3578	1

Signal:

RAM_MEMORY(1)(1)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	3599	1

Signal:

RAM_MEMORY(1)(0)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	3566	1

Signal:

RAM_MEMORY(2)(31)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3678	1

Signal:

RAM_MEMORY(2)(30)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3678	1

Signal:

RAM_MEMORY(2)(29)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	3685	1

Signal:

RAM_MEMORY(2)(28)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3689	1

Signal:

RAM_MEMORY(2)(27)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	3678	1

Signal:

RAM_MEMORY(2)(26)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3678	1

Signal:

RAM_MEMORY(2)(25)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3660	1

Signal:

RAM_MEMORY(2)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3646	1

Signal:

RAM_MEMORY(2)(23)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3679	1

Signal:

RAM_MEMORY(2)(22)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3661	1

Signal:

RAM_MEMORY(2)(21)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3679	1

Signal:

RAM_MEMORY(2)(20)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3675	1

Signal:

RAM_MEMORY(2)(19)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	3717	1

Signal:

RAM_MEMORY(2)(18)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3693	1

Signal:

RAM_MEMORY(2)(17)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3679	1

Signal:

RAM_MEMORY(2)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3661	1

Signal:

RAM_MEMORY(2)(15)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3692	1

Signal:

RAM_MEMORY(2)(14)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3692	1

Signal:

RAM_MEMORY(2)(13)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3714	1

Signal:

RAM_MEMORY(2)(12)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3692	1

Signal:

RAM_MEMORY(2)(11)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3706	1

Signal:

RAM_MEMORY(2)(10)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3688	1

Signal:

RAM_MEMORY(2)(9)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3706	1

Signal:

RAM_MEMORY(2)(8)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3710	1

Signal:

RAM_MEMORY(2)(7)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3613	1

Signal:

RAM_MEMORY(2)(6)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	3630	1

Signal:

RAM_MEMORY(2)(5)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3613	1

Signal:

RAM_MEMORY(2)(4)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3609	1

Signal:

RAM_MEMORY(2)(3)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	3685	1

Signal:

RAM_MEMORY(2)(2)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3631	1

Signal:

RAM_MEMORY(2)(1)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3623	1

Signal:

RAM_MEMORY(2)(0)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3631	1

Signal:

RAM_MEMORY(3)(31)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3555	1

Signal:

RAM_MEMORY(3)(30)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3559	1

Signal:

RAM_MEMORY(3)(29)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3552	1

Signal:

RAM_MEMORY(3)(28)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3542	1

Signal:

RAM_MEMORY(3)(27)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3538	1

Signal:

RAM_MEMORY(3)(26)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3542	1

Signal:

RAM_MEMORY(3)(25)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3555	1

Signal:

RAM_MEMORY(3)(24)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3552	1

Signal:

RAM_MEMORY(3)(23)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3471	1

Signal:

RAM_MEMORY(3)(22)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3491	1

Signal:

RAM_MEMORY(3)(21)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3488	1

Signal:

RAM_MEMORY(3)(20)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3471	1

Signal:

RAM_MEMORY(3)(19)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3487	1

Signal:

RAM_MEMORY(3)(18)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	3499	1

Signal:

RAM_MEMORY(3)(17)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	3543	1

Signal:

RAM_MEMORY(3)(16)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3471	1

Signal:

RAM_MEMORY(3)(15)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3539	1

Signal:

RAM_MEMORY(3)(14)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3542	1

Signal:

RAM_MEMORY(3)(13)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3542	1

Signal:

RAM_MEMORY(3)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3552	1

Signal:

RAM_MEMORY(3)(11)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3556	1

Signal:

RAM_MEMORY(3)(10)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3539	1

Signal:

RAM_MEMORY(3)(9)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	3559	1

Signal:

RAM_MEMORY(3)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3535	1

Signal:

RAM_MEMORY(3)(7)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3538	1

Signal:

RAM_MEMORY(3)(6)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3539	1

Signal:

RAM_MEMORY(3)(5)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3538	1

Signal:

RAM_MEMORY(3)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3535	1

Signal:

RAM_MEMORY(3)(3)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3555	1

Signal:

RAM_MEMORY(3)(2)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3556	1

Signal:

RAM_MEMORY(3)(1)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3538	1

Signal:

RAM_MEMORY(3)(0)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3538	1

Signal:

RAM_MEMORY(4)(31)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	3005	1

Signal:

RAM_MEMORY(4)(30)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	3010	1

Signal:

RAM_MEMORY(4)(29)

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	3020	1

Signal:

RAM_MEMORY(4)(28)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	3069	1

Signal:

RAM_MEMORY(4)(27)

	From	To	Count	Threshold
Bin	0	1	194	1
Bin	1	0	3040	1

Signal:

RAM_MEMORY(4)(26)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	3053	1

Signal:

RAM_MEMORY(4)(25)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	2982	1

Signal:

RAM_MEMORY(4)(24)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	3055	1

Signal:

RAM_MEMORY(4)(23)

	From	To	Count	Threshold
Bin	0	1	175	1
Bin	1	0	3000	1

Signal:

RAM_MEMORY(4)(22)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	3000	1

Signal:

RAM_MEMORY(4)(21)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	2946	1

Signal:

RAM_MEMORY(4)(20)

	From	To	Count	Threshold
Bin	0	1	190	1
Bin	1	0	3039	1

Signal:

RAM_MEMORY(4)(19)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	3024	1

Signal:

RAM_MEMORY(4)(18)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	3018	1

Signal:

RAM_MEMORY(4)(17)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	3014	1

Signal:

RAM_MEMORY(4)(16)

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	3010	1

Signal:

RAM_MEMORY(4)(15)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2960	1

Signal:

RAM_MEMORY(4)(14)

	From	To	Count	Threshold
Bin	0	1	175	1
Bin	1	0	3009	1

Signal:

RAM_MEMORY(4)(13)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	3013	1

Signal:

RAM_MEMORY(4)(12)

	From	To	Count	Threshold
Bin	0	1	177	1
Bin	1	0	2992	1

Signal:

RAM_MEMORY(4)(11)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	3031	1

Signal:

RAM_MEMORY(4)(10)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	2994	1

Signal:

RAM_MEMORY(4)(9)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	2983	1

Signal:

RAM_MEMORY(4)(8)

	From	To	Count	Threshold
Bin	0	1	167	1
Bin	1	0	3015	1

Signal:

RAM_MEMORY(4)(7)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	2928	1

Signal:

RAM_MEMORY(4)(6)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2971	1

Signal:

RAM_MEMORY(4)(5)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	2949	1

Signal:

RAM_MEMORY(4)(4)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	2984	1

Signal:

RAM_MEMORY(4)(3)

	From	To	Count	Threshold
Bin	0	1	212	1
Bin	1	0	2953	1

Signal:

RAM_MEMORY(4)(2)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	2925	1

Signal:

RAM_MEMORY(4)(1)

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	2932	1

Signal:

RAM_MEMORY(4)(0)

	From	To	Count	Threshold
Bin	0	1	203	1
Bin	1	0	3003	1

Signal:

RAM_MEMORY(5)(31)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	2995	1

Signal:

RAM_MEMORY(5)(30)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	3011	1

Signal:

RAM_MEMORY(5)(29)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	3027	1

Signal:

RAM_MEMORY(5)(28)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2967	1

Signal:

RAM_MEMORY(5)(27)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	2993	1

Signal:

RAM_MEMORY(5)(26)

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	2963	1

Signal:

RAM_MEMORY(5)(25)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(5)(24)

	From	To	Count	Threshold
Bin	0	1	161	1
Bin	1	0	3024	1

Signal:

RAM_MEMORY(5)(23)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	2910	1

Signal:

RAM_MEMORY(5)(22)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2962	1

Signal:

RAM_MEMORY(5)(21)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(5)(20)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2941	1

Signal:

RAM_MEMORY(5)(19)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	2963	1

Signal:

RAM_MEMORY(5)(18)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2942	1

Signal:

RAM_MEMORY(5)(17)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2994	1

Signal:

RAM_MEMORY(5)(16)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2990	1

Signal:

RAM_MEMORY(5)(15)

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	2940	1

Signal:

RAM_MEMORY(5)(14)

	From	To	Count	Threshold
Bin	0	1	173	1
Bin	1	0	2989	1

Signal:

RAM_MEMORY(5)(13)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2994	1

Signal:

RAM_MEMORY(5)(12)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	2947	1

Signal:

RAM_MEMORY(5)(11)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2955	1

Signal:

RAM_MEMORY(5)(10)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	2969	1

Signal:

RAM_MEMORY(5)(9)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2986	1

Signal:

RAM_MEMORY(5)(8)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2941	1

Signal:

RAM_MEMORY(5)(7)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	2915	1

Signal:

RAM_MEMORY(5)(6)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	2976	1

Signal:

RAM_MEMORY(5)(5)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	2904	1

Signal:

RAM_MEMORY(5)(4)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2915	1

Signal:

RAM_MEMORY(5)(3)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	2870	1

Signal:

RAM_MEMORY(5)(2)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2869	1

Signal:

RAM_MEMORY(5)(1)

	From	To	Count	Threshold
Bin	0	1	187	1
Bin	1	0	2977	1

Signal:

RAM_MEMORY(5)(0)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	2915	1

Signal:

RAM_MEMORY(6)(31)

	From	To	Count	Threshold
Bin	0	1	142	1
Bin	1	0	2897	1

Signal:

RAM_MEMORY(6)(30)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2919	1

Signal:

RAM_MEMORY(6)(29)

	From	To	Count	Threshold
Bin	0	1	126	1
Bin	1	0	2891	1

Signal:

RAM_MEMORY(6)(28)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2933	1

Signal:

RAM_MEMORY(6)(27)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	2879	1

Signal:

RAM_MEMORY(6)(26)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2934	1

Signal:

RAM_MEMORY(6)(25)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	2900	1

Signal:

RAM_MEMORY(6)(24)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2869	1

Signal:

RAM_MEMORY(6)(23)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2873	1

Signal:

RAM_MEMORY(6)(22)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2839	1

Signal:

RAM_MEMORY(6)(21)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2801	1

Signal:

RAM_MEMORY(6)(20)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	2887	1

Signal:

RAM_MEMORY(6)(19)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	2947	1

Signal:

RAM_MEMORY(6)(18)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2935	1

Signal:

RAM_MEMORY(6)(17)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2955	1

Signal:

RAM_MEMORY(6)(16)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2929	1

Signal:

RAM_MEMORY(6)(15)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2862	1

Signal:

RAM_MEMORY(6)(14)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2930	1

Signal:

RAM_MEMORY(6)(13)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2866	1

Signal:

RAM_MEMORY(6)(12)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2888	1

Signal:

RAM_MEMORY(6)(11)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2952	1

Signal:

RAM_MEMORY(6)(10)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2832	1

Signal:

RAM_MEMORY(6)(9)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	2895	1

Signal:

RAM_MEMORY(6)(8)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2861	1

Signal:

RAM_MEMORY(6)(7)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	2867	1

Signal:

RAM_MEMORY(6)(6)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2881	1

Signal:

RAM_MEMORY(6)(5)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2962	1

Signal:

RAM_MEMORY(6)(4)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2813	1

Signal:

RAM_MEMORY(6)(3)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2866	1

Signal:

RAM_MEMORY(6)(2)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	2892	1

Signal:

RAM_MEMORY(6)(1)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2892	1

Signal:

RAM_MEMORY(6)(0)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2875	1

Signal:

RAM_MEMORY(7)(31)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(30)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2789	1

Signal:

RAM_MEMORY(7)(29)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2776	1

Signal:

RAM_MEMORY(7)(28)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2858	1

Signal:

RAM_MEMORY(7)(27)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2805	1

Signal:

RAM_MEMORY(7)(26)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	2801	1

Signal:

RAM_MEMORY(7)(25)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2791	1

Signal:

RAM_MEMORY(7)(24)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2830	1

Signal:

RAM_MEMORY(7)(23)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2816	1

Signal:

RAM_MEMORY(7)(22)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2862	1

Signal:

RAM_MEMORY(7)(21)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2816	1

Signal:

RAM_MEMORY(7)(20)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	2780	1

Signal:

RAM_MEMORY(7)(19)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	2776	1

Signal:

RAM_MEMORY(7)(18)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2849	1

Signal:

RAM_MEMORY(7)(17)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2803	1

Signal:

RAM_MEMORY(7)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2776	1

Signal:

RAM_MEMORY(7)(15)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2801	1

Signal:

RAM_MEMORY(7)(14)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2858	1

Signal:

RAM_MEMORY(7)(13)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2859	1

Signal:

RAM_MEMORY(7)(12)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2834	1

Signal:

RAM_MEMORY(7)(11)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2843	1

Signal:

RAM_MEMORY(7)(10)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2870	1

Signal:

RAM_MEMORY(7)(9)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2874	1

Signal:

RAM_MEMORY(7)(8)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2858	1

Signal:

RAM_MEMORY(7)(7)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2859	1

Signal:

RAM_MEMORY(7)(6)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2804	1

Signal:

RAM_MEMORY(7)(5)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2834	1

Signal:

RAM_MEMORY(7)(4)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2776	1

Signal:

RAM_MEMORY(7)(3)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2801	1

Signal:

RAM_MEMORY(7)(2)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(1)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2801	1

Signal:

RAM_MEMORY(7)(0)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2792	1

Signal:

RAM_MEMORY(8)(31)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2658	1

Signal:

RAM_MEMORY(8)(30)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	2655	1

Signal:

RAM_MEMORY(8)(29)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2687	1

Signal:

RAM_MEMORY(8)(28)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2699	1

Signal:

RAM_MEMORY(8)(27)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(26)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2743	1

Signal:

RAM_MEMORY(8)(25)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2675	1

Signal:

RAM_MEMORY(8)(24)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(8)(23)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2708	1

Signal:

RAM_MEMORY(8)(22)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2708	1

Signal:

RAM_MEMORY(8)(21)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	2728	1

Signal:

RAM_MEMORY(8)(20)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	2699	1

Signal:

RAM_MEMORY(8)(19)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	2678	1

Signal:

RAM_MEMORY(8)(18)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	2658	1

Signal:

RAM_MEMORY(8)(17)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2731	1

Signal:

RAM_MEMORY(8)(16)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2655	1

Signal:

RAM_MEMORY(8)(15)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	2675	1

Signal:

RAM_MEMORY(8)(14)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2731	1

Signal:

RAM_MEMORY(8)(13)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(12)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2743	1

Signal:

RAM_MEMORY(8)(11)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2687	1

Signal:

RAM_MEMORY(8)(10)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	2643	1

Signal:

RAM_MEMORY(8)(9)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2655	1

Signal:

RAM_MEMORY(8)(8)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	2696	1

Signal:

RAM_MEMORY(8)(7)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2655	1

Signal:

RAM_MEMORY(8)(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2643	1

Signal:

RAM_MEMORY(8)(5)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(8)(4)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(8)(3)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(8)(2)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2743	1

Signal:

RAM_MEMORY(8)(1)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2731	1

Signal:

RAM_MEMORY(8)(0)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(9)(31)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2579	1

Signal:

RAM_MEMORY(9)(30)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2590	1

Signal:

RAM_MEMORY(9)(29)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2529	1

Signal:

RAM_MEMORY(9)(28)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2561	1

Signal:

RAM_MEMORY(9)(27)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2581	1

Signal:

RAM_MEMORY(9)(26)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2590	1

Signal:

RAM_MEMORY(9)(25)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2561	1

Signal:

RAM_MEMORY(9)(24)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2559	1

Signal:

RAM_MEMORY(9)(23)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2527	1

Signal:

RAM_MEMORY(9)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2507	1

Signal:

RAM_MEMORY(9)(21)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2527	1

Signal:

RAM_MEMORY(9)(20)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2548	1

Signal:

RAM_MEMORY(9)(19)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2590	1

Signal:

RAM_MEMORY(9)(18)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2592	1

Signal:

RAM_MEMORY(9)(17)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2550	1

Signal:

RAM_MEMORY(9)(16)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2559	1

Signal:

RAM_MEMORY(9)(15)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2550	1

Signal:

RAM_MEMORY(9)(14)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2548	1

Signal:

RAM_MEMORY(9)(13)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2540	1

Signal:

RAM_MEMORY(9)(12)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2529	1

Signal:

RAM_MEMORY(9)(11)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2550	1

Signal:

RAM_MEMORY(9)(10)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	2579	1

Signal:

RAM_MEMORY(9)(9)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2496	1

Signal:

RAM_MEMORY(9)(8)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2592	1

Signal:

RAM_MEMORY(9)(7)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2579	1

Signal:

RAM_MEMORY(9)(6)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2590	1

Signal:

RAM_MEMORY(9)(5)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2550	1

Signal:

RAM_MEMORY(9)(4)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2548	1

Signal:

RAM_MEMORY(9)(3)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2579	1

Signal:

RAM_MEMORY(9)(2)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	2559	1

Signal:

RAM_MEMORY(9)(1)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2592	1

Signal:

RAM_MEMORY(9)(0)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2561	1

Signal:

RAM_MEMORY(10)(31)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(29)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(28)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(27)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(26)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(25)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(24)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(23)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(22)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(21)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(19)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(18)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(17)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(16)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(15)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(13)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(11)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(9)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(7)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(6)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(5)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(3)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(10)(1)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(10)(0)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(11)(31)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(30)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(29)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(27)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(26)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(25)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(24)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(23)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(22)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(21)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(19)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(18)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(17)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(16)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(15)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(14)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(13)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(12)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(10)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(9)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(7)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(5)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(4)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(3)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(2)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2303	1

Signal:

RAM_MEMORY(11)(1)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(11)(0)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2312	1

Signal:

RAM_MEMORY(12)(31)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(30)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(29)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(28)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(27)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(26)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(25)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(24)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(23)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(22)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(21)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(20)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(19)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(18)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(17)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(15)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(14)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(13)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(12)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(11)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(10)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(9)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(8)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(7)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(5)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(4)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(3)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(12)(1)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2159	1

Signal:

RAM_MEMORY(12)(0)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2151	1

Signal:

RAM_MEMORY(13)(31)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(30)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(29)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(27)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(26)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(25)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(24)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(23)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(22)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(21)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(19)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(18)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(17)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(16)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(15)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(13)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(11)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(10)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(9)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(8)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(7)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(6)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(5)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(4)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(3)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(13)(1)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1999	1

Signal:

RAM_MEMORY(13)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2006	1

Signal:

RAM_MEMORY(14)(31)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(30)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(29)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(28)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(27)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(26)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(25)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(23)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(21)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(20)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(19)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(18)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(17)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(15)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(13)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(11)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(10)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(9)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(8)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(7)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(6)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(5)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(4)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1853	1

Signal:

RAM_MEMORY(14)(3)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(1)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(14)(0)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1847	1

Signal:

RAM_MEMORY(15)(31)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(29)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(28)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(27)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(26)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(25)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(24)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(23)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(22)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(21)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(20)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(19)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(17)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(15)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(13)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(11)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(10)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(9)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(7)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(5)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(4)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1695	1

Signal:

RAM_MEMORY(15)(3)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(2)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(1)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(15)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1700	1

Signal:

RAM_MEMORY(16)(31)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(29)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(27)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(26)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(25)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(24)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(23)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(21)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(19)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(17)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(15)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(13)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(11)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(10)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(9)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(7)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(5)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(3)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(16)(1)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1546	1

Signal:

RAM_MEMORY(16)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1550	1

Signal:

RAM_MEMORY(17)(31)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(30)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(29)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(27)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(26)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(25)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(23)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(21)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(19)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(17)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(15)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(13)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(11)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(10)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(9)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(7)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(5)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(3)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1396	1

Signal:

RAM_MEMORY(17)(1)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(17)(0)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1393	1

Signal:

RAM_MEMORY(18)(31)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(29)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(27)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(26)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(25)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(23)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(22)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(21)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(19)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(17)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(15)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(13)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(11)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(9)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(7)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(5)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(3)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(18)(1)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1242	1

Signal:

RAM_MEMORY(18)(0)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1240	1

Signal:

RAM_MEMORY(19)(31)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(29)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(27)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(26)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(25)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(23)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(22)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(21)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(19)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(17)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(15)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(13)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(11)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(9)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(7)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(5)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(3)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1087	1

Signal:

RAM_MEMORY(19)(1)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(19)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1088	1

Signal:

RAM_MEMORY(20)(31)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	976	1

Signal:

RAM_MEMORY(20)(30)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(29)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(28)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(27)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(26)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(25)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	976	1

Signal:

RAM_MEMORY(20)(24)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(23)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	976	1

Signal:

RAM_MEMORY(20)(22)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(21)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(20)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(19)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(18)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(17)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	976	1

Signal:

RAM_MEMORY(20)(16)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	935	1

Signal:

RAM_MEMORY(20)(15)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	771	1

Signal:

RAM_MEMORY(20)(14)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	730	1

Signal:

RAM_MEMORY(20)(13)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	730	1

Signal:

RAM_MEMORY(20)(12)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	752	1

Signal:

RAM_MEMORY(20)(11)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	760	1

Signal:

RAM_MEMORY(20)(10)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	790	1

Signal:

RAM_MEMORY(20)(9)

	From	To	Count	Threshold
Bin	0	1	134	1
Bin	1	0	825	1

Signal:

RAM_MEMORY(20)(8)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	785	1

Signal:

RAM_MEMORY(20)(7)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	761	1

Signal:

RAM_MEMORY(20)(6)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	720	1

Signal:

RAM_MEMORY(20)(5)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	720	1

Signal:

RAM_MEMORY(20)(4)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	741	1

Signal:

RAM_MEMORY(20)(3)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	720	1

Signal:

RAM_MEMORY(20)(2)

	From	To	Count	Threshold
Bin	0	1	143	1
Bin	1	0	798	1

Signal:

RAM_MEMORY(20)(1)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	778	1

Signal:

RAM_MEMORY(20)(0)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	775	1

Signal:

INT_READ_DATA(31)

	From	To	Count	Threshold
Bin	0	1	230	1
Bin	1	0	385	1

Signal:

INT_READ_DATA(30)

	From	To	Count	Threshold
Bin	0	1	333	1
Bin	1	0	488	1

Signal:

INT_READ_DATA(29)

	From	To	Count	Threshold
Bin	0	1	309	1
Bin	1	0	464	1

Signal:

INT_READ_DATA(28)

	From	To	Count	Threshold
Bin	0	1	909	1
Bin	1	0	1064	1

Signal:

INT_READ_DATA(27)

	From	To	Count	Threshold
Bin	0	1	1192	1
Bin	1	0	1346	1

Signal:

INT_READ_DATA(26)

	From	To	Count	Threshold
Bin	0	1	1178	1
Bin	1	0	1333	1

Signal:

INT_READ_DATA(25)

	From	To	Count	Threshold
Bin	0	1	1129	1
Bin	1	0	1284	1

Signal:

INT_READ_DATA(24)

	From	To	Count	Threshold
Bin	0	1	1220	1
Bin	1	0	1375	1

Signal:

INT_READ_DATA(23)

	From	To	Count	Threshold
Bin	0	1	1457	1
Bin	1	0	1612	1

Signal:

INT_READ_DATA(22)

	From	To	Count	Threshold
Bin	0	1	1508	1
Bin	1	0	1663	1

Signal:

INT_READ_DATA(21)

	From	To	Count	Threshold
Bin	0	1	1213	1
Bin	1	0	1368	1

Signal:

INT_READ_DATA(20)

	From	To	Count	Threshold
Bin	0	1	1171	1
Bin	1	0	1326	1

Signal:

INT_READ_DATA(19)

	From	To	Count	Threshold
Bin	0	1	1386	1
Bin	1	0	1541	1

Signal:

INT_READ_DATA(18)

	From	To	Count	Threshold
Bin	0	1	1247	1
Bin	1	0	1402	1

Signal:

INT_READ_DATA(17)

	From	To	Count	Threshold
Bin	0	1	638	1
Bin	1	0	793	1

Signal:

INT_READ_DATA(16)

	From	To	Count	Threshold
Bin	0	1	863	1
Bin	1	0	1018	1

Signal:

INT_READ_DATA(15)

	From	To	Count	Threshold
Bin	0	1	678	1
Bin	1	0	833	1

Signal:

INT_READ_DATA(14)

	From	To	Count	Threshold
Bin	0	1	946	1
Bin	1	0	1101	1

Signal:

INT_READ_DATA(13)

	From	To	Count	Threshold
Bin	0	1	1035	1
Bin	1	0	1190	1

Signal:

INT_READ_DATA(12)

	From	To	Count	Threshold
Bin	0	1	633	1
Bin	1	0	788	1

Signal:

INT_READ_DATA(11)

	From	To	Count	Threshold
Bin	0	1	673	1
Bin	1	0	828	1

Signal:

INT_READ_DATA(10)

	From	To	Count	Threshold
Bin	0	1	587	1
Bin	1	0	742	1

Signal:

INT_READ_DATA(9)

	From	To	Count	Threshold
Bin	0	1	1363	1
Bin	1	0	1518	1

Signal:

INT_READ_DATA(8)

	From	To	Count	Threshold
Bin	0	1	876	1
Bin	1	0	1031	1

Signal:

INT_READ_DATA(7)

	From	To	Count	Threshold
Bin	0	1	1647	1
Bin	1	0	1802	1

Signal:

INT_READ_DATA(6)

	From	To	Count	Threshold
Bin	0	1	1176	1
Bin	1	0	1330	1

Signal:

INT_READ_DATA(5)

	From	To	Count	Threshold
Bin	0	1	1352	1
Bin	1	0	1507	1

Signal:

INT_READ_DATA(4)

	From	To	Count	Threshold
Bin	0	1	1000	1
Bin	1	0	1155	1

Signal:

INT_READ_DATA(3)

	From	To	Count	Threshold
Bin	0	1	815	1
Bin	1	0	970	1

Signal:

INT_READ_DATA(2)

	From	To	Count	Threshold
Bin	0	1	1125	1
Bin	1	0	1280	1

Signal:

INT_READ_DATA(1)

	From	To	Count	Threshold
Bin	0	1	1167	1
Bin	1	0	1322	1

Signal:

INT_READ_DATA(0)

	From	To	Count	Threshold
Bin	0	1	1415	1
Bin	1	0	1570	1

Signal:

BYTE_WE(3)

	From	To	Count	Threshold
Bin	0	1	11472	1
Bin	1	0	11637	1

Signal:

BYTE_WE(2)

	From	To	Count	Threshold
Bin	0	1	11472	1
Bin	1	0	11637	1

Signal:

BYTE_WE(1)

	From	To	Count	Threshold
Bin	0	1	11472	1
Bin	1	0	11637	1

Signal:

BYTE_WE(0)

	From	To	Count	Threshold
Bin	0	1	11472	1
Bin	1	0	11637	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: