NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/test_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ADDR_DEC_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_REG_FALSE_GEN	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

ADDR_DEC_GEN(0)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(1)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(2)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_GEN(3)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

ADDR_DEC_REG_FALSE_GEN

100.0 % (1/1)

N.A.

100.0 % (1/1)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_TEST_REGISTERS_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (42/42)	100.0 % (2/2)	N.A.	N.A.	100.0 % (49/49)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_TEST_REGISTERS_COMP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (42/42)

100.0 % (2/2)

N.A.

100.0 % (49/49)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 153 to 154:

153:    addr_dec_enabled_i <= addr_dec_i when (enable = '1') else 
154:                          (OTHERS => '0');

Count: 19913561
Threshold: 1

Signal assignment statement on line 153:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
Count: 313176
Threshold: 1

Signal assignment statement on line 154:

154: (OTHERS => '0');
Count: 19600385
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 153:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	313176	1
Bin	False	19600385	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

ADDR_DEC

	Element	From	To	Count	Threshold
Bin	(3)	0	1	93763	1
Bin	(3)	1	0	534190	1
Bin	(2)	0	1	41383	1
Bin	(2)	1	0	586570	1
Bin	(1)	0	1	135146	1
Bin	(1)	1	0	492807	1
Bin	(0)	0	1	42884	1
Bin	(0)	1	0	585069	1

Signal:

ADDR_DEC_I

	Element	From	To	Count	Threshold
Bin	(3)	0	1	149571	1
Bin	(3)	1	0	19762389	1
Bin	(2)	0	1	9428029	1
Bin	(2)	1	0	10483931	1
Bin	(1)	0	1	279547	1
Bin	(1)	1	0	19632413	1
Bin	(0)	0	1	98833	1
Bin	(0)	1	0	19813127	1

Signal:

ADDR_DEC_ENABLED_I

	Element	From	To	Count	Threshold
Bin	(3)	0	1	93763	1
Bin	(3)	1	0	95364	1
Bin	(2)	0	1	41383	1
Bin	(2)	1	0	42984	1
Bin	(1)	0	1	135146	1
Bin	(1)	1	0	136747	1
Bin	(0)	0	1	42884	1
Bin	(0)	1	0	44485	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 153:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	19600385	1
Bin	True	313176	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_TEST_REGISTERS_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/test_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 153 to 154:

Signal assignment statement on line 153:

Signal assignment statement on line 154:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 153:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 153:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: