NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ADDR_DEC_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
ADDR_DEC_REG_FALSE_GEN	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_TEST_REGISTERS_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (42/42)	100.0 % (2/2)	N.A.	N.A.	100.0 % (49/49)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

153:    addr_dec_enabled_i <= addr_dec_i when (enable = '1') else 
154:                          (OTHERS => '0');

Count: 20338106
Threshold: 1

Signal assignment statement:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
Count: 313006
Threshold: 1

Signal assignment statement:

154: (OTHERS => '0');
Count: 20025100
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	313006	1
Bin	False	20025100	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13267459	1
Bin	1	0	13269059	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

ADDRESS(5)

	From	To	Count	Threshold
Bin	0	1	16744778	1
Bin	1	0	11049255	1

Port:

ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	328560	1
Bin	1	0	27465473	1

Port:

ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	576099	1
Bin	1	0	27217934	1

Port:

ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	436079	1
Bin	1	0	27357954	1

Port:

ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	27015237	1
Bin	1	0	778796	1

Port:

ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	17655249	1
Bin	1	0	10138784	1

Port:

ENABLE

	From	To	Count	Threshold
Bin	0	1	313006	1
Bin	1	0	314606	1

Port:

ADDR_DEC(3)

	From	To	Count	Threshold
Bin	0	1	93729	1
Bin	1	0	533883	1

Port:

ADDR_DEC(2)

	From	To	Count	Threshold
Bin	0	1	41349	1
Bin	1	0	586263	1

Port:

ADDR_DEC(1)

	From	To	Count	Threshold
Bin	0	1	135078	1
Bin	1	0	492534	1

Port:

ADDR_DEC(0)

	From	To	Count	Threshold
Bin	0	1	42850	1
Bin	1	0	584762	1

Signal:

ADDR_DEC_I(3)

	From	To	Count	Threshold
Bin	0	1	149084	1
Bin	1	0	20187422	1

Signal:

ADDR_DEC_I(2)

	From	To	Count	Threshold
Bin	0	1	9641830	1
Bin	1	0	10694676	1

Signal:

ADDR_DEC_I(1)

	From	To	Count	Threshold
Bin	0	1	278997	1
Bin	1	0	20057509	1

Signal:

ADDR_DEC_I(0)

	From	To	Count	Threshold
Bin	0	1	98342	1
Bin	1	0	20238164	1

Signal:

ADDR_DEC_ENABLED_I(3)

	From	To	Count	Threshold
Bin	0	1	93729	1
Bin	1	0	95329	1

Signal:

ADDR_DEC_ENABLED_I(2)

	From	To	Count	Threshold
Bin	0	1	41349	1
Bin	1	0	42949	1

Signal:

ADDR_DEC_ENABLED_I(1)

	From	To	Count	Threshold
Bin	0	1	135078	1
Bin	1	0	136678	1

Signal:

ADDR_DEC_ENABLED_I(0)

	From	To	Count	Threshold
Bin	0	1	42850	1
Bin	1	0	44450	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else

	Evaluated to	Count	Threshold
Bin	False	20025100	1
Bin	True	313006	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_TEST_REGISTERS_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

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Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: