Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_A_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| GEN_FILT_POS |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
100.0 % (5/5) |
N.A. |
N.A. |
100.0 % (10/10) |
| GEN_FILT_NEG |
100.0 % (1/1) |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (1/1) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
Signal assignment statement:
121: masked_input <= filter_input and filter_mask; Count: 114696
Threshold: 1
Signal assignment statement:
122: masked_value <= filter_value and filter_mask; Count: 8298
Threshold: 1
Covered toggles:
Port:
FILTER_MASK(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 412 | 1 |
| Bin | 1 | 0 | 2012 | 1 |
Port:
FILTER_MASK(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 334 | 1 |
| Bin | 1 | 0 | 1934 | 1 |
Port:
FILTER_MASK(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 358 | 1 |
| Bin | 1 | 0 | 1958 | 1 |
Port:
FILTER_MASK(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 362 | 1 |
| Bin | 1 | 0 | 1962 | 1 |
Port:
FILTER_MASK(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 390 | 1 |
| Bin | 1 | 0 | 1990 | 1 |
Port:
FILTER_MASK(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2007 | 1 |
Port:
FILTER_MASK(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 387 | 1 |
| Bin | 1 | 0 | 1987 | 1 |
Port:
FILTER_MASK(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 344 | 1 |
| Bin | 1 | 0 | 1944 | 1 |
Port:
FILTER_MASK(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 376 | 1 |
| Bin | 1 | 0 | 1976 | 1 |
Port:
FILTER_MASK(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
Port:
FILTER_MASK(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 412 | 1 |
| Bin | 1 | 0 | 2012 | 1 |
Port:
FILTER_MASK(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
Port:
FILTER_MASK(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
Port:
FILTER_MASK(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
Port:
FILTER_MASK(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
Port:
FILTER_MASK(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 1691 | 1 |
Port:
FILTER_MASK(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
Port:
FILTER_MASK(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123 | 1 |
| Bin | 1 | 0 | 1723 | 1 |
Port:
FILTER_MASK(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 256 | 1 |
| Bin | 1 | 0 | 1856 | 1 |
Port:
FILTER_MASK(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 1867 | 1 |
Port:
FILTER_MASK(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 1867 | 1 |
Port:
FILTER_MASK(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 1882 | 1 |
Port:
FILTER_MASK(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 1843 | 1 |
Port:
FILTER_MASK(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 276 | 1 |
| Bin | 1 | 0 | 1876 | 1 |
Port:
FILTER_MASK(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
Port:
FILTER_MASK(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 265 | 1 |
| Bin | 1 | 0 | 1865 | 1 |
Port:
FILTER_MASK(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 274 | 1 |
| Bin | 1 | 0 | 1874 | 1 |
Port:
FILTER_MASK(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 234 | 1 |
| Bin | 1 | 0 | 1834 | 1 |
Port:
FILTER_MASK(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 1896 | 1 |
Port:
FILTER_VALUE(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 786 | 1 |
| Bin | 1 | 0 | 2386 | 1 |
Port:
FILTER_VALUE(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 850 | 1 |
| Bin | 1 | 0 | 2450 | 1 |
Port:
FILTER_VALUE(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
Port:
FILTER_VALUE(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 738 | 1 |
| Bin | 1 | 0 | 2338 | 1 |
Port:
FILTER_VALUE(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
Port:
FILTER_VALUE(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 782 | 1 |
| Bin | 1 | 0 | 2382 | 1 |
Port:
FILTER_VALUE(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 837 | 1 |
| Bin | 1 | 0 | 2437 | 1 |
Port:
FILTER_VALUE(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 822 | 1 |
| Bin | 1 | 0 | 2422 | 1 |
Port:
FILTER_VALUE(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 781 | 1 |
| Bin | 1 | 0 | 2381 | 1 |
Port:
FILTER_VALUE(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 816 | 1 |
| Bin | 1 | 0 | 2416 | 1 |
Port:
FILTER_VALUE(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 814 | 1 |
| Bin | 1 | 0 | 2414 | 1 |
Port:
FILTER_VALUE(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 397 | 1 |
| Bin | 1 | 0 | 1997 | 1 |
Port:
FILTER_VALUE(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 397 | 1 |
| Bin | 1 | 0 | 1997 | 1 |
Port:
FILTER_VALUE(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2007 | 1 |
Port:
FILTER_VALUE(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 433 | 1 |
| Bin | 1 | 0 | 2033 | 1 |
Port:
FILTER_VALUE(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 2009 | 1 |
Port:
FILTER_VALUE(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 375 | 1 |
| Bin | 1 | 0 | 1975 | 1 |
Port:
FILTER_VALUE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 458 | 1 |
| Bin | 1 | 0 | 2058 | 1 |
Port:
FILTER_VALUE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 405 | 1 |
| Bin | 1 | 0 | 2005 | 1 |
Port:
FILTER_VALUE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 385 | 1 |
| Bin | 1 | 0 | 1985 | 1 |
Port:
FILTER_VALUE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 381 | 1 |
| Bin | 1 | 0 | 1981 | 1 |
Port:
FILTER_VALUE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 399 | 1 |
| Bin | 1 | 0 | 1999 | 1 |
Port:
FILTER_VALUE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 405 | 1 |
| Bin | 1 | 0 | 2005 | 1 |
Port:
FILTER_VALUE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 415 | 1 |
| Bin | 1 | 0 | 2015 | 1 |
Port:
FILTER_VALUE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 417 | 1 |
| Bin | 1 | 0 | 2017 | 1 |
Port:
FILTER_VALUE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2007 | 1 |
Port:
FILTER_VALUE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 416 | 1 |
| Bin | 1 | 0 | 2016 | 1 |
Port:
FILTER_VALUE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 378 | 1 |
| Bin | 1 | 0 | 1978 | 1 |
Port:
FILTER_VALUE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 417 | 1 |
| Bin | 1 | 0 | 2017 | 1 |
Port:
FILTER_INPUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34332 | 1 |
| Bin | 1 | 0 | 30165 | 1 |
Port:
FILTER_INPUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20951 | 1 |
| Bin | 1 | 0 | 16748 | 1 |
Port:
FILTER_INPUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34995 | 1 |
| Bin | 1 | 0 | 29978 | 1 |
Port:
FILTER_INPUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26409 | 1 |
| Bin | 1 | 0 | 21440 | 1 |
Port:
FILTER_INPUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37621 | 1 |
| Bin | 1 | 0 | 32560 | 1 |
Port:
FILTER_INPUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27574 | 1 |
| Bin | 1 | 0 | 22162 | 1 |
Port:
FILTER_INPUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37576 | 1 |
| Bin | 1 | 0 | 32729 | 1 |
Port:
FILTER_INPUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26623 | 1 |
| Bin | 1 | 0 | 21662 | 1 |
Port:
FILTER_INPUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34131 | 1 |
| Bin | 1 | 0 | 30013 | 1 |
Port:
FILTER_INPUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25018 | 1 |
| Bin | 1 | 0 | 20939 | 1 |
Port:
FILTER_INPUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35861 | 1 |
| Bin | 1 | 0 | 31802 | 1 |
Port:
FILTER_INPUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6676 | 1 |
| Bin | 1 | 0 | 77411 | 1 |
Port:
FILTER_INPUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 76980 | 1 |
Port:
FILTER_INPUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6016 | 1 |
| Bin | 1 | 0 | 75936 | 1 |
Port:
FILTER_INPUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6457 | 1 |
| Bin | 1 | 0 | 77301 | 1 |
Port:
FILTER_INPUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6203 | 1 |
| Bin | 1 | 0 | 75854 | 1 |
Port:
FILTER_INPUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6655 | 1 |
| Bin | 1 | 0 | 77348 | 1 |
Port:
FILTER_INPUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6116 | 1 |
| Bin | 1 | 0 | 76014 | 1 |
Port:
FILTER_INPUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6759 | 1 |
| Bin | 1 | 0 | 77172 | 1 |
Port:
FILTER_INPUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6340 | 1 |
| Bin | 1 | 0 | 76882 | 1 |
Port:
FILTER_INPUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7191 | 1 |
| Bin | 1 | 0 | 78168 | 1 |
Port:
FILTER_INPUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6170 | 1 |
| Bin | 1 | 0 | 76119 | 1 |
Port:
FILTER_INPUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 77753 | 1 |
Port:
FILTER_INPUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6122 | 1 |
| Bin | 1 | 0 | 76213 | 1 |
Port:
FILTER_INPUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6712 | 1 |
| Bin | 1 | 0 | 78180 | 1 |
Port:
FILTER_INPUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6213 | 1 |
| Bin | 1 | 0 | 76204 | 1 |
Port:
FILTER_INPUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7044 | 1 |
| Bin | 1 | 0 | 78347 | 1 |
Port:
FILTER_INPUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6316 | 1 |
| Bin | 1 | 0 | 75925 | 1 |
Port:
FILTER_INPUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6757 | 1 |
| Bin | 1 | 0 | 77490 | 1 |
Port:
ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2598 | 1 |
| Bin | 1 | 0 | 998 | 1 |
Port:
VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2084 | 1 |
| Bin | 1 | 0 | 3024 | 1 |
Signal:
MASKED_INPUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 484 | 1 |
| Bin | 1 | 0 | 2084 | 1 |
Signal:
MASKED_INPUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 403 | 1 |
| Bin | 1 | 0 | 2003 | 1 |
Signal:
MASKED_INPUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 391 | 1 |
| Bin | 1 | 0 | 1991 | 1 |
Signal:
MASKED_INPUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436 | 1 |
| Bin | 1 | 0 | 2036 | 1 |
Signal:
MASKED_INPUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 445 | 1 |
| Bin | 1 | 0 | 2045 | 1 |
Signal:
MASKED_INPUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 454 | 1 |
| Bin | 1 | 0 | 2054 | 1 |
Signal:
MASKED_INPUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 456 | 1 |
| Bin | 1 | 0 | 2056 | 1 |
Signal:
MASKED_INPUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 361 | 1 |
| Bin | 1 | 0 | 1961 | 1 |
Signal:
MASKED_INPUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 437 | 1 |
| Bin | 1 | 0 | 2037 | 1 |
Signal:
MASKED_INPUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436 | 1 |
| Bin | 1 | 0 | 2036 | 1 |
Signal:
MASKED_INPUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 470 | 1 |
| Bin | 1 | 0 | 2070 | 1 |
Signal:
MASKED_INPUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1642 | 1 |
Signal:
MASKED_INPUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 1648 | 1 |
Signal:
MASKED_INPUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
Signal:
MASKED_INPUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Signal:
MASKED_INPUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Signal:
MASKED_INPUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 1648 | 1 |
Signal:
MASKED_INPUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
Signal:
MASKED_INPUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1760 | 1 |
Signal:
MASKED_INPUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162 | 1 |
| Bin | 1 | 0 | 1762 | 1 |
Signal:
MASKED_INPUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 186 | 1 |
| Bin | 1 | 0 | 1786 | 1 |
Signal:
MASKED_INPUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 178 | 1 |
| Bin | 1 | 0 | 1778 | 1 |
Signal:
MASKED_INPUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
Signal:
MASKED_INPUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 184 | 1 |
| Bin | 1 | 0 | 1784 | 1 |
Signal:
MASKED_INPUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 188 | 1 |
| Bin | 1 | 0 | 1788 | 1 |
Signal:
MASKED_INPUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 153 | 1 |
| Bin | 1 | 0 | 1753 | 1 |
Signal:
MASKED_INPUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 166 | 1 |
| Bin | 1 | 0 | 1766 | 1 |
Signal:
MASKED_INPUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162 | 1 |
| Bin | 1 | 0 | 1762 | 1 |
Signal:
MASKED_INPUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 190 | 1 |
| Bin | 1 | 0 | 1790 | 1 |
Signal:
MASKED_VALUE(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
Signal:
MASKED_VALUE(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236 | 1 |
| Bin | 1 | 0 | 1836 | 1 |
Signal:
MASKED_VALUE(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 251 | 1 |
| Bin | 1 | 0 | 1851 | 1 |
Signal:
MASKED_VALUE(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 230 | 1 |
| Bin | 1 | 0 | 1830 | 1 |
Signal:
MASKED_VALUE(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 280 | 1 |
| Bin | 1 | 0 | 1880 | 1 |
Signal:
MASKED_VALUE(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 277 | 1 |
| Bin | 1 | 0 | 1877 | 1 |
Signal:
MASKED_VALUE(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 283 | 1 |
| Bin | 1 | 0 | 1883 | 1 |
Signal:
MASKED_VALUE(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 242 | 1 |
| Bin | 1 | 0 | 1842 | 1 |
Signal:
MASKED_VALUE(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 249 | 1 |
| Bin | 1 | 0 | 1849 | 1 |
Signal:
MASKED_VALUE(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 264 | 1 |
| Bin | 1 | 0 | 1864 | 1 |
Signal:
MASKED_VALUE(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 326 | 1 |
| Bin | 1 | 0 | 1926 | 1 |
Signal:
MASKED_VALUE(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Signal:
MASKED_VALUE(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36 | 1 |
| Bin | 1 | 0 | 1636 | 1 |
Signal:
MASKED_VALUE(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 38 | 1 |
| Bin | 1 | 0 | 1638 | 1 |
Signal:
MASKED_VALUE(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Signal:
MASKED_VALUE(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Signal:
MASKED_VALUE(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Signal:
MASKED_VALUE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1689 | 1 |
Signal:
MASKED_VALUE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 198 | 1 |
| Bin | 1 | 0 | 1798 | 1 |
Signal:
MASKED_VALUE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 209 | 1 |
| Bin | 1 | 0 | 1809 | 1 |
Signal:
MASKED_VALUE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 213 | 1 |
| Bin | 1 | 0 | 1813 | 1 |
Signal:
MASKED_VALUE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 220 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
Signal:
MASKED_VALUE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 200 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
Signal:
MASKED_VALUE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 229 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Signal:
MASKED_VALUE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 218 | 1 |
| Bin | 1 | 0 | 1818 | 1 |
Signal:
MASKED_VALUE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 218 | 1 |
| Bin | 1 | 0 | 1818 | 1 |
Signal:
MASKED_VALUE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 221 | 1 |
| Bin | 1 | 0 | 1821 | 1 |
Signal:
MASKED_VALUE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 193 | 1 |
| Bin | 1 | 0 | 1793 | 1 |
Signal:
MASKED_VALUE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 227 | 1 |
| Bin | 1 | 0 | 1827 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: