NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 5234
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 5234
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 167488
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 5234
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	351	1
Bin	1	0	506	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	539	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	459	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	740	1
Bin	1	0	889	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	766	1
Bin	1	0	915	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	581	1
Bin	1	0	733	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	845	1
Bin	1	0	997	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	892	1
Bin	1	0	1042	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	787	1
Bin	1	0	936	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	667	1
Bin	1	0	818	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	950	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	606	1
Bin	1	0	755	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	933	1
Bin	1	0	1082	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	774	1
Bin	1	0	923	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	675	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	429	1
Bin	1	0	581	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	717	1
Bin	1	0	869	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	561	1
Bin	1	0	714	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	652	1
Bin	1	0	805	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	507	1
Bin	1	0	660	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	503	1
Bin	1	0	654	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	619	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	972	1
Bin	1	0	1120	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	599	1
Bin	1	0	750	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	948	1
Bin	1	0	1090	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	923	1
Bin	1	0	1073	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	844	1
Bin	1	0	994	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	493	1
Bin	1	0	644	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	709	1
Bin	1	0	859	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	878	1
Bin	1	0	1026	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	938	1
Bin	1	0	1088	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	775	1
Bin	1	0	921	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	1221	1
Bin	1	0	1081	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	33587	1
Bin	'0'	'1'	13072	1
Bin	'1'	'0'	100924	1
Bin	'1'	'1'	14625	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

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Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: