NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	100.0 % (30/30)	N.A.	N.A.	100.0 % (1641/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (17/17)	N.A.	N.A.	100.0 % (109/109)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST	100.0 % (18/18)	100.0 % (12/12)	100.0 % (516/516)	100.0 % (15/15)	N.A.	N.A.	100.0 % (561/561)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 4626
Threshold: 1

Signal assignment statement:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 238
Threshold: 1

Signal assignment statement:

280: '0';
Count: 4388
Threshold: 1

If statement:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 49588694
Threshold: 1

Signal assignment statement:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 49561729
Threshold: 1

Signal assignment statement:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 26965
Threshold: 1

If statement:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 189135
Threshold: 1

Signal assignment statement:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 185325
Threshold: 1

Signal assignment statement:

289: mr_tst_control_twrstb;
Count: 3810
Threshold: 1

If statement:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 1586623
Threshold: 1

Signal assignment statement:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 1569925
Threshold: 1

Signal assignment statement:

293: mr_tst_wdata_tst_wdata;
Count: 16698
Threshold: 1

If statement:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 175632
Threshold: 1

Signal assignment statement:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 171858
Threshold: 1

Signal assignment statement:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 3774
Threshold: 1

If statement:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 16661
Threshold: 1

Signal assignment statement:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 2122
Threshold: 1

Signal assignment statement:

302: (others => '0');
Count: 14539
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	Evaluated to	Count	Threshold
Bin	True	238	1
Bin	False	4388	1

"if" / "when" / "else" condition:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	49561729	1
Bin	False	26965	1

"if" / "when" / "else" condition:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	185325	1
Bin	False	3810	1

"if" / "when" / "else" condition:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	1569925	1
Bin	False	16698	1

"if" / "when" / "else" condition:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	171858	1
Bin	False	3774	1

"if" / "when" / "else" condition:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')

	Evaluated to	Count	Threshold
Bin	True	2122	1
Bin	False	14539	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13640743	1
Bin	1	0	13641403	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	2844	1
Bin	1	0	2844	1

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	770	1

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold
Bin	0	1	636	1
Bin	1	0	1296	1

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold
Bin	0	1	31329	1
Bin	1	0	33257	1

Port:

MR_TST_DEST_TST_ADDR(4)

	From	To	Count	Threshold
Bin	0	1	3406	1
Bin	1	0	4066	1

Port:

MR_TST_DEST_TST_ADDR(3)

	From	To	Count	Threshold
Bin	0	1	4810	1
Bin	1	0	5470	1

Port:

MR_TST_DEST_TST_ADDR(2)

	From	To	Count	Threshold
Bin	0	1	9862	1
Bin	1	0	10522	1

Port:

MR_TST_DEST_TST_ADDR(1)

	From	To	Count	Threshold
Bin	0	1	21367	1
Bin	1	0	22027	1

Port:

MR_TST_DEST_TST_ADDR(0)

	From	To	Count	Threshold
Bin	0	1	42723	1
Bin	1	0	43383	1

Port:

MR_TST_DEST_TST_MTGT(3)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	874	1

Port:

MR_TST_DEST_TST_MTGT(2)

	From	To	Count	Threshold
Bin	0	1	353	1
Bin	1	0	1013	1

Port:

MR_TST_DEST_TST_MTGT(1)

	From	To	Count	Threshold
Bin	0	1	472	1
Bin	1	0	1132	1

Port:

MR_TST_DEST_TST_MTGT(0)

	From	To	Count	Threshold
Bin	0	1	896	1
Bin	1	0	1556	1

Port:

MR_TST_WDATA_TST_WDATA(31)

	From	To	Count	Threshold
Bin	0	1	1490	1
Bin	1	0	2150	1

Port:

MR_TST_WDATA_TST_WDATA(30)

	From	To	Count	Threshold
Bin	0	1	1437	1
Bin	1	0	2097	1

Port:

MR_TST_WDATA_TST_WDATA(29)

	From	To	Count	Threshold
Bin	0	1	1448	1
Bin	1	0	2108	1

Port:

MR_TST_WDATA_TST_WDATA(28)

	From	To	Count	Threshold
Bin	0	1	1585	1
Bin	1	0	2245	1

Port:

MR_TST_WDATA_TST_WDATA(27)

	From	To	Count	Threshold
Bin	0	1	1607	1
Bin	1	0	2267	1

Port:

MR_TST_WDATA_TST_WDATA(26)

	From	To	Count	Threshold
Bin	0	1	1590	1
Bin	1	0	2250	1

Port:

MR_TST_WDATA_TST_WDATA(25)

	From	To	Count	Threshold
Bin	0	1	1603	1
Bin	1	0	2263	1

Port:

MR_TST_WDATA_TST_WDATA(24)

	From	To	Count	Threshold
Bin	0	1	1673	1
Bin	1	0	2333	1

Port:

MR_TST_WDATA_TST_WDATA(23)

	From	To	Count	Threshold
Bin	0	1	1542	1
Bin	1	0	2202	1

Port:

MR_TST_WDATA_TST_WDATA(22)

	From	To	Count	Threshold
Bin	0	1	1481	1
Bin	1	0	2141	1

Port:

MR_TST_WDATA_TST_WDATA(21)

	From	To	Count	Threshold
Bin	0	1	1519	1
Bin	1	0	2179	1

Port:

MR_TST_WDATA_TST_WDATA(20)

	From	To	Count	Threshold
Bin	0	1	1613	1
Bin	1	0	2273	1

Port:

MR_TST_WDATA_TST_WDATA(19)

	From	To	Count	Threshold
Bin	0	1	1608	1
Bin	1	0	2268	1

Port:

MR_TST_WDATA_TST_WDATA(18)

	From	To	Count	Threshold
Bin	0	1	1595	1
Bin	1	0	2255	1

Port:

MR_TST_WDATA_TST_WDATA(17)

	From	To	Count	Threshold
Bin	0	1	1591	1
Bin	1	0	2251	1

Port:

MR_TST_WDATA_TST_WDATA(16)

	From	To	Count	Threshold
Bin	0	1	1629	1
Bin	1	0	2289	1

Port:

MR_TST_WDATA_TST_WDATA(15)

	From	To	Count	Threshold
Bin	0	1	1530	1
Bin	1	0	2190	1

Port:

MR_TST_WDATA_TST_WDATA(14)

	From	To	Count	Threshold
Bin	0	1	1465	1
Bin	1	0	2125	1

Port:

MR_TST_WDATA_TST_WDATA(13)

	From	To	Count	Threshold
Bin	0	1	1515	1
Bin	1	0	2175	1

Port:

MR_TST_WDATA_TST_WDATA(12)

	From	To	Count	Threshold
Bin	0	1	1598	1
Bin	1	0	2258	1

Port:

MR_TST_WDATA_TST_WDATA(11)

	From	To	Count	Threshold
Bin	0	1	1604	1
Bin	1	0	2264	1

Port:

MR_TST_WDATA_TST_WDATA(10)

	From	To	Count	Threshold
Bin	0	1	1606	1
Bin	1	0	2266	1

Port:

MR_TST_WDATA_TST_WDATA(9)

	From	To	Count	Threshold
Bin	0	1	1630	1
Bin	1	0	2290	1

Port:

MR_TST_WDATA_TST_WDATA(8)

	From	To	Count	Threshold
Bin	0	1	1644	1
Bin	1	0	2304	1

Port:

MR_TST_WDATA_TST_WDATA(7)

	From	To	Count	Threshold
Bin	0	1	1589	1
Bin	1	0	2249	1

Port:

MR_TST_WDATA_TST_WDATA(6)

	From	To	Count	Threshold
Bin	0	1	1527	1
Bin	1	0	2187	1

Port:

MR_TST_WDATA_TST_WDATA(5)

	From	To	Count	Threshold
Bin	0	1	1554	1
Bin	1	0	2214	1

Port:

MR_TST_WDATA_TST_WDATA(4)

	From	To	Count	Threshold
Bin	0	1	1594	1
Bin	1	0	2254	1

Port:

MR_TST_WDATA_TST_WDATA(3)

	From	To	Count	Threshold
Bin	0	1	1602	1
Bin	1	0	2262	1

Port:

MR_TST_WDATA_TST_WDATA(2)

	From	To	Count	Threshold
Bin	0	1	1615	1
Bin	1	0	2275	1

Port:

MR_TST_WDATA_TST_WDATA(1)

	From	To	Count	Threshold
Bin	0	1	1616	1
Bin	1	0	2276	1

Port:

MR_TST_WDATA_TST_WDATA(0)

	From	To	Count	Threshold
Bin	0	1	1677	1
Bin	1	0	2337	1

Port:

MR_TST_RDATA_TST_RDATA(31)

	From	To	Count	Threshold
Bin	0	1	471	1
Bin	1	0	1131	1

Port:

MR_TST_RDATA_TST_RDATA(30)

	From	To	Count	Threshold
Bin	0	1	467	1
Bin	1	0	1127	1

Port:

MR_TST_RDATA_TST_RDATA(29)

	From	To	Count	Threshold
Bin	0	1	473	1
Bin	1	0	1133	1

Port:

MR_TST_RDATA_TST_RDATA(28)

	From	To	Count	Threshold
Bin	0	1	510	1
Bin	1	0	1170	1

Port:

MR_TST_RDATA_TST_RDATA(27)

	From	To	Count	Threshold
Bin	0	1	503	1
Bin	1	0	1163	1

Port:

MR_TST_RDATA_TST_RDATA(26)

	From	To	Count	Threshold
Bin	0	1	517	1
Bin	1	0	1177	1

Port:

MR_TST_RDATA_TST_RDATA(25)

	From	To	Count	Threshold
Bin	0	1	526	1
Bin	1	0	1186	1

Port:

MR_TST_RDATA_TST_RDATA(24)

	From	To	Count	Threshold
Bin	0	1	515	1
Bin	1	0	1175	1

Port:

MR_TST_RDATA_TST_RDATA(23)

	From	To	Count	Threshold
Bin	0	1	525	1
Bin	1	0	1185	1

Port:

MR_TST_RDATA_TST_RDATA(22)

	From	To	Count	Threshold
Bin	0	1	518	1
Bin	1	0	1178	1

Port:

MR_TST_RDATA_TST_RDATA(21)

	From	To	Count	Threshold
Bin	0	1	533	1
Bin	1	0	1193	1

Port:

MR_TST_RDATA_TST_RDATA(20)

	From	To	Count	Threshold
Bin	0	1	525	1
Bin	1	0	1185	1

Port:

MR_TST_RDATA_TST_RDATA(19)

	From	To	Count	Threshold
Bin	0	1	505	1
Bin	1	0	1165	1

Port:

MR_TST_RDATA_TST_RDATA(18)

	From	To	Count	Threshold
Bin	0	1	503	1
Bin	1	0	1163	1

Port:

MR_TST_RDATA_TST_RDATA(17)

	From	To	Count	Threshold
Bin	0	1	493	1
Bin	1	0	1153	1

Port:

MR_TST_RDATA_TST_RDATA(16)

	From	To	Count	Threshold
Bin	0	1	494	1
Bin	1	0	1154	1

Port:

MR_TST_RDATA_TST_RDATA(15)

	From	To	Count	Threshold
Bin	0	1	497	1
Bin	1	0	1157	1

Port:

MR_TST_RDATA_TST_RDATA(14)

	From	To	Count	Threshold
Bin	0	1	490	1
Bin	1	0	1150	1

Port:

MR_TST_RDATA_TST_RDATA(13)

	From	To	Count	Threshold
Bin	0	1	492	1
Bin	1	0	1152	1

Port:

MR_TST_RDATA_TST_RDATA(12)

	From	To	Count	Threshold
Bin	0	1	507	1
Bin	1	0	1167	1

Port:

MR_TST_RDATA_TST_RDATA(11)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	1174	1

Port:

MR_TST_RDATA_TST_RDATA(10)

	From	To	Count	Threshold
Bin	0	1	504	1
Bin	1	0	1164	1

Port:

MR_TST_RDATA_TST_RDATA(9)

	From	To	Count	Threshold
Bin	0	1	484	1
Bin	1	0	1144	1

Port:

MR_TST_RDATA_TST_RDATA(8)

	From	To	Count	Threshold
Bin	0	1	498	1
Bin	1	0	1158	1

Port:

MR_TST_RDATA_TST_RDATA(7)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	1181	1

Port:

MR_TST_RDATA_TST_RDATA(6)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	1148	1

Port:

MR_TST_RDATA_TST_RDATA(5)

	From	To	Count	Threshold
Bin	0	1	513	1
Bin	1	0	1173	1

Port:

MR_TST_RDATA_TST_RDATA(4)

	From	To	Count	Threshold
Bin	0	1	475	1
Bin	1	0	1135	1

Port:

MR_TST_RDATA_TST_RDATA(3)

	From	To	Count	Threshold
Bin	0	1	491	1
Bin	1	0	1151	1

Port:

MR_TST_RDATA_TST_RDATA(2)

	From	To	Count	Threshold
Bin	0	1	483	1
Bin	1	0	1143	1

Port:

MR_TST_RDATA_TST_RDATA(1)

	From	To	Count	Threshold
Bin	0	1	515	1
Bin	1	0	1175	1

Port:

MR_TST_RDATA_TST_RDATA(0)

	From	To	Count	Threshold
Bin	0	1	498	1
Bin	1	0	1158	1

Port:

TXTB_PORT_A_ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	249017	1
Bin	1	0	24501565	1

Port:

TXTB_PORT_A_ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	396175	1
Bin	1	0	24354407	1

Port:

TXTB_PORT_A_ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	299014	1
Bin	1	0	24451568	1

Port:

TXTB_PORT_A_ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	24194275	1
Bin	1	0	556307	1

Port:

TXTB_PORT_A_ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	15940744	1
Bin	1	0	8809838	1

Port:

TXTB_PORT_A_DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	26356	1
Bin	1	0	762824	1

Port:

TXTB_PORT_A_DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	28657	1
Bin	1	0	760523	1

Port:

TXTB_PORT_A_DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	27152	1
Bin	1	0	762028	1

Port:

TXTB_PORT_A_DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	44044	1
Bin	1	0	745136	1

Port:

TXTB_PORT_A_DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	37637	1
Bin	1	0	751543	1

Port:

TXTB_PORT_A_DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	35980	1
Bin	1	0	753200	1

Port:

TXTB_PORT_A_DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	49211	1
Bin	1	0	739969	1

Port:

TXTB_PORT_A_DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	36691	1
Bin	1	0	752489	1

Port:

TXTB_PORT_A_DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	35471	1
Bin	1	0	753709	1

Port:

TXTB_PORT_A_DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	44528	1
Bin	1	0	744652	1

Port:

TXTB_PORT_A_DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	38824	1
Bin	1	0	750356	1

Port:

TXTB_PORT_A_DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	37253	1
Bin	1	0	751927	1

Port:

TXTB_PORT_A_DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	64725	1
Bin	1	0	724455	1

Port:

TXTB_PORT_A_DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	84831	1
Bin	1	0	704349	1

Port:

TXTB_PORT_A_DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	79950	1
Bin	1	0	709230	1

Port:

TXTB_PORT_A_DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	141786	1
Bin	1	0	647394	1

Port:

TXTB_PORT_A_DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	33296	1
Bin	1	0	755884	1

Port:

TXTB_PORT_A_DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	41814	1
Bin	1	0	747366	1

Port:

TXTB_PORT_A_DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	36216	1
Bin	1	0	752964	1

Port:

TXTB_PORT_A_DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	40217	1
Bin	1	0	748963	1

Port:

TXTB_PORT_A_DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	58401	1
Bin	1	0	730779	1

Port:

TXTB_PORT_A_DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	61314	1
Bin	1	0	727866	1

Port:

TXTB_PORT_A_DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	79096	1
Bin	1	0	710084	1

Port:

TXTB_PORT_A_DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	80705	1
Bin	1	0	708475	1

Port:

TXTB_PORT_A_DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	68788	1
Bin	1	0	720392	1

Port:

TXTB_PORT_A_DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	65064	1
Bin	1	0	724116	1

Port:

TXTB_PORT_A_DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	65949	1
Bin	1	0	723231	1

Port:

TXTB_PORT_A_DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	83106	1
Bin	1	0	706074	1

Port:

TXTB_PORT_A_DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	90500	1
Bin	1	0	698680	1

Port:

TXTB_PORT_A_DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	100212	1
Bin	1	0	688968	1

Port:

TXTB_PORT_A_DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	165652	1
Bin	1	0	623528	1

Port:

TXTB_PORT_A_DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	141015	1
Bin	1	0	648165	1

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold
Bin	0	1	640015	1
Bin	1	0	149165	1

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	45078	1
Bin	1	0	45738	1

Port:

TXTB_PORT_A_BE(3)

	From	To	Count	Threshold
Bin	0	1	24721305	1
Bin	1	0	28617	1

Port:

TXTB_PORT_A_BE(2)

	From	To	Count	Threshold
Bin	0	1	24721613	1
Bin	1	0	28309	1

Port:

TXTB_PORT_A_BE(1)

	From	To	Count	Threshold
Bin	0	1	24633047	1
Bin	1	0	116875	1

Port:

TXTB_PORT_A_BE(0)

	From	To	Count	Threshold
Bin	0	1	24634059	1
Bin	1	0	115863	1

Port:

TXTB_PORT_B_ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	10515	1
Bin	1	0	11175	1

Port:

TXTB_PORT_B_ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	346	1
Bin	1	0	1006	1

Port:

TXTB_PORT_B_ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	15447	1
Bin	1	0	16107	1

Port:

TXTB_PORT_B_ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	12158	1
Bin	1	0	12158	1

Port:

TXTB_PORT_B_ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	34271	1
Bin	1	0	34931	1

Port:

TXTB_PORT_B_DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	797	1
Bin	1	0	1417	1

Port:

TXTB_PORT_B_DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	824	1
Bin	1	0	1444	1

Port:

TXTB_PORT_B_DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	888	1
Bin	1	0	1508	1

Port:

TXTB_PORT_B_DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	2429	1
Bin	1	0	3038	1

Port:

TXTB_PORT_B_DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	2410	1
Bin	1	0	3009	1

Port:

TXTB_PORT_B_DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	2341	1
Bin	1	0	2951	1

Port:

TXTB_PORT_B_DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	2351	1
Bin	1	0	2956	1

Port:

TXTB_PORT_B_DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	2251	1
Bin	1	0	2861	1

Port:

TXTB_PORT_B_DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	2638	1
Bin	1	0	3241	1

Port:

TXTB_PORT_B_DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Port:

TXTB_PORT_B_DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	2750	1
Bin	1	0	3346	1

Port:

TXTB_PORT_B_DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Port:

TXTB_PORT_B_DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	2365	1
Bin	1	0	2962	1

Port:

TXTB_PORT_B_DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	2495	1
Bin	1	0	3095	1

Port:

TXTB_PORT_B_DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	1523	1
Bin	1	0	2137	1

Port:

TXTB_PORT_B_DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	1651	1
Bin	1	0	2267	1

Port:

TXTB_PORT_B_DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	1565	1
Bin	1	0	2180	1

Port:

TXTB_PORT_B_DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	1605	1
Bin	1	0	2219	1

Port:

TXTB_PORT_B_DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	1539	1
Bin	1	0	2155	1

Port:

TXTB_PORT_B_DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	1729	1
Bin	1	0	2341	1

Port:

TXTB_PORT_B_DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	1747	1
Bin	1	0	2361	1

Port:

TXTB_PORT_B_DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	1696	1
Bin	1	0	2311	1

Port:

TXTB_PORT_B_DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	2507	1
Bin	1	0	3109	1

Port:

TXTB_PORT_B_DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	1680	1
Bin	1	0	2293	1

Port:

TXTB_PORT_B_DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	3152	1
Bin	1	0	3741	1

Port:

TXTB_PORT_B_DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	2395	1
Bin	1	0	2993	1

Port:

TXTB_PORT_B_DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	2387	1
Bin	1	0	2999	1

Port:

TXTB_PORT_B_DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	1721	1
Bin	1	0	2337	1

Port:

TXTB_PORT_B_DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	1906	1
Bin	1	0	2506	1

Port:

TXTB_PORT_B_DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	2312	1
Bin	1	0	2911	1

Port:

TXTB_PORT_B_DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	2184	1
Bin	1	0	2778	1

Port:

TXTB_PORT_B_DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	2823	1
Bin	1	0	3416	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1541	1
Bin	1	0	2201	1

Signal:

TXTB_PORT_A_ADDRESS_I(4)

	From	To	Count	Threshold
Bin	0	1	249177	1
Bin	1	0	24490131	1

Signal:

TXTB_PORT_A_ADDRESS_I(3)

	From	To	Count	Threshold
Bin	0	1	396317	1
Bin	1	0	24342955	1

Signal:

TXTB_PORT_A_ADDRESS_I(2)

	From	To	Count	Threshold
Bin	0	1	299363	1
Bin	1	0	24440323	1

Signal:

TXTB_PORT_A_ADDRESS_I(1)

	From	To	Count	Threshold
Bin	0	1	24190026	1
Bin	1	0	550460	1

Signal:

TXTB_PORT_A_ADDRESS_I(0)

	From	To	Count	Threshold
Bin	0	1	15933488	1
Bin	1	0	8808687	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	45992	1
Bin	1	0	46757	1

Signal:

TXTB_PORT_A_DATA_I(31)

	From	To	Count	Threshold
Bin	0	1	26137	1
Bin	1	0	755481	1

Signal:

TXTB_PORT_A_DATA_I(30)

	From	To	Count	Threshold
Bin	0	1	28439	1
Bin	1	0	753177	1

Signal:

TXTB_PORT_A_DATA_I(29)

	From	To	Count	Threshold
Bin	0	1	26928	1
Bin	1	0	754680	1

Signal:

TXTB_PORT_A_DATA_I(28)

	From	To	Count	Threshold
Bin	0	1	43833	1
Bin	1	0	737801	1

Signal:

TXTB_PORT_A_DATA_I(27)

	From	To	Count	Threshold
Bin	0	1	37427	1
Bin	1	0	744199	1

Signal:

TXTB_PORT_A_DATA_I(26)

	From	To	Count	Threshold
Bin	0	1	35755	1
Bin	1	0	745867	1

Signal:

TXTB_PORT_A_DATA_I(25)

	From	To	Count	Threshold
Bin	0	1	48972	1
Bin	1	0	732670	1

Signal:

TXTB_PORT_A_DATA_I(24)

	From	To	Count	Threshold
Bin	0	1	36476	1
Bin	1	0	745188	1

Signal:

TXTB_PORT_A_DATA_I(23)

	From	To	Count	Threshold
Bin	0	1	35264	1
Bin	1	0	746390	1

Signal:

TXTB_PORT_A_DATA_I(22)

	From	To	Count	Threshold
Bin	0	1	44313	1
Bin	1	0	737319	1

Signal:

TXTB_PORT_A_DATA_I(21)

	From	To	Count	Threshold
Bin	0	1	38609	1
Bin	1	0	743041	1

Signal:

TXTB_PORT_A_DATA_I(20)

	From	To	Count	Threshold
Bin	0	1	37036	1
Bin	1	0	744618	1

Signal:

TXTB_PORT_A_DATA_I(19)

	From	To	Count	Threshold
Bin	0	1	64114	1
Bin	1	0	717522	1

Signal:

TXTB_PORT_A_DATA_I(18)

	From	To	Count	Threshold
Bin	0	1	80461	1
Bin	1	0	701208	1

Signal:

TXTB_PORT_A_DATA_I(17)

	From	To	Count	Threshold
Bin	0	1	78460	1
Bin	1	0	703192	1

Signal:

TXTB_PORT_A_DATA_I(16)

	From	To	Count	Threshold
Bin	0	1	137847	1
Bin	1	0	643805	1

Signal:

TXTB_PORT_A_DATA_I(15)

	From	To	Count	Threshold
Bin	0	1	33084	1
Bin	1	0	748556	1

Signal:

TXTB_PORT_A_DATA_I(14)

	From	To	Count	Threshold
Bin	0	1	41608	1
Bin	1	0	740040	1

Signal:

TXTB_PORT_A_DATA_I(13)

	From	To	Count	Threshold
Bin	0	1	36008	1
Bin	1	0	745634	1

Signal:

TXTB_PORT_A_DATA_I(12)

	From	To	Count	Threshold
Bin	0	1	40010	1
Bin	1	0	741652	1

Signal:

TXTB_PORT_A_DATA_I(11)

	From	To	Count	Threshold
Bin	0	1	58183	1
Bin	1	0	723447	1

Signal:

TXTB_PORT_A_DATA_I(10)

	From	To	Count	Threshold
Bin	0	1	61092	1
Bin	1	0	720542	1

Signal:

TXTB_PORT_A_DATA_I(9)

	From	To	Count	Threshold
Bin	0	1	78858	1
Bin	1	0	702782	1

Signal:

TXTB_PORT_A_DATA_I(8)

	From	To	Count	Threshold
Bin	0	1	80475	1
Bin	1	0	701165	1

Signal:

TXTB_PORT_A_DATA_I(7)

	From	To	Count	Threshold
Bin	0	1	68584	1
Bin	1	0	713108	1

Signal:

TXTB_PORT_A_DATA_I(6)

	From	To	Count	Threshold
Bin	0	1	64854	1
Bin	1	0	716800	1

Signal:

TXTB_PORT_A_DATA_I(5)

	From	To	Count	Threshold
Bin	0	1	65729	1
Bin	1	0	715917	1

Signal:

TXTB_PORT_A_DATA_I(4)

	From	To	Count	Threshold
Bin	0	1	81874	1
Bin	1	0	699730	1

Signal:

TXTB_PORT_A_DATA_I(3)

	From	To	Count	Threshold
Bin	0	1	88367	1
Bin	1	0	693275	1

Signal:

TXTB_PORT_A_DATA_I(2)

	From	To	Count	Threshold
Bin	0	1	97980	1
Bin	1	0	683671	1

Signal:

TXTB_PORT_A_DATA_I(1)

	From	To	Count	Threshold
Bin	0	1	161690	1
Bin	1	0	619955	1

Signal:

TXTB_PORT_A_DATA_I(0)

	From	To	Count	Threshold
Bin	0	1	137224	1
Bin	1	0	644504	1

Signal:

TXTB_PORT_B_ADDRESS_I(4)

	From	To	Count	Threshold
Bin	0	1	10675	1
Bin	1	0	11335	1

Signal:

TXTB_PORT_B_ADDRESS_I(3)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	1148	1

Signal:

TXTB_PORT_B_ADDRESS_I(2)

	From	To	Count	Threshold
Bin	0	1	15796	1
Bin	1	0	16456	1

Signal:

TXTB_PORT_B_ADDRESS_I(1)

	From	To	Count	Threshold
Bin	0	1	13033	1
Bin	1	0	13033	1

Signal:

TXTB_PORT_B_ADDRESS_I(0)

	From	To	Count	Threshold
Bin	0	1	35766	1
Bin	1	0	36426	1

Signal:

TXTB_PORT_B_DATA_OUT_I(31)

	From	To	Count	Threshold
Bin	0	1	797	1
Bin	1	0	1417	1

Signal:

TXTB_PORT_B_DATA_OUT_I(30)

	From	To	Count	Threshold
Bin	0	1	824	1
Bin	1	0	1444	1

Signal:

TXTB_PORT_B_DATA_OUT_I(29)

	From	To	Count	Threshold
Bin	0	1	888	1
Bin	1	0	1508	1

Signal:

TXTB_PORT_B_DATA_OUT_I(28)

	From	To	Count	Threshold
Bin	0	1	2429	1
Bin	1	0	3038	1

Signal:

TXTB_PORT_B_DATA_OUT_I(27)

	From	To	Count	Threshold
Bin	0	1	2410	1
Bin	1	0	3009	1

Signal:

TXTB_PORT_B_DATA_OUT_I(26)

	From	To	Count	Threshold
Bin	0	1	2341	1
Bin	1	0	2951	1

Signal:

TXTB_PORT_B_DATA_OUT_I(25)

	From	To	Count	Threshold
Bin	0	1	2351	1
Bin	1	0	2956	1

Signal:

TXTB_PORT_B_DATA_OUT_I(24)

	From	To	Count	Threshold
Bin	0	1	2251	1
Bin	1	0	2861	1

Signal:

TXTB_PORT_B_DATA_OUT_I(23)

	From	To	Count	Threshold
Bin	0	1	2638	1
Bin	1	0	3241	1

Signal:

TXTB_PORT_B_DATA_OUT_I(22)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Signal:

TXTB_PORT_B_DATA_OUT_I(21)

	From	To	Count	Threshold
Bin	0	1	2750	1
Bin	1	0	3346	1

Signal:

TXTB_PORT_B_DATA_OUT_I(20)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Signal:

TXTB_PORT_B_DATA_OUT_I(19)

	From	To	Count	Threshold
Bin	0	1	2365	1
Bin	1	0	2962	1

Signal:

TXTB_PORT_B_DATA_OUT_I(18)

	From	To	Count	Threshold
Bin	0	1	2495	1
Bin	1	0	3095	1

Signal:

TXTB_PORT_B_DATA_OUT_I(17)

	From	To	Count	Threshold
Bin	0	1	1523	1
Bin	1	0	2137	1

Signal:

TXTB_PORT_B_DATA_OUT_I(16)

	From	To	Count	Threshold
Bin	0	1	1651	1
Bin	1	0	2267	1

Signal:

TXTB_PORT_B_DATA_OUT_I(15)

	From	To	Count	Threshold
Bin	0	1	1565	1
Bin	1	0	2180	1

Signal:

TXTB_PORT_B_DATA_OUT_I(14)

	From	To	Count	Threshold
Bin	0	1	1605	1
Bin	1	0	2219	1

Signal:

TXTB_PORT_B_DATA_OUT_I(13)

	From	To	Count	Threshold
Bin	0	1	1539	1
Bin	1	0	2155	1

Signal:

TXTB_PORT_B_DATA_OUT_I(12)

	From	To	Count	Threshold
Bin	0	1	1729	1
Bin	1	0	2341	1

Signal:

TXTB_PORT_B_DATA_OUT_I(11)

	From	To	Count	Threshold
Bin	0	1	1747	1
Bin	1	0	2361	1

Signal:

TXTB_PORT_B_DATA_OUT_I(10)

	From	To	Count	Threshold
Bin	0	1	1696	1
Bin	1	0	2311	1

Signal:

TXTB_PORT_B_DATA_OUT_I(9)

	From	To	Count	Threshold
Bin	0	1	2507	1
Bin	1	0	3109	1

Signal:

TXTB_PORT_B_DATA_OUT_I(8)

	From	To	Count	Threshold
Bin	0	1	1680	1
Bin	1	0	2293	1

Signal:

TXTB_PORT_B_DATA_OUT_I(7)

	From	To	Count	Threshold
Bin	0	1	3152	1
Bin	1	0	3741	1

Signal:

TXTB_PORT_B_DATA_OUT_I(6)

	From	To	Count	Threshold
Bin	0	1	2395	1
Bin	1	0	2993	1

Signal:

TXTB_PORT_B_DATA_OUT_I(5)

	From	To	Count	Threshold
Bin	0	1	2387	1
Bin	1	0	2999	1

Signal:

TXTB_PORT_B_DATA_OUT_I(4)

	From	To	Count	Threshold
Bin	0	1	1721	1
Bin	1	0	2337	1

Signal:

TXTB_PORT_B_DATA_OUT_I(3)

	From	To	Count	Threshold
Bin	0	1	1906	1
Bin	1	0	2506	1

Signal:

TXTB_PORT_B_DATA_OUT_I(2)

	From	To	Count	Threshold
Bin	0	1	2312	1
Bin	1	0	2911	1

Signal:

TXTB_PORT_B_DATA_OUT_I(1)

	From	To	Count	Threshold
Bin	0	1	2184	1
Bin	1	0	2778	1

Signal:

TXTB_PORT_B_DATA_OUT_I(0)

	From	To	Count	Threshold
Bin	0	1	2823	1
Bin	1	0	3416	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	898	1

Signal:

PARITY_WORD(20)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2993	1

Signal:

PARITY_WORD(19)

	From	To	Count	Threshold
Bin	0	1	4	1
Bin	1	0	3086	1

Signal:

PARITY_WORD(18)

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	3078	1

Signal:

PARITY_WORD(17)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	3067	1

Signal:

PARITY_WORD(16)

	From	To	Count	Threshold
Bin	0	1	32	1
Bin	1	0	3058	1

Signal:

PARITY_WORD(15)

	From	To	Count	Threshold
Bin	0	1	38	1
Bin	1	0	3052	1

Signal:

PARITY_WORD(14)

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	3050	1

Signal:

PARITY_WORD(13)

	From	To	Count	Threshold
Bin	0	1	37	1
Bin	1	0	3053	1

Signal:

PARITY_WORD(12)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3046	1

Signal:

PARITY_WORD(11)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2982	1

Signal:

PARITY_WORD(10)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	3010	1

Signal:

PARITY_WORD(9)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	3000	1

Signal:

PARITY_WORD(8)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2968	1

Signal:

PARITY_WORD(7)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2975	1

Signal:

PARITY_WORD(6)

	From	To	Count	Threshold
Bin	0	1	174	1
Bin	1	0	2916	1

Signal:

PARITY_WORD(5)

	From	To	Count	Threshold
Bin	0	1	319	1
Bin	1	0	2771	1

Signal:

PARITY_WORD(4)

	From	To	Count	Threshold
Bin	0	1	703	1
Bin	1	0	2387	1

Signal:

PARITY_WORD(3)

	From	To	Count	Threshold
Bin	0	1	1313	1
Bin	1	0	1777	1

Signal:

PARITY_WORD(2)

	From	To	Count	Threshold
Bin	0	1	1683	1
Bin	1	0	1407	1

Signal:

PARITY_WORD(1)

	From	To	Count	Threshold
Bin	0	1	1075	1
Bin	1	0	2015	1

Signal:

PARITY_WORD(0)

	From	To	Count	Threshold
Bin	0	1	1119	1
Bin	1	0	1971	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	4119	1
Bin	1	0	3544	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	3874	1
Bin	1	0	4534	1

Uncovered expressions:

Excluded expressions:

"and" expression

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and

	Evaluated to	Count	Threshold
Bin	False	2875	1
Bin	True	1751	1

"and" expression

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	LHS	RHS	Count	Threshold
Bin	True	False	1513	1
Bin	True	True	238	1

"=" expression

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	26965	1
Bin	True	49561729	1

"=" expression

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	3810	1
Bin	True	185325	1

"=" expression

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	16698	1
Bin	True	1569925	1

"=" expression

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	3774	1
Bin	True	171858	1

"=" expression

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')

	Evaluated to	Count	Threshold
Bin	False	14539	1
Bin	True	2122	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: