NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TXT_BUF_TEST_DATA_PADDING_GEN(5)

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TXT_BUF_PADDING_INDEX_GEN_TRUE	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
TXT_BUF_PADDING_INDEX_GEN_FALSE	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TXT_BUF_TEST_DATA_PADDING_GEN(5)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

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