NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_BUS_SAMPLING_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_agent.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_BUS_SAMPLING_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (15/15) 100.0 % (17/17)

Details:

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Statement Branch Toggle Expression FSM state Functional

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Excluded toggles:

Port:

 CLK
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

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Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 156 to 157:

156:    -- psl bit_err_secondary_cov : cover 
157:    --  {bit_err_ssp_valid = '1' and bit_err_norm_valid = '0'}; 
Count: 551
Threshold: 1

PSL cover point on lines 159 to 160:

159:    -- psl bit_err_secondary_capt_cov : cover 
160:    --  {bit_err_ssp_valid = '1' and bit_err_ssp_capt_q = '1' and bit_err_ssp_condition = '0'}; 
Count: 549
Threshold: 1

PSL cover point on lines 162 to 163:

162:    -- psl bit_err_secondary_direct_cov : cover 
163:    --  {bit_err_ssp_valid = '1' and bit_err_ssp_capt_q = '0' and bit_err_ssp_condition = '1'}; 
Count: 2
Threshold: 1

PSL cover point on lines 170 to 172:

170:    -- psl sync_edge_but_prev_sample_the_same_cov : cover 
171:    --  {(rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and 
172:    --   (prev_rx_sample = rx_data) and (tq_edge = '1')}; 
Count: 4706
Threshold: 1

PSL cover point on lines 179 to 180:

179:    -- psl ssp_meas_n_offset_cov : cover 
180:    --  {mr_ssp_cfg_ssp_src = SSP_SRC_MEAS_N_OFFSET and tran_delay_meas = '1'}; 
Count: 455919
Threshold: 1

PSL cover point on lines 182 to 183:

182:    -- psl ssp_offset_cov : cover 
183:    --  {mr_ssp_cfg_ssp_src = SSP_SRC_OFFSET and tran_delay_meas = '1'}; 
Count: 8600
Threshold: 1

PSL cover point on lines 185 to 186:

185:    -- psl ssp_no_ssp_cov : cover 
186:    --  {mr_ssp_cfg_ssp_src = SSP_SRC_NO_SSP and tran_delay_meas = '1'}; 
Count: 2041773
Threshold: 1

PSL cover point on lines 190 to 191:

190:    -- psl ssp_offset_max_cov : cover 
191:    --  {ssp_delay = std_logic_vector(to_unsigned(C_SSP_DELAY_SAT_VAL, C_SSP_POS_WIDTH))}; 
Count: 184860
Threshold: 1

PSL cover point on lines 198 to 199:

198:    -- psl tx_data_cache_one_bit_on_fly_cov : cover 
199:    --  {write_pointer_q = read_pointer_q + 1}; 
Count: 2598850
Threshold: 1

PSL cover point on lines 201 to 202:

201:    -- psl tx_data_cache_two_bits_on_fly_cov : cover 
202:    --  {write_pointer_q = read_pointer_q + 2}; 
Count: 397799
Threshold: 1

PSL cover point on lines 204 to 205:

204:    -- psl tx_data_cache_three_bits_on_fly_cov : cover 
205:    --  {write_pointer_q = read_pointer_q + 3}; 
Count: 527610
Threshold: 1

PSL cover point on lines 207 to 208:

207:    -- psl tx_data_cache_four_bits_on_fly_cov : cover 
208:    --  {write_pointer_q = read_pointer_q + 4}; 
Count: 9973
Threshold: 1

PSL cover point on lines 210 to 211:

210:    -- psl tx_data_cache_five_bits_on_fly_cov : cover 
211:    --  {write_pointer_q = read_pointer_q + 5}; 
Count: 201272
Threshold: 1

PSL cover point on lines 213 to 214:

213:    -- psl tx_data_cache_six_bits_on_fly_cov : cover 
214:    --  {write_pointer_q = read_pointer_q + 6}; 
Count: 7581
Threshold: 1

PSL cover point on lines 216 to 217:

216:    -- psl tx_data_cache_seven_bits_on_fly_cov : cover 
217:    --  {write_pointer_q = read_pointer_q + 7}; 
Count: 487
Threshold: 1