NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_BUS_SAMPLING_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_bus_sampling.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_BUS_SAMPLING_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (15/15) 100.0 % (17/17)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin015275788681
Bin105275804601

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

156:    -- psl bit_err_secondary_cov : cover 
157:    --  {bit_err_ssp_valid = '1' and bit_err_norm_valid = '0'}; 
Count: 426
Threshold: 1

PSL cover point:

159:    -- psl bit_err_secondary_capt_cov : cover 
160:    --  {bit_err_ssp_valid = '1' and bit_err_ssp_capt_q = '1' and bit_err_ssp_condition = '0'}; 
Count: 425
Threshold: 1

PSL cover point:

162:    -- psl bit_err_secondary_direct_cov : cover 
163:    --  {bit_err_ssp_valid = '1' and bit_err_ssp_capt_q = '0' and bit_err_ssp_condition = '1'}; 
Count: 1
Threshold: 1

PSL cover point:

170:    -- psl sync_edge_but_prev_sample_the_same_cov : cover 
171:    --  {(rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and 
172:    --   (prev_rx_sample = rx_data) and (tq_edge = '1')}; 
Count: 4988
Threshold: 1

PSL cover point:

179:    -- psl ssp_meas_n_offset_cov : cover 
180:    --  {mr_ssp_cfg_ssp_src = SSP_SRC_MEAS_N_OFFSET and tran_delay_meas = '1'}; 
Count: 429094
Threshold: 1

PSL cover point:

182:    -- psl ssp_offset_cov : cover 
183:    --  {mr_ssp_cfg_ssp_src = SSP_SRC_OFFSET and tran_delay_meas = '1'}; 
Count: 10600
Threshold: 1

PSL cover point:

185:    -- psl ssp_no_ssp_cov : cover 
186:    --  {mr_ssp_cfg_ssp_src = SSP_SRC_NO_SSP and tran_delay_meas = '1'}; 
Count: 2043484
Threshold: 1

PSL cover point:

190:    -- psl ssp_offset_max_cov : cover 
191:    --  {ssp_delay = std_logic_vector(to_unsigned(C_SSP_DELAY_SAT_VAL, C_SSP_POS_WIDTH))}; 
Count: 129780
Threshold: 1

PSL cover point:

198:    -- psl tx_data_cache_one_bit_on_fly_cov : cover 
199:    --  {write_pointer_q = read_pointer_q + 1}; 
Count: 2700537
Threshold: 1

PSL cover point:

201:    -- psl tx_data_cache_two_bits_on_fly_cov : cover 
202:    --  {write_pointer_q = read_pointer_q + 2}; 
Count: 564083
Threshold: 1

PSL cover point:

204:    -- psl tx_data_cache_three_bits_on_fly_cov : cover 
205:    --  {write_pointer_q = read_pointer_q + 3}; 
Count: 460697
Threshold: 1

PSL cover point:

207:    -- psl tx_data_cache_four_bits_on_fly_cov : cover 
208:    --  {write_pointer_q = read_pointer_q + 4}; 
Count: 5596
Threshold: 1

PSL cover point:

210:    -- psl tx_data_cache_five_bits_on_fly_cov : cover 
211:    --  {write_pointer_q = read_pointer_q + 5}; 
Count: 178836
Threshold: 1

PSL cover point:

213:    -- psl tx_data_cache_six_bits_on_fly_cov : cover 
214:    --  {write_pointer_q = read_pointer_q + 6}; 
Count: 3313
Threshold: 1

PSL cover point:

216:    -- psl tx_data_cache_seven_bits_on_fly_cov : cover 
217:    --  {write_pointer_q = read_pointer_q + 7}; 
Count: 455
Threshold: 1