NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST.SEGM_END_REQ_CAPTURE(2)	100.0 % (10/10)	100.0 % (10/10)	N.A.	92.3 % (12/13)	N.A.	N.A.	96.9 % (32/33)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST.SEGM_END_REQ_CAPTURE(2)

100.0 % (10/10)

N.A.

92.3 % (12/13)

N.A.

96.9 % (32/33)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 198 to 199:

198:        segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else 
199:                                  req_input(i);

Count: 65517542
Threshold: 1

Signal assignment statement on line 198:

198: segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else
Count: 32761002
Threshold: 1

Signal assignment statement on line 199:

199: req_input(i);
Count: 32756540
Threshold: 1

If statement on lines 201 to 203:

201:        segm_end_req_capt_ce(i) <= 
202:            '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else 
203:            '0';

Count: 65517542
Threshold: 1

Signal assignment statement on line 202:

202: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else
Count: 42738960
Threshold: 1

Signal assignment statement on line 203:

203: '0';
Count: 22778582
Threshold: 1

If statement on lines 207 to 213:

207:            if (res_n = '0') then 
208:                segm_end_req_capt_q(i) <= '0'; 
...
212:                end if; 
213:            end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 208:

208: segm_end_req_capt_q(i) <= '0';
Count: 2424883
Threshold: 1

If statement on lines 210 to 212:

210:                if (segm_end_req_capt_ce(i) = '1') then 
211:                    segm_end_req_capt_q(i) <= segm_end_req_capt_d(i); 
212:                end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 211:

211: segm_end_req_capt_q(i) <= segm_end_req_capt_d(i);
Count: 29411861
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 198:

198: segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else

	Evaluated to	Count	Threshold
Bin	True	32761002	1
Bin	False	32756540	1

"if" / "when" / "else" condition on line 202:

202: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else

	Evaluated to	Count	Threshold
Bin	True	42738960	1
Bin	False	22778582	1

"if" / "when" / "else" condition on line 207:

207: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 209:

209: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 210:

210: if (segm_end_req_capt_ce(i) = '1') then

	Evaluated to	Count	Threshold
Bin	True	29411861	1
Bin	False	514379817	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

"or" expression on line 202:

 segm_end_req_capt_clr(i) = '1' or req_input(i) = '1' 
 <------------LHS------------->    <------RHS------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	True	False	0	1

Excluded expressions:

Covered expressions:

"=" expression on line 198:

segm_end_req_capt_clr(i) = '1'

	Evaluated to	Count	Threshold
Bin	False	32756540	1
Bin	True	32761002	1

"or" expression on line 202:

 segm_end_req_capt_clr(i) = '1' or req_input(i) = '1' 
 <------------LHS------------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	22778582	1
Bin	False	True	9977958	1

"=" expression on line 202:

segm_end_req_capt_clr(i) = '1'

	Evaluated to	Count	Threshold
Bin	False	32756540	1
Bin	True	32761002	1

"=" expression on line 202:

req_input(i) = '1'

	Evaluated to	Count	Threshold
Bin	False	22778582	1
Bin	True	9977958	1

"=" expression on line 207:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 210:

segm_end_req_capt_ce(i) = '1'

	Evaluated to	Count	Threshold
Bin	False	514379817	1
Bin	True	29411861	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST.SEGM_END_REQ_CAPTURE(2)

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 198 to 199:

Signal assignment statement on line 198:

Signal assignment statement on line 199:

If statement on lines 201 to 203:

Signal assignment statement on line 202:

Signal assignment statement on line 203:

If statement on lines 207 to 213:

Signal assignment statement on line 208:

If statement on lines 210 to 212:

Signal assignment statement on line 211:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 202:

"if" / "when" / "else" condition on line 207:

"if" / "when" / "else" condition on line 209:

"if" / "when" / "else" condition on line 210:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

"or" expression on line 202:

Excluded expressions:

Covered expressions:

"=" expression on line 198:

"or" expression on line 202:

"=" expression on line 202:

"=" expression on line 202:

"=" expression on line 207:

"=" expression on line 210:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: