File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- End of segment detector.
71: --
72: -- Purpose:
73: -- Detects end of current segment (TSEG1 or TSEG2) as a result of Hard-sync.,
74: -- or request from Bit segment meter. Provides signal for clearing Bit Time
75: -- counters. Only requests from Bit segment meter module which matches current
76: -- Bit-rate is considered (Nominal resynchronisation is considered in Nominal
77: -- Bit-rate, Data resynchronisation is considered in Data Bit-rate).
78: --------------------------------------------------------------------------------
79:
80: Library ieee;
81: use ieee.std_logic_1164.all;
82: use ieee.numeric_std.ALL;
83:
84: Library ctu_can_fd_rtl;
85: use ctu_can_fd_rtl.can_constants_pkg.all;
86: use ctu_can_fd_rtl.can_types_pkg.all;
87:
88: use ctu_can_fd_rtl.CAN_FD_register_map.all;
89: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
90:
91: entity segment_end_detector is
92: port (
93: -------------------------------------------------------------------------------------------
94: -- Clock and Asynchronous reset
95: -------------------------------------------------------------------------------------------
96: clk_sys : in std_logic;
97: res_n : in std_logic;
98:
99: -------------------------------------------------------------------------------------------
100: -- Control interface
101: -------------------------------------------------------------------------------------------
102: -- Sample control (Nominal, Data, Secondary)
103: sp_control : in std_logic_vector(1 downto 0);
104:
105: -- Hard synchronisation edge is valid
106: h_sync_edge_valid : in std_logic;
107:
108: -- Segment end request (Nominal)
109: exit_segm_req_nbt : in std_logic;
110:
111: -- Segment end request (Data)
112: exit_segm_req_dbt : in std_logic;
113:
114: -- Bit time FSM is in TSEG1
115: is_tseg1 : in std_logic;
116:
117: -- Bit time FSM is in TSEG2
118: is_tseg2 : in std_logic;
119:
120: -- Nominal Time quanta is active
121: tq_edge_nbt : in std_logic;
122:
123: -- Data Time quanta is active
124: tq_edge_dbt : in std_logic;
125:
126: -------------------------------------------------------------------------------------------
127: -- Status signals
128: -------------------------------------------------------------------------------------------
129: -- Segment end
130: segm_end : out std_logic;
131:
132: -- Hard Synchronisation is valid
133: h_sync_valid : out std_logic;
134:
135: -- Clear Bit time counters
136: bt_ctr_clear : out std_logic
137: );
138: end entity;
139:
140: architecture rtl of segment_end_detector is
141:
142: -------------------------------------------------------------------------------------------
143: -- Registers to capture requests for Hard-sync (0), NBT end of segment (1), DBT end of
144: -- segment (2)
145: -------------------------------------------------------------------------------------------
146: signal req_input : std_logic_vector(2 downto 1);
147: signal segm_end_req_capt_d : std_logic_vector(2 downto 1);
148: signal segm_end_req_capt_q : std_logic_vector(2 downto 1);
149: signal segm_end_req_capt_ce : std_logic_vector(2 downto 1);
150: signal segm_end_req_capt_clr : std_logic_vector(2 downto 1);
151:
152: -- ORed flags and combinational requests
153: signal segm_end_req_capt_dq : std_logic_vector(2 downto 1);
154:
155: -- Valid requests to end segment for each Sample type (Nominal, Data)
156: signal segm_end_nbt_valid : std_logic;
157: signal segm_end_dbt_valid : std_logic;
158: signal segm_end_nbt_dbt_valid : std_logic;
159:
160: -- Combinational requests to finish segment.
161: signal tseg1_end_req_valid : std_logic;
162: signal tseg2_end_req_valid : std_logic;
163: signal h_sync_valid_i : std_logic;
164:
165: -- End of segment, internal value
166: signal segment_end_i : std_logic;
167:
168: -- Nominal / Data Time quanta are active
169: signal nbt_tq_active : std_logic;
170: signal dbt_tq_active : std_logic;
171:
172: -- Bit time clear - internal value
173: signal bt_ctr_clear_i : std_logic;
174:
175: begin
176:
177: -----------------------------------------------------------------------------------------------
178: -- End of segment request capturing:
179: -- 1. NBT Resynchronisation requests segment end
180: -- 2. DBT Resynchronisation requests segment end
181: -----------------------------------------------------------------------------------------------
182: req_input(1) <= exit_segm_req_nbt;
183: req_input(2) <= exit_segm_req_dbt;
184:
185: -----------------------------------------------------------------------------------------------
186: -- Clearing requests:
187: -- 2. Segment end.
188: -- 3. Segment end.
189: -----------------------------------------------------------------------------------------------
190: segm_end_req_capt_clr(1) <= segment_end_i;
191: segm_end_req_capt_clr(2) <= segment_end_i;
192:
193: segm_end_req_capture : for i in 1 to 2 generate
194: begin
195:
196: -- Clear the flag upon real end of segment!
197: segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else
198: req_input(i);
199:
200: segm_end_req_capt_ce(i) <=
201: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else
202: '0';
203:
204: end_of_segm_req_proc : process(clk_sys, res_n)
205: begin
206: if (res_n = '0') then
207: segm_end_req_capt_q(i) <= '0';
208: elsif (rising_edge(clk_sys)) then
209: if (segm_end_req_capt_ce(i) = '1') then
210: segm_end_req_capt_q(i) <= segm_end_req_capt_d(i);
211: end if;
212: end if;
213: end process;
214:
215: end generate;
216:
217: -----------------------------------------------------------------------------------------------
218: -- Segment end request from NBT and DBT resynchronisation is valid for each Bit segment
219: -- differently.
220: -- For TSEG1:
221: -- 1. Combinational is valid! Here the request hangs (it is always due to comparison with Bit
222: -- time counter, so it does not have to be captured)!
223: -- For TSEG2:
224: -- 2. Combinational is valid, or captured request is valid. This accounts for edge in the same
225: -- clock cycle, as well as immediate exit occured in previous clock cycle during previous
226: -- Time quanta which was captured and is not present anymore!
227: -----------------------------------------------------------------------------------------------
228: segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1')
229: else
230: req_input(1) or segm_end_req_capt_q(1);
231:
232: segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1')
233: else
234: req_input(2) or segm_end_req_capt_q(2);
235:
236: -----------------------------------------------------------------------------------------------
237: -- Nominal and Data Time Quanta are active only when corresponding Sample type is set!
238: -----------------------------------------------------------------------------------------------
239: nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1')
240: else
241: '0';
242:
243: dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or
244: sp_control = SECONDARY_SAMPLE))
245: else
246: '0';
247:
248: -----------------------------------------------------------------------------------------------
249: -- Request to finish from either Nominal Bit-Rate re-synchronisation or Data Re-synchronisation
250: -- is valid when Sample control has Nominal or Data, Secondary sampling set!
251: -----------------------------------------------------------------------------------------------
252: segm_end_nbt_valid <=
253: '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1')
254: else
255: '0';
256:
257: segm_end_dbt_valid <=
258: '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1')
259: else
260: '0';
261:
262: segm_end_nbt_dbt_valid <=
263: '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1')
264: else
265: '0';
266:
267: -----------------------------------------------------------------------------------------------
268: -- Time segment end requests.
269: -----------------------------------------------------------------------------------------------
270: tseg1_end_req_valid <=
271: '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else
272: '0';
273:
274: tseg2_end_req_valid <=
275: '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1')
276: else
277: '0';
278:
279: -----------------------------------------------------------------------------------------------
280: -- Align Hard synchronisation request with Time Quanta. Note that Hard sync. is only allowed in
281: -- Nominal Bit-rat, thus use only Nominal Time Quanta edge!
282: -----------------------------------------------------------------------------------------------
283: h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1'))
284: else
285: '0';
286:
287: -----------------------------------------------------------------------------------------------
288: -- Overall segment end request occurs due to following conditions:
289: -- 1. Nominal Bit Time Resynchronisation signals end of segment, Nominal Time Quanta edge and
290: -- Sample control is NOMINAL_SAMPLE.
291: -- 2. Data Bit Time Resynchronisation signals end of segment, Data Time Quanta edge and Sample
292: -- control is either DATA_SAMPLE or SECONDARY_SAMPLE!
293: -- 3. Hard synchronisation induced end of segment in TSEG2! In TSEG1 segment is not ended,
294: -- only Bit Time counter is restarted!
295: -----------------------------------------------------------------------------------------------
296: segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or
297: tseg2_end_req_valid = '1' or
298: (h_sync_valid_i = '1' and is_tseg2 = '1'))
299: else
300: '0';
301:
302: -----------------------------------------------------------------------------------------------
303: -- Bit time counter clear:
304: -- 1. Segment end.
305: -- 2. Hard sync is valid. This covers the case when Hard-sync edge occurs in TSEG1 and TSEG1
306: -- does not end, it just gets re-started (bit time counter will be cleared)!
307: -----------------------------------------------------------------------------------------------
308: bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1')
309: else
310: '0';
311:
312: bt_ctr_clear <= bt_ctr_clear_i;
313: segm_end <= segment_end_i;
314: h_sync_valid <= h_sync_valid_i;
315:
316:
317: -----------------------------------------------------------------------------------------------
318: -----------------------------------------------------------------------------------------------
319: -- Assertions
320: -----------------------------------------------------------------------------------------------
321: -----------------------------------------------------------------------------------------------
322:
323: -- psl default clock is rising_edge(clk_sys);
324:
325: -- psl no_h_sync_not_in_time_quanta : assert never
326: -- (h_sync_edge_valid = '1' and tq_edge_nbt = '0');
327:
328: end architecture rtl;