Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage:
PSL cover point on lines 358 to 359:
358: -- psl traffic_ctrs_tx_inc_cov : cover
359: -- {tran_valid = '1'};
Count: 11112
Threshold: 1
PSL cover point on lines 361 to 362:
361: -- psl traffic_ctrs_rx_inc_cov : cover
362: -- {rec_valid = '1'};
Count: 15178
Threshold: 1
PSL cover point on lines 368 to 372:
368: -- psl tx_base_id_can_2_0_cov : cover
369: -- {tran_ident_type = BASE and
370: -- tran_frame_type = NORMAL_CAN and
371: -- tran_is_rtr = '0' and
372: -- tran_frame_valid = '1'};
Count: 43217078
Threshold: 1
PSL cover point on lines 374 to 378:
374: -- psl tx_extended_id_can_2_0_cov : cover
375: -- {tran_ident_type = EXTENDED and
376: -- tran_frame_type = NORMAL_CAN and
377: -- tran_is_rtr = '0' and
378: -- tran_frame_valid = '1'};
Count: 26356675
Threshold: 1
PSL cover point on lines 380 to 384:
380: -- psl tx_base_id_can_fd_cov : cover
381: -- {tran_ident_type = BASE and
382: -- tran_frame_type = FD_CAN and
383: -- tran_is_rtr = '0' and
384: -- tran_frame_valid = '1'};
Count: 65708889
Threshold: 1
PSL cover point on lines 386 to 390:
386: -- psl tx_extended_id_can_fd_cov : cover
387: -- {tran_ident_type = EXTENDED and
388: -- tran_frame_type = FD_CAN and
389: -- tran_is_rtr = '0' and
390: -- tran_frame_valid = '1'};
Count: 37810131
Threshold: 1
PSL cover point on lines 392 to 396:
392: -- psl tx_base_id_can_2_0_rtr_cov : cover
393: -- {tran_ident_type = BASE and
394: -- tran_frame_type = NORMAL_CAN and
395: -- tran_is_rtr = '1' and
396: -- tran_frame_valid = '1'};
Count: 3024213
Threshold: 1
PSL cover point on lines 398 to 402:
398: -- psl tx_extended_id_can_2_0_rtr_cov : cover
399: -- {tran_ident_type = EXTENDED and
400: -- tran_frame_type = NORMAL_CAN and
401: -- tran_is_rtr = '1' and
402: -- tran_frame_valid = '1'};
Count: 4596739
Threshold: 1
PSL cover point on lines 404 to 408:
404: -- psl tx_base_id_can_fd_rtr_cov : cover
405: -- {tran_ident_type = BASE and
406: -- tran_frame_type = FD_CAN and
407: -- tran_is_rtr = '1' and
408: -- tran_frame_valid = '1'};
Count: 506688
Threshold: 1
PSL cover point on lines 410 to 414:
410: -- psl tx_extended_id_can_fd_rtr_cov : cover
411: -- {tran_ident_type = EXTENDED and
412: -- tran_frame_type = FD_CAN and
413: -- tran_is_rtr = '1' and
414: -- tran_frame_valid = '1'};
Count: 475361
Threshold: 1
PSL cover point on lines 421 to 425:
421: -- psl rx_base_id_can_2_0_cov : cover
422: -- {rec_ident_type = BASE and
423: -- rec_frame_type = NORMAL_CAN and
424: -- rec_is_rtr = '0' and
425: -- store_metadata = '1'};
Count: 3692
Threshold: 1
PSL cover point on lines 427 to 431:
427: -- psl rx_extended_id_can_2_0_cov : cover
428: -- {rec_ident_type = EXTENDED and
429: -- rec_frame_type = NORMAL_CAN and
430: -- rec_is_rtr = '0' and
431: -- store_metadata = '1'};
Count: 2230
Threshold: 1
PSL cover point on lines 433 to 437:
433: -- psl rx_base_id_can_fd_cov : cover
434: -- {rec_ident_type = BASE and
435: -- rec_frame_type = FD_CAN and
436: -- rec_is_rtr = '0' and
437: -- store_metadata = '1'};
Count: 13449
Threshold: 1
PSL cover point on lines 439 to 443:
439: -- psl rx_extended_id_can_fd_cov : cover
440: -- {rec_ident_type = EXTENDED and
441: -- rec_frame_type = FD_CAN and
442: -- rec_is_rtr = '0' and
443: -- store_metadata = '1'};
Count: 2804
Threshold: 1
PSL cover point on lines 445 to 449:
445: -- psl rx_base_id_can_2_0_rtr_cov : cover
446: -- {rec_ident_type = BASE and
447: -- rec_frame_type = NORMAL_CAN and
448: -- rec_is_rtr = '1' and
449: -- store_metadata = '1'};
Count: 3401
Threshold: 1
PSL cover point on lines 451 to 455:
451: -- psl rx_extended_id_can_2_0_rtr_cov : cover
452: -- {rec_ident_type = EXTENDED and
453: -- rec_frame_type = NORMAL_CAN and
454: -- rec_is_rtr = '1' and
455: -- store_metadata = '1'};
Count: 2963
Threshold: 1
PSL cover point on lines 461 to 462:
461: -- psl bds_non_fix_to_fixed_change_cov : cover
462: -- {bds_trigger = '1' and non_fix_to_fix_chng = '1'};
Count: 13512
Threshold: 1
PSL cover point on lines 464 to 465:
464: -- psl bds_stuff_err_detect_cov : cover
465: -- {stuff_err_q = '1'};
Count: 20672
Threshold: 1
PSL cover point on lines 467 to 468:
467: -- psl bds_stuff_lvl_reached_regular_cov : cover
468: -- {stuff_lvl_reached = '1' and fixed_stuff = '0'};
Count: 27815045
Threshold: 1
PSL cover point on lines 470 to 471:
470: -- psl bds_stuff_lvl_reached_fixed_cov : cover
471: -- {stuff_lvl_reached = '1' and fixed_stuff = '1'};
Count: 4227213
Threshold: 1
PSL cover point on lines 478 to 479:
478: -- psl err_ctrs_inc_one_cov : cover
479: -- {inc_one = '1'};
Count: 12158
Threshold: 1
PSL cover point on lines 481 to 482:
481: -- psl err_ctrs_inc_eight_cov : cover
482: -- {inc_eight = '1'};
Count: 14903
Threshold: 1
PSL cover point on lines 484 to 485:
484: -- psl err_ctrs_dec_one_cov : cover
485: -- {dec_one = '1'};
Count: 26093
Threshold: 1
PSL cover point on lines 487 to 488:
487: -- psl err_ctrs_rec_saturation : cover
488: -- {(rx_err_ctr_inc < rx_err_ctr_q) and rx_err_ctr_ce = '1'};
Count: 19
Threshold: 1
PSL cover point on lines 497 to 498:
497: -- psl err_detect_bit_err_cov : cover
498: -- {bit_err = '1'};
Count: 9785
Threshold: 1
PSL cover point on lines 500 to 501:
500: -- psl err_detect_bit_err_arb_cov : cover
501: -- {bit_err_arb = '1'};
Count: 1455
Threshold: 1
PSL cover point on lines 503 to 504:
503: -- psl err_detect_stuff_err_cov : cover
504: -- {stuff_err = '1'};
Count: 20672
Threshold: 1
PSL cover point on lines 506 to 507:
506: -- psl err_detect_form_err_cov : cover
507: -- {form_err = '1'};
Count: 2733
Threshold: 1
PSL cover point on lines 509 to 510:
509: -- psl err_detect_ack_err_cov : cover
510: -- {ack_err = '1'};
Count: 1321
Threshold: 1
PSL cover point on lines 512 to 513:
512: -- psl err_detect_crc_err_cov : cover
513: -- {crc_err = '1'};
Count: 808
Threshold: 1
PSL cover point on lines 515 to 516:
515: -- psl err_detect_parity_err_cov : cover
516: -- {tran_frame_parity_error = '1'};
Count: 165
Threshold: 1
PSL cover point on lines 520 to 521:
520: -- psl err_capt_q_form_err_cov : cover
521: -- {err_capt_err_type_q = ERC_FRM_ERR};
Count: 36939052
Threshold: 1
PSL cover point on lines 523 to 524:
523: -- psl err_capt_q_bit_err_cov : cover
524: -- {err_capt_err_type_q = ERC_BIT_ERR};
Count: 332596023
Threshold: 1
PSL cover point on lines 526 to 527:
526: -- psl err_capt_q_crc_err_cov : cover
527: -- {err_capt_err_type_q = ERC_CRC_ERR};
Count: 724430
Threshold: 1
PSL cover point on lines 529 to 530:
529: -- psl err_capt_q_ack_err_cov : cover
530: -- {err_capt_err_type_q = ERC_ACK_ERR};
Count: 3906265
Threshold: 1
PSL cover point on lines 532 to 533:
532: -- psl err_capt_q_stuff_err_cov : cover
533: -- {err_capt_err_type_q = ERC_STUF_ERR};
Count: 170011916
Threshold: 1
PSL cover point on lines 535 to 536:
535: -- psl err_capt_q_prt_err_cov : cover
536: -- {err_capt_err_type_q = ERC_PRT_ERR};
Count: 821743
Threshold: 1
PSL cover point on lines 543 to 544:
543: -- psl err_ctr_inc_eight_A : cover
544: -- {primary_err = '1' and is_receiver = '1'};
Count: 155
Threshold: 1
PSL cover point on lines 546 to 548:
546: -- psl err_ctr_inc_eight_B : cover
547: -- {(act_err_ovr_flag = '1' and err_detected = '1') and
548: -- (not(primary_err = '1' and is_receiver = '1'))};
Count: 1381
Threshold: 1
PSL cover point on lines 550 to 553:
550: -- psl err_ctr_inc_eight_C : cover
551: -- {(is_transmitter = '1' and err_detected = '1' and err_ctrs_unchanged = '0') and
552: -- (not(act_err_ovr_flag = '1' and err_detected = '1')) and
553: -- (not(primary_err = '1' and is_receiver = '1'))};
Count: 13115
Threshold: 1
PSL cover point on lines 555 to 559:
555: -- psl err_ctr_inc_eight_D : cover
556: -- { (err_delim_late = '1' or bit_err_after_ack_err = '1') and
557: -- (not(is_transmitter = '1' and err_detected = '1' and err_ctrs_unchanged = '0')) and
558: -- (not(act_err_ovr_flag = '1' and err_detected = '1')) and
559: -- (not(primary_err = '1' and is_receiver = '1'))};
Count: 252
Threshold: 1
PSL cover point on lines 561 to 562:
561: -- psl err_ctr_dec_one_A : cover
562: -- {decrement_rec = '1' and tran_valid = '0'};
Count: 14981
Threshold: 1
PSL cover point on lines 564 to 565:
564: -- psl err_ctr_dec_one_B : cover
565: -- {decrement_rec = '0' and tran_valid = '1'};
Count: 11112
Threshold: 1
PSL cover point on lines 577 to 578:
577: -- psl err_frm_req_in_sof_cov : cover
578: -- {curr_state = s_pc_sof; err_frm_req = '1'};
Count: 55
Threshold: 1
PSL cover point on lines 580 to 581:
580: -- psl err_frm_req_in_s_pc_base_id_in_base_cov : cover
581: -- {curr_state = s_pc_base_id and err_frm_req = '1'};
Count: 2571
Threshold: 1
PSL cover point on lines 583 to 584:
583: -- psl err_frm_req_in_s_pc_ext_id_in_ext_id_cov : cover
584: -- {curr_state = s_pc_ext_id and err_frm_req = '1'};
Count: 1820
Threshold: 1
PSL cover point on lines 586 to 587:
586: -- psl err_frm_req_in_s_pc_ext_id_in_rtr_srr_r1_cov : cover
587: -- {curr_state = s_pc_rtr_srr_r1 and err_frm_req = '1'};
Count: 187
Threshold: 1
PSL cover point on lines 589 to 590:
589: -- psl err_frm_req_in_s_pc_ext_id_in_ide_cov : cover
590: -- {curr_state = s_pc_ide and err_frm_req = '1'};
Count: 158
Threshold: 1
PSL cover point on lines 592 to 593:
592: -- psl err_frm_req_in_s_pc_rtr_r1_cov : cover
593: -- {curr_state = s_pc_rtr_r1 and err_frm_req = '1'};
Count: 86
Threshold: 1
PSL cover point on lines 595 to 596:
595: -- psl err_frm_req_in_s_pc_edl_r1_cov : cover
596: -- {curr_state = s_pc_edl_r1 and err_frm_req = '1'};
Count: 100
Threshold: 1
PSL cover point on lines 598 to 599:
598: -- psl err_frm_req_in_s_pc_r0_ext_cov : cover
599: -- {curr_state = s_pc_r0_ext and err_frm_req = '1'};
Count: 65
Threshold: 1
PSL cover point on lines 601 to 602:
601: -- psl err_frm_req_in_s_pc_r0_fd_cov : cover
602: -- {curr_state = s_pc_r0_fd and err_frm_req = '1'};
Count: 127
Threshold: 1
PSL cover point on lines 604 to 605:
604: -- psl err_frm_req_in_s_pc_edl_r0_cov : cover
605: -- {curr_state = s_pc_edl_r0 and err_frm_req = '1'};
Count: 33
Threshold: 1
PSL cover point on lines 607 to 608:
607: -- psl err_frm_req_in_s_pc_esi_cov : cover
608: -- {curr_state = s_pc_esi and err_frm_req = '1'};
Count: 50
Threshold: 1
PSL cover point on lines 610 to 611:
610: -- psl err_frm_req_in_s_pc_dlc_cov : cover
611: -- {curr_state = s_pc_dlc and err_frm_req = '1'};
Count: 578
Threshold: 1
PSL cover point on lines 613 to 614:
613: -- psl err_frm_req_in_s_pc_data_cov : cover
614: -- {curr_state = s_pc_data and err_frm_req = '1'};
Count: 18250
Threshold: 1
PSL cover point on lines 616 to 617:
616: -- psl err_frm_req_in_s_pc_stuff_count_cov : cover
617: -- {curr_state = s_pc_stuff_count and err_frm_req = '1'};
Count: 264
Threshold: 1
PSL cover point on lines 619 to 620:
619: -- psl err_frm_req_in_s_pc_crc_cov : cover
620: -- {curr_state = s_pc_crc and err_frm_req = '1'};
Count: 1489
Threshold: 1
PSL cover point on lines 622 to 623:
622: -- psl err_frm_req_in_s_pc_crc_delim_cov : cover
623: -- {curr_state = s_pc_crc_delim and err_frm_req = '1'};
Count: 55
Threshold: 1
PSL cover point on lines 625 to 626:
625: -- psl err_frm_req_in_s_pc_ack_cov : cover
626: -- {curr_state = s_pc_ack and err_frm_req = '1'};
Count: 70
Threshold: 1
PSL cover point on lines 628 to 629:
628: -- psl err_frm_req_in_s_pc_eof_cov : cover
629: -- {curr_state = s_pc_eof and err_frm_req = '1'};
Count: 2160
Threshold: 1
PSL cover point on lines 631 to 632:
631: -- psl err_frm_req_in_s_pc_act_err_flag_cov : cover
632: -- {curr_state = s_pc_act_err_flag and err_frm_req = '1'};
Count: 1227
Threshold: 1
PSL cover point on lines 634 to 635:
634: -- psl err_frm_req_in_s_pc_ovr_flag_cov : cover
635: -- {curr_state = s_pc_ovr_flag and err_frm_req = '1'};
Count: 90
Threshold: 1
PSL cover point on lines 637 to 638:
637: -- psl err_frm_req_in_s_pc_ovr_delim_cov : cover
638: -- {curr_state = s_pc_ovr_delim and err_frm_req = '1'};
Count: 85
Threshold: 1
PSL cover point on lines 640 to 641:
640: -- psl err_frm_req_in_s_pc_err_delim_cov : cover
641: -- {curr_state = s_pc_err_delim and err_frm_req = '1'};
Count: 182
Threshold: 1
PSL cover point on lines 646 to 647:
646: -- psl ovr_from_eof_cov : cover
647: -- {curr_state = s_pc_eof and next_state = s_pc_ovr_flag};
Count: 136
Threshold: 1
PSL cover point on lines 649 to 650:
649: -- psl ovr_from_intermission_cov : cover
650: -- {curr_state = s_pc_intermission and next_state = s_pc_ovr_flag};
Count: 289
Threshold: 1
PSL cover point on lines 652 to 653:
652: -- psl ovr_from_err_delim : cover
653: -- {curr_state = s_pc_err_delim and next_state = s_pc_ovr_flag};
Count: 104
Threshold: 1
PSL cover point on lines 655 to 656:
655: -- psl ovr_from_ovr_delim_cov : cover
656: -- {curr_state = s_pc_ovr_delim and next_state = s_pc_ovr_flag};
Count: 32
Threshold: 1
PSL cover point on lines 661 to 662:
661: -- psl pex_on_fdf_enable_cov : cover
662: -- {pex_on_fdf_enable = '1' and mr_status_pexs = '1'};
Count: 60925
Threshold: 1
PSL cover point on lines 664 to 665:
664: -- psl pex_on_res_enable_cov : cover
665: -- {pex_on_res_enable = '1' and mr_status_pexs = '1'};
Count: 2529520
Threshold: 1
PSL cover point on lines 667 to 668:
667: -- psl pex_in_s_pc_r0_fd_cov : cover
668: -- {curr_state = s_pc_r0_fd and pexs_set = '1'};
Count: 5972
Threshold: 1
PSL cover point on lines 670 to 671:
670: -- psl pex_in_s_pc_edl_r1_cov : cover
671: -- {curr_state = s_pc_edl_r1 and pexs_set = '1'};
Count: 8
Threshold: 1
PSL cover point on lines 675 to 676:
675: -- psl classical_can_cov : cover
676: -- {curr_state = s_pc_base_id and mr_settings_pex = '0' and mr_mode_fde = '0'};
Count: 100590
Threshold: 1
PSL cover point on lines 678 to 679:
678: -- psl fd_tolerant_can_cov : cover
679: -- {curr_state = s_pc_base_id and mr_settings_pex = '1' and mr_mode_fde = '0'};
Count: 10144
Threshold: 1
PSL cover point on lines 681 to 682:
681: -- psl fd_enabled_can_cov : cover
682: -- {curr_state = s_pc_base_id and mr_settings_pex = '0' and mr_mode_fde = '1'};
Count: 43706039
Threshold: 1
PSL cover point on lines 684 to 685:
684: -- psl fd_enabled_with_pex : cover
685: -- {curr_state = s_pc_base_id and mr_settings_pex = '1' and mr_mode_fde = '1'};
Count: 126336
Threshold: 1
PSL cover point on lines 689 to 690:
689: -- psl iso_fd_cov : cover
690: -- {curr_state = s_pc_base_id and mr_settings_nisofd = '0'};
Count: 43872667
Threshold: 1
PSL cover point on lines 692 to 693:
692: -- psl non_iso_fd_cov : cover
693: -- {curr_state = s_pc_base_id and mr_settings_nisofd = '1'};
Count: 70442
Threshold: 1
PSL cover point on lines 697 to 698:
697: -- psl arb_lost_base_id_cov : cover
698: -- {curr_state = s_pc_base_id and arbitration_lost_i = '1'};
Count: 336
Threshold: 1
PSL cover point on lines 700 to 701:
700: -- psl arb_lost_rtr_srr_r1_cov : cover
701: -- {curr_state = s_pc_rtr_srr_r1 and arbitration_lost_i = '1'};
Count: 62
Threshold: 1
PSL cover point on lines 703 to 704:
703: -- psl arb_lost_ide_cov : cover
704: -- {curr_state = s_pc_ide and arbitration_lost_i = '1'};
Count: 50
Threshold: 1
PSL cover point on lines 706 to 707:
706: -- psl arb_lost_ext_id_cov : cover
707: -- {curr_state = s_pc_ext_id and arbitration_lost_i = '1'};
Count: 249
Threshold: 1
PSL cover point on lines 709 to 710:
709: -- psl arb_lost_rtr_r1_cov : cover
710: -- {curr_state = s_pc_rtr_r1 and arbitration_lost_i = '1'};
Count: 14
Threshold: 1
PSL cover point on lines 717 to 718:
717: -- psl reinteg_ctr_clr_cov : cover
718: -- {reinteg_ctr_clr = '1'};
Count: 4806
Threshold: 1
PSL cover point on lines 720 to 721:
720: -- psl reinteg_ctr_expired_cov : cover
721: -- {reinteg_ctr_expired = '1'};
Count: 56724
Threshold: 1
PSL cover point on lines 723 to 724:
723: -- psl reinteg_ctr_ce_A : cover
724: -- {(reinteg_ctr_clr = '1') and (not(reinteg_ctr_enable = '1' and rx_trigger = '1'))};
Count: 4806
Threshold: 1
PSL cover point on lines 726 to 727:
726: -- psl reinteg_ctr_ce_B : cover
727: -- {(not(reinteg_ctr_clr = '1')) and (reinteg_ctr_enable = '1' and rx_trigger = '1')};
Count: 21930
Threshold: 1
PSL cover point on lines 734 to 735:
734: -- psl rx_shift_reg_clear_cov : cover
735: -- {rx_clear = '1'};
Count: 55762
Threshold: 1
PSL cover point on lines 738 to 739:
738: -- psl rx_shift_reg_linear_mode_cov : cover
739: -- {rx_shift_in_sel = '0' and rx_shift_ena = "1111"};
Count: 116223624
Threshold: 1
PSL cover point on lines 741 to 742:
741: -- psl rx_shift_reg_byte_mode_byte_1_cov : cover
742: -- {rx_shift_in_sel = '1' and rx_shift_ena = "0001"};
Count: 49168978
Threshold: 1
PSL cover point on lines 744 to 745:
744: -- psl rx_shift_reg_byte_mode_byte_2_cov : cover
745: -- {rx_shift_in_sel = '1' and rx_shift_ena = "0010"};
Count: 40905530
Threshold: 1
PSL cover point on lines 747 to 748:
747: -- psl rx_shift_reg_byte_mode_byte_3_cov : cover
748: -- {rx_shift_in_sel = '1' and rx_shift_ena = "0100"};
Count: 38601648
Threshold: 1
PSL cover point on lines 750 to 751:
750: -- psl rx_shift_reg_byte_mode_byte_4_cov : cover
751: -- {rx_shift_in_sel = '1' and rx_shift_ena = "1000"};
Count: 36254166
Threshold: 1
PSL cover point on lines 753 to 754:
753: -- psl rx_shift_reg_store_base_id_cov : cover
754: -- {rx_store_base_id = '1'};
Count: 53181
Threshold: 1
PSL cover point on lines 756 to 757:
756: -- psl rx_shift_reg_store_ext_id_cov : cover
757: -- {rx_store_ext_id = '1'};
Count: 15808
Threshold: 1
PSL cover point on lines 759 to 760:
759: -- psl rx_shift_reg_store_ide_cov : cover
760: -- {rx_store_ide = '1'};
Count: 52832
Threshold: 1
PSL cover point on lines 762 to 763:
762: -- psl rx_shift_reg_store_rtr_cov : cover
763: -- {rx_store_rtr = '1'};
Count: 68716
Threshold: 1
PSL cover point on lines 765 to 766:
765: -- psl rx_shift_reg_store_edl_cov : cover
766: -- {rx_store_edl = '1'};
Count: 50792
Threshold: 1
PSL cover point on lines 768 to 769:
768: -- psl rx_shift_reg_store_dlc_cov : cover
769: -- {rx_store_dlc = '1'};
Count: 49790
Threshold: 1
PSL cover point on lines 771 to 772:
771: -- psl rx_shift_reg_store_esi_cov : cover
772: -- {rx_store_esi = '1'};
Count: 28525
Threshold: 1
PSL cover point on lines 774 to 775:
774: -- psl rx_shift_reg_store_brs_cov : cover
775: -- {rx_store_brs = '1'};
Count: 28575
Threshold: 1
PSL cover point on lines 777 to 778:
777: -- psl rx_shift_reg_store_stuff_count_cov : cover
778: -- {rx_store_stuff_count = '1'};
Count: 13272
Threshold: 1
PSL cover point on lines 785 to 786:
785: -- psl tx_shift_reg_load_base_id_cov : cover
786: -- {tx_load_base_id = '1'};
Count: 45441
Threshold: 1
PSL cover point on lines 788 to 789:
788: -- psl tx_shift_reg_load_extended_id_cov : cover
789: -- {tx_load_ext_id = '1'};
Count: 17628
Threshold: 1
PSL cover point on lines 791 to 792:
791: -- psl tx_shift_reg_load_dlc_cov : cover
792: -- {tx_load_dlc = '1'};
Count: 50368
Threshold: 1
PSL cover point on lines 794 to 795:
794: -- psl tx_shift_reg_load_data_word_cov : cover
795: -- {tx_load_data_word = '1'};
Count: 156909
Threshold: 1
PSL cover point on lines 797 to 798:
797: -- psl tx_shift_reg_load_stuff_count_cov : cover
798: -- {tx_load_stuff_count = '1'};
Count: 13536
Threshold: 1
PSL cover point on lines 800 to 801:
800: -- psl tx_shift_reg_load_crc_cov : cover
801: -- {tx_load_crc = '1'};
Count: 31276
Threshold: 1
PSL cover point on lines 803 to 804:
803: -- psl tx_shift_flip_fstc_cov : cover
804: -- {tran_frame_test.fstc = '1' and mr_mode_tstm = '1'};
Count: 466680
Threshold: 1
PSL cover point on lines 806 to 807:
806: -- psl tx_shift_flip_fcrc_cov : cover
807: -- {tran_frame_test.fcrc = '1' and mr_mode_tstm = '1'};
Count: 2356778
Threshold: 1
PSL cover point on lines 809 to 810:
809: -- psl tx_shift_flip_sdlc_cov : cover
810: -- {tran_frame_test.sdlc = '1' and mr_mode_tstm = '1'};
Count: 344439
Threshold: 1
PSL cover point on lines 812 to 813:
812: -- psl tx_shift_flip_fstc_disable_cov : cover
813: -- {tran_frame_test.fstc = '1' and mr_mode_tstm = '0'};
Count: 104955
Threshold: 1
PSL cover point on lines 815 to 816:
815: -- psl tx_shift_flip_fcrc_disable_cov : cover
816: -- {tran_frame_test.fcrc = '1' and mr_mode_tstm = '0'};
Count: 104955
Threshold: 1
PSL cover point on lines 818 to 819:
818: -- psl tx_shift_flip_sdlc_disable_cov : cover
819: -- {tran_frame_test.sdlc = '1' and mr_mode_tstm = '0'};
Count: 104955
Threshold: 1