NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_TX_ARBITRATOR_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_tx_arbitrator.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average
G_EACH_BUF(0) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(1) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(2) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(3) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(4) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(5) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(6) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)
G_EACH_BUF(7) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_TX_ARBITRATOR_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (23/23) 100.0 % (25/25)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin015275788681
Bin105275804601

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

175:    -- psl txtb_ttm_ena_cov : cover 
176:    --    {mr_mode_tttm = '1' and tran_frame_valid = '1'}; 
Count: 377952
Threshold: 1

PSL cover point:

177:    -- psl txtb_ttm_dis_cov : cover 
178:    --    {mr_mode_tttm = '0' and tran_frame_valid = '1'}; 
Count: 181613225
Threshold: 1

PSL cover point:

180:    -- psl txtb_txbbm_ena_cov : cover 
181:    --    {mr_mode_txbbm = '1' and tran_frame_valid = '1'}; 
Count: 439635
Threshold: 1

PSL cover point:

182:    -- psl txtb_txbbm_dis_cov : cover 
183:    --    {mr_mode_txbbm = '0' and tran_frame_valid = '1'}; 
Count: 181551542
Threshold: 1

PSL cover point:

189:    -- psl txt_buf_change_cov : cover 
190:    --    {txtb_changed = '1' and txtb_hw_cmd.lock = '1'} 
191:    --    report "TX Buffer changed between two frames"; 
Count: 10007
Threshold: 1

PSL cover point:

193:    -- psl txt_buf_sim_chng_and_lock_cov : cover 
194:    --    {select_index_changed = '1' and txtb_hw_cmd.lock = '1'}; 
Count: 23
Threshold: 1

PSL cover point:

200:    -- psl txtb_lock_arb_sel_low_cov : cover 
201:    --  {curr_state = s_arb_sel_low_ts and txtb_hw_cmd_lock = '1'}; 
Count: 10
Threshold: 1

PSL cover point:

203:    -- psl txtb_lock_arb_sel_hi_cov : cover 
204:    --  {curr_state = s_arb_sel_upp_ts and txtb_hw_cmd_lock = '1'}; 
Count: 10
Threshold: 1

PSL cover point:

206:    -- psl txtb_lock_arb_sel_ftw_cov : cover 
207:    --  {curr_state = s_arb_sel_ftw and txtb_hw_cmd_lock = '1'}; 
Count: 2
Threshold: 1

PSL cover point:

209:    -- psl txtb_lock_arb_sel_ffw_cov : cover 
210:    --  {curr_state = s_arb_sel_ffw and txtb_hw_cmd_lock = '1'}; 
Count: 2
Threshold: 1

PSL cover point:

212:    -- psl txtb_lock_arb_sel_idw_cov : cover 
213:    --  {curr_state = s_arb_sel_idw and txtb_hw_cmd_lock = '1'}; 
Count: 2
Threshold: 1

PSL cover point:

215:    -- psl txtb_lock_arb_sel_validated_cov : cover 
216:    --  {curr_state = s_arb_validated and txtb_hw_cmd_lock = '1'}; 
Count: 24790
Threshold: 1

PSL cover point:

222:    -- psl txtb_not_available_arb_sel_low_cov : cover 
223:    --  {curr_state = s_arb_sel_low_ts and select_buf_avail = '0'}; 
Count: 186
Threshold: 1

PSL cover point:

225:    -- psl txtb_not_available_arb_sel_upp_cov : cover 
226:    --  {curr_state = s_arb_sel_upp_ts and select_buf_avail = '0'}; 
Count: 112
Threshold: 1

PSL cover point:

228:    -- psl txtb_not_available_arb_sel_ffw_cov : cover 
229:    --  {curr_state = s_arb_sel_ffw and select_buf_avail = '0'}; 
Count: 90
Threshold: 1

PSL cover point:

231:    -- psl txtb_not_available_arb_sel_ftw_cov : cover 
232:    --  {curr_state = s_arb_sel_ftw and select_buf_avail = '0'}; 
Count: 90
Threshold: 1

PSL cover point:

234:    -- psl txtb_not_available_arb_sel_idw_cov : cover 
235:    --  {curr_state = s_arb_sel_idw and select_buf_avail = '0'}; 
Count: 78
Threshold: 1

PSL cover point:

237:    -- psl txtb_not_available_arb_validated_cov : cover 
238:    --  {curr_state = s_arb_validated and select_buf_avail = '0'}; 
Count: 225
Threshold: 1

PSL cover point:

244:    -- psl txtb_ffw_parity_error_cov : cover 
245:    --  {curr_state = s_arb_sel_ffw and parity_error_vld = '1'}; 
Count: 44
Threshold: 1

PSL cover point:

247:    -- psl txtb_idw_parity_error_cov : cover 
248:    --  {curr_state = s_arb_sel_idw and parity_error_vld = '1'}; 
Count: 78
Threshold: 1

PSL cover point:

250:    -- psl txtb_lts_parity_error_cov : cover 
251:    --  {curr_state = s_arb_sel_low_ts and parity_error_vld = '1'}; 
Count: 66
Threshold: 1

PSL cover point:

253:    -- psl txtb_uts_parity_error_cov : cover 
254:    --  {curr_state = s_arb_sel_upp_ts and parity_error_vld = '1'}; 
Count: 33
Threshold: 1

PSL cover point:

260:    -- psl txt_buf_wait_till_timestamp_cov : cover 
261:    --    {curr_state = s_arb_sel_upp_ts and fsm_wait_state_q = '0' and 
262:    --     timestamp_valid = '0'}; 
Count: 368595
Threshold: 1