NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_TIME_CFG_CAPTURE_INST	100.0 % (25/25)	100.0 % (14/14)	100.0 % (270/270)	100.0 % (20/20)	N.A.	N.A.	100.0 % (329/329)
SYNCHRONISATION_CHECKER_INST	100.0 % (27/27)	100.0 % (24/24)	100.0 % (34/34)	100.0 % (68/68)	N.A.	N.A.	100.0 % (153/153)
BIT_SEGMENT_METER_NBT_INST	100.0 % (66/66)	100.0 % (48/48)	100.0 % (96/96)	100.0 % (161/161)	N.A.	N.A.	100.0 % (371/371)
BIT_TIME_COUNTERS_NBT_INST	100.0 % (23/23)	100.0 % (20/20)	100.0 % (114/114)	100.0 % (29/29)	N.A.	N.A.	100.0 % (186/186)
BIT_SEGMENT_METER_DBT_INST	100.0 % (66/66)	100.0 % (48/48)	100.0 % (90/90)	100.0 % (161/161)	N.A.	N.A.	100.0 % (365/365)
BIT_TIME_COUNTERS_DBT_INST	100.0 % (23/23)	100.0 % (20/20)	100.0 % (108/108)	100.0 % (29/29)	N.A.	N.A.	100.0 % (180/180)
SEGMENT_END_DETECTOR_INST	100.0 % (63/63)	100.0 % (44/44)	100.0 % (72/72)	99.1 % (119/120)	N.A.	N.A.	99.6 % (298/299)
BIT_TIME_FSM_INST	100.0 % (29/29)	100.0 % (26/26)	100.0 % (18/18)	100.0 % (18/18)	100.0 % (6/6)	N.A.	100.0 % (97/97)
TRIGGER_GENERATOR_INST	100.0 % (16/16)	100.0 % (14/14)	100.0 % (22/22)	100.0 % (18/18)	N.A.	N.A.	100.0 % (70/70)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BIT_TIME_CFG_CAPTURE_INST

100.0 % (25/25)

100.0 % (14/14)

100.0 % (270/270)

100.0 % (20/20)

N.A.

100.0 % (329/329)

SYNCHRONISATION_CHECKER_INST

100.0 % (27/27)

100.0 % (24/24)

100.0 % (34/34)

100.0 % (68/68)

N.A.

100.0 % (153/153)

BIT_SEGMENT_METER_NBT_INST

100.0 % (66/66)

100.0 % (48/48)

100.0 % (96/96)

100.0 % (161/161)

N.A.

100.0 % (371/371)

BIT_TIME_COUNTERS_NBT_INST

100.0 % (23/23)

100.0 % (20/20)

100.0 % (114/114)

100.0 % (29/29)

N.A.

100.0 % (186/186)

BIT_SEGMENT_METER_DBT_INST

100.0 % (66/66)

100.0 % (48/48)

100.0 % (90/90)

100.0 % (161/161)

N.A.

100.0 % (365/365)

BIT_TIME_COUNTERS_DBT_INST

100.0 % (23/23)

100.0 % (20/20)

100.0 % (108/108)

100.0 % (29/29)

N.A.

100.0 % (180/180)

SEGMENT_END_DETECTOR_INST

100.0 % (63/63)

100.0 % (44/44)

100.0 % (72/72)

99.1 % (119/120)

N.A.

99.6 % (298/299)

BIT_TIME_FSM_INST

100.0 % (29/29)

100.0 % (26/26)

100.0 % (18/18)

100.0 % (6/6)

N.A.

100.0 % (97/97)

TRIGGER_GENERATOR_INST

100.0 % (16/16)

100.0 % (14/14)

100.0 % (22/22)

100.0 % (18/18)

N.A.

100.0 % (70/70)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST	100.0 % (3/3)	100.0 % (2/2)	100.0 % (314/314)	N.A.	N.A.	N.A.	100.0 % (319/319)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST

100.0 % (3/3)

100.0 % (2/2)

100.0 % (314/314)

N.A.

100.0 % (319/319)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 474 to 475:

474:    tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else 
475:               tq_edge_dbt;

Count: 238026454
Threshold: 1

Signal assignment statement on line 474:

474: tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else
Count: 154917132
Threshold: 1

Signal assignment statement on line 475:

475: tq_edge_dbt;
Count: 83109322
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 474:

474: tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	154917132	1
Bin	False	83109322	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_BTR_PROP

	Element	From	To	Threshold	Excluded due to
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_PH1

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_PH2

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_SJW

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PROP_FD

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PH1_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PH2_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_BRP_FD

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_SJW_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SYNC_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SYNC_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

NO_POS_RESYNC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

NBT_CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DBT_CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

RX_TRIGGERS

	Element	From	To	Count	Threshold
Bin	(1)	0	1	34160725	1
Bin	(1)	1	0	34163927	1
Bin	(0)	0	1	22764474	1
Bin	(0)	1	0	45558577	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11391077	1
Bin	1	0	11392677	1

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	110674758	1
Bin	1	0	110676356	1

Signal:

TSEG1_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	457	1
Bin	(7)	1	0	2056	1
Bin	(6)	0	1	1689	1
Bin	(6)	1	0	3290	1
Bin	(5)	0	1	807	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	934	1
Bin	(4)	1	0	2533	1
Bin	(3)	0	1	5981	1
Bin	(3)	1	0	4381	1
Bin	(2)	0	1	4191	1
Bin	(2)	1	0	5782	1
Bin	(1)	0	1	1064	1
Bin	(1)	1	0	2662	1
Bin	(0)	0	1	3761	1
Bin	(0)	1	0	2160	1

Signal:

TSEG2_NBT

	Element	From	To	Count	Threshold
Bin	(5)	0	1	204	1
Bin	(5)	1	0	1803	1
Bin	(4)	0	1	349	1
Bin	(4)	1	0	1947	1
Bin	(3)	0	1	313	1
Bin	(3)	1	0	1912	1
Bin	(2)	0	1	3874	1
Bin	(2)	1	0	2275	1
Bin	(1)	0	1	3412	1
Bin	(1)	1	0	5003	1
Bin	(0)	0	1	2160	1
Bin	(0)	1	0	559	1

Signal:

BRP_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	13	1
Bin	(7)	1	0	1614	1
Bin	(6)	0	1	14	1
Bin	(6)	1	0	1615	1
Bin	(5)	0	1	12	1
Bin	(5)	1	0	1613	1
Bin	(4)	0	1	16	1
Bin	(4)	1	0	1617	1
Bin	(3)	0	1	4831	1
Bin	(3)	1	0	3242	1
Bin	(2)	0	1	930	1
Bin	(2)	1	0	2524	1
Bin	(1)	0	1	4762	1
Bin	(1)	1	0	3170	1
Bin	(0)	0	1	2317	1
Bin	(0)	1	0	3915	1

Signal:

SJW_NBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	204	1
Bin	(4)	1	0	1802	1
Bin	(3)	0	1	271	1
Bin	(3)	1	0	1869	1
Bin	(2)	0	1	971	1
Bin	(2)	1	0	2568	1
Bin	(1)	0	1	2624	1
Bin	(1)	1	0	1032	1
Bin	(0)	0	1	3116	1
Bin	(0)	1	0	4713	1

Signal:

TSEG1_DBT

	Element	From	To	Count	Threshold
Bin	(6)	0	1	2330	1
Bin	(6)	1	0	3929	1
Bin	(5)	0	1	267	1
Bin	(5)	1	0	1868	1
Bin	(4)	0	1	2412	1
Bin	(4)	1	0	4011	1
Bin	(3)	0	1	3645	1
Bin	(3)	1	0	5235	1
Bin	(2)	0	1	4399	1
Bin	(2)	1	0	2798	1
Bin	(1)	0	1	3281	1
Bin	(1)	1	0	1689	1
Bin	(0)	0	1	2073	1
Bin	(0)	1	0	472	1

Signal:

TSEG2_DBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	288	1
Bin	(4)	1	0	1887	1
Bin	(3)	0	1	315	1
Bin	(3)	1	0	1914	1
Bin	(2)	0	1	1212	1
Bin	(2)	1	0	2802	1
Bin	(1)	0	1	1734	1
Bin	(1)	1	0	134	1
Bin	(0)	0	1	3870	1
Bin	(0)	1	0	2269	1

Signal:

BRP_DBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	18	1
Bin	(7)	1	0	1619	1
Bin	(6)	0	1	29	1
Bin	(6)	1	0	1630	1
Bin	(5)	0	1	17	1
Bin	(5)	1	0	1618	1
Bin	(4)	0	1	30	1
Bin	(4)	1	0	1631	1
Bin	(3)	0	1	27	1
Bin	(3)	1	0	1628	1
Bin	(2)	0	1	4843	1
Bin	(2)	1	0	3254	1
Bin	(1)	0	1	757	1
Bin	(1)	1	0	2355	1
Bin	(0)	0	1	2600	1
Bin	(0)	1	0	4192	1

Signal:

SJW_DBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	247	1
Bin	(4)	1	0	1845	1
Bin	(3)	0	1	289	1
Bin	(3)	1	0	1887	1
Bin	(2)	0	1	916	1
Bin	(2)	1	0	2513	1
Bin	(1)	0	1	2568	1
Bin	(1)	1	0	976	1
Bin	(0)	0	1	953	1
Bin	(0)	1	0	2550	1

Signal:

SEGMENT_END

	From	To	Count	Threshold
Bin	0	1	22778918	1
Bin	1	0	22780519	1

Signal:

H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	56587	1
Bin	1	0	58188	1

Signal:

IS_TSEG1

	From	To	Count	Threshold
Bin	0	1	11388526	1
Bin	1	0	11388516	1

Signal:

IS_TSEG2

	From	To	Count	Threshold
Bin	0	1	11382222	1
Bin	1	0	11383822	1

Signal:

RESYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	800361	1
Bin	1	0	801962	1

Signal:

H_SYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	56587	1
Bin	1	0	58188	1

Signal:

SEGM_COUNTER_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	567762	1
Bin	(7)	1	0	569363	1
Bin	(6)	0	1	916230	1
Bin	(6)	1	0	917830	1
Bin	(5)	0	1	3211003	1
Bin	(5)	1	0	3212604	1
Bin	(4)	0	1	6924096	1
Bin	(4)	1	0	6925697	1
Bin	(3)	0	1	15395931	1
Bin	(3)	1	0	15397530	1
Bin	(2)	0	1	37654100	1
Bin	(2)	1	0	37655700	1
Bin	(1)	0	1	78939501	1
Bin	(1)	1	0	78941099	1
Bin	(0)	0	1	151143099	1
Bin	(0)	1	0	151144695	1

Signal:

SEGM_COUNTER_DBT

	Element	From	To	Count	Threshold
Bin	(6)	0	1	141676	1
Bin	(6)	1	0	143277	1
Bin	(5)	0	1	246419	1
Bin	(5)	1	0	248020	1
Bin	(4)	0	1	788153	1
Bin	(4)	1	0	789754	1
Bin	(3)	0	1	4490644	1
Bin	(3)	1	0	4492245	1
Bin	(2)	0	1	11946010	1
Bin	(2)	1	0	11947611	1
Bin	(1)	0	1	22767194	1
Bin	(1)	1	0	22768795	1
Bin	(0)	0	1	42344657	1
Bin	(0)	1	0	42346257	1

Signal:

EXIT_SEGM_REQ_NBT

	From	To	Count	Threshold
Bin	0	1	16470592	1
Bin	1	0	16472193	1

Signal:

EXIT_SEGM_REQ_DBT

	From	To	Count	Threshold
Bin	0	1	9978252	1
Bin	1	0	9979853	1

Signal:

TQ_EDGE_NBT

	From	To	Count	Threshold
Bin	0	1	98927208	1
Bin	1	0	98928806	1

Signal:

TQ_EDGE_DBT

	From	To	Count	Threshold
Bin	0	1	34598889	1
Bin	1	0	34600480	1

Signal:

RX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22778488	1
Bin	1	0	22780089	1

Signal:

TX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22772413	1
Bin	1	0	22774013	1

Signal:

START_EDGE

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8083	1

Signal:

BT_CTR_CLEAR

	From	To	Count	Threshold
Bin	0	1	22813000	1
Bin	1	0	22814601	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

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